CN107562563B

CN107562563B - Nand Flash control method and device

Info

Publication number: CN107562563B
Application number: CN201610515960.0A
Authority: CN
Inventors: 牛鹏举; 吴少校; 宁利臣; 孙丞廉
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2021-06-15
Anticipated expiration: 2036-07-01
Also published as: CN107562563A

Abstract

The invention provides a Nand Flash control method and a Nand Flash control device, wherein the method comprises the following steps: adopting a check algorithm with the error correction digit larger than the preset error correction digit to encode data to be written to obtain at least two groups of write-encoded data, sequentially writing the at least two groups of write-encoded data into main areas of at least two adjacent pages of Nand Flash, wherein each group of write-encoded data comprises: and the write check data and the write check code corresponding to the write check data. According to the technical scheme, the write check code and the corresponding write check data are stored in the main area together, so that the limitation of the number of bytes of the ECC check code and the limited storage space of the Nand Flash oob area is broken, the ECC algorithm capability is improved, and the reliability of the operation data is enhanced.

Description

Nand Flash control method and device

Technical Field

The invention relates to the technical field of computers, in particular to a Nand Flash control method and device.

Background

Nand Flash (Nand Flash) is a non-volatile storage technology, i.e., data can be stored even after power is off, and is widely used in the industry. The Nand Flash reads and writes data in units of pages and erases data in units of blocks, and during the use process, the Nand Flash occasionally has a bit reversal phenomenon due to the inherent characteristics of hardware, that is, a certain bit in the Nand Flash changes from 1 to 0 or from 0 to 1.

An Error Checking and Correcting (ECC) algorithm is an Error detection and Correction algorithm suitable for Nand Flash, and can realize data Checking under certain conditions and ensure data correctness. Therefore, when the page of Nand Flash is read and written, the ECC algorithm interface function is called by software or the ECC function integrated on hardware is started, the check result generated by the ECC algorithm is stored in the oob area of the page, and the check result is processed, so that whether the operation data is in error can be detected, and the correctness of the operation data is further ensured.

However, the check results generated by the current ECC algorithm are stored in the shared (oob) area of the Nand Flash page, while the physical page structure size of the current general-purpose large-capacity Nand Flash is (2k +64) bytes (byte), wherein the size of the oob area is 64byte, which is used for storing not only the check results generated by the ECC algorithm, but also computer system data or user data, and therefore, the size of the check results that can be stored in the oob area is limited, which affects the checking capability of the ECC algorithm.

Disclosure of Invention

The invention provides a Nand Flash control method and device, which aim to solve the problem that the checking capability of an ECC algorithm is influenced because the storage space of an oob area on the Nand Flash is limited.

The invention provides a Nand Flash control method, which comprises the following steps:

encoding data to be written by adopting a check algorithm with the error correction digit larger than the preset error correction digit to obtain at least two groups of write encoded data, wherein each group of write encoded data comprises: the write check data and a write check code corresponding to the write check data;

and writing the write check data included in each group of write-coded data in the at least two groups of write-coded data and the write check code corresponding to the write check data into the main areas of at least two adjacent pages of the Nand Flash in sequence.

The invention also provides a Nand Flash control device, which comprises:

the encoding module is used for encoding data to be written by adopting a check algorithm with the error correction digit being greater than the preset error correction digit to obtain at least two groups of write-encoded data, wherein each group of write-encoded data comprises: the write check data and a write check code corresponding to the write check data;

and the write operation module is used for sequentially writing write check data included in each group of write-coded data in the at least two groups of write-coded data obtained by the coding module and write check codes corresponding to the write check data into main areas of at least two adjacent pages of the Nand Flash.

According to the Nand Flash control method and device provided by the invention, at least two groups of write-coded data obtained by coding data to be written by adopting a check algorithm with the error correction digit larger than the preset error correction digit are sequentially written into the main areas of at least two adjacent pages of the Nand Flash, and each group of write-coded data comprises the write-check data and the corresponding check code thereof, so that the write-check code and the corresponding write-check data thereof are stored in the main areas together, the limitation that the byte number of the ECC check code and the storage space of the oob area on the Nand Flash are limited is broken, the ECC algorithm capability is improved, and the reliability of operation data is enhanced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic flow chart of a Nand Flash control method according to a first embodiment of the present invention;

FIG. 2 is a schematic layout diagram of a Nand Flash physical page in the Nand Flash control method provided by the present invention;

FIG. 3 is a schematic flow chart of a Nand Flash control method according to a second embodiment of the present invention;

FIG. 4 is a schematic flow chart of a Nand Flash control method according to a third embodiment of the present invention;

FIG. 5 is a schematic structural diagram of data storage distribution in the Nand Flash control method provided by the present invention;

FIG. 6 is a schematic flow chart of a fourth embodiment of a Nand Flash control method provided by the present invention;

FIG. 7 is a schematic flow chart of a fifth embodiment of a Nand Flash control method provided by the present invention;

FIG. 8 is a schematic structural diagram of a Nand Flash control device according to a first embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a Nand Flash control device according to a second embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a Nand Flash control device according to a third embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a fourth embodiment of a Nand Flash control device provided in the present invention;

FIG. 12 is a schematic flow chart of a fifth embodiment of the Nand Flash control device provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The internal memory of Nand Flash (Nand Flash) adopts a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) structure, in which a Floating Gate is provided, and is a unit for really storing data. The Nand Flash consists of a plurality of blocks, each block comprises a plurality of pages, the pages are basic units of read-write operation of the Nand Flash, and the blocks are basic units of erase operation of the Nand Flash.

When the Nand Flash is used, due to the inherent characteristics of hardware of the Nand Flash, a bit reversal phenomenon occasionally occurs, that is, a certain bit in the original Nand Flash changes, namely, the bit changes from 1 to 0 or from 0 to 1.

The bit reversal phenomenon of Nand Flash is mainly caused by the following reasons/effects:

(1) drift effect (Drifting Effects)

The drift effect means that the voltage value of the charge (cell) stored in Nand Flash changes and becomes different from the original value.

(2) Program-Disturb induced Errors (Program-Disturb Errors)

An error caused by program disturb is also called an over-program effect (over-program effect), which means that when a program operation, i.e. a write operation, is performed on a certain page, a certain bit of a non-relevant other page is caused to jump.

(3) Errors due to Read Disturb (Read-Disturb Errors)

The error generated by the read operation interference means that when a page is subjected to data read operation, data of a certain bit in the data is permanently changed, namely, a bit value of a corresponding page on the Nand Flash is changed.

Because data is easy to generate errors when read and write operations are performed on Nand Flash, Error Checking and Correction (ECC for short) algorithm is usually adopted to realize Error detection and Correction of Nand Flash in order to ensure the correctness of data. However, when Nand Flash is operated, whether ECC is used or not needs to be determined according to the importance of stored data, and specifically, when Nand Flash is applied to multimedia information, such as storing audio and video files, the problem caused by bit reversal is not serious or even negligible; when the method is used for storing an operating system, a configuration file and other sensitive information, an ECC algorithm is needed to check the data and ensure the correctness of the data.

If the operation time sequence and the circuit stability of the Nand Flash do not have problems, the Nand Flash generally does not cause the whole block or page to be in error when in error, but only one or a few bits in the whole page are in error. Generally, an ECC algorithm can correct 1 bit error and detect 2 bit errors, and the calculation speed is fast, but it cannot correct errors of 1 bit or more, and cannot guarantee detection of errors of 2 bits or more.

The implementation principle of an ECC algorithm is described as follows:

the ECC algorithm operates on 256 bytes of data at a time, including column checking and row checking. Performing XOR on each Bit to be checked, and if the result is 0, indicating that the Bit to be checked contains an even number of 1 s; if the result is 1, it indicates that an odd number of 1 s is contained. Table 1 shows ECC column check rules, and table 2 shows ECC row check rules, and as shown in tables 1 and 2, 256 bytes of data form a matrix of 256 rows and 8 columns, and each element of the matrix represents one Bit.

TABLE 1 ECC column check rule schematic

As shown in table 1, CP0 to CP5 have 6 Bit bits and indicate Column Parity (Column polarity), CP0 has the polarity of 0, 2, 4, and 6 columns, CP1 has the polarity of 1, 3, 5, and 7 columns, CP2 has the polarity of 0, 1, 4, and 5 columns, CP3 has the polarity of 2, 3, 6, and 7 columns, CP4 has the polarity of 0, 1, 2, and 3 columns, and CP5 has the polarity of 4, 5, 6, and 7 columns.

CP0 is formulated as: CP0 is equal to Bit0^ Bit2^ Bit4^ Bit6, that is, CP0 indicates that 256 Bit bits in the 0 th column are XOR-ed with 256 Bit bits in the 2 nd column, XOR-ed with each Bit in the 4 th and 6 th columns, and thus CP0 is the result of XOR-ing 256 x 4 and 1024 Bit bits. Similarly, CP 1-CP 5 are formulated as follows:

CP1＝Bit1^Bit3^Bit5^Bit7；CP2＝Bit0^Bit1^Bit4^Bit5；

CP3＝Bit2^Bit3^Bit6^Bit7；CP4＝Bit0^Bit1^Bit2^Bit3；

CP5＝Bit4^Bit5^Bit6^Bit7。

TABLE 2 ECC Row check rule schematic

As shown in table 2, RP0 to RP15 are 16 Bit bits, and represent Row Parity (Row polarity), as follows:

RP0 is the polarity of bytes 0, 2, 4, 6, …, 252, 254;

RP1 is the polarity of bytes 1, 3, 5, 7, …, 253, 255;

RP2 is the polarity of bytes 0, 1, 4, 5, 8, 9, …, 252, 253 (process 2 bytes, skip 2 bytes);

RP3 is the polarity of bytes 2, 3, 6, 7, 10, 11, …, 254, 255 (2 bytes are skipped, 2 bytes are processed);

similarly, RP4 indicates that 4 bytes are processed, skipping 4 bytes;

RP5 indicates 4 bytes are skipped and processed;

RP6 indicates that 8 Bytes are processed, 8 Bytes are skipped;

RP7 indicates 8 Bytes are skipped and 8 Bytes are processed;

RP8 indicates that 16 Bytes are processed, 16 are skipped;

RP9 indicates 16 bytes are skipped and processed;

RP10 indicates handling 32 Bytes, skipping 32 Bytes;

RP11 indicates that 32 Bytes are skipped and processed;

RP12 indicates that 64 Bytes are processed, 64 Bytes are skipped;

RP13 indicates 64 Bytes are skipped and 64 Bytes are processed;

RP14 indicates that 128 bytes are processed, 128 bytes are skipped;

RP15 indicates 128 bytes are skipped and 128 bytes are processed.

As can be seen, since each Bit of RP0 to RP15 is 128 bytes (i.e., 128 rows), RP0 to RP15 are the exclusive-or results of 128 × 8 to 1024 bits.

In summary, a total of 6-Bit column check results and 16-Bit row check results, for a total of 22 bits, are generated for 256 bytes of data. Specifically, when data is written in a page of Nand Flash, 22 bits of original ECC checksum are generated every 256 bytes and stored in an oob area of the page; when data is read from Nand Flash, generating 22 bits of new ECC checksum every 256 bytes, carrying out bitwise XOR on the original ECC checksum and the new ECC checksum, and if the result is 0, indicating that no error exists; if 11 bit bits in the 3-byte XOR result are 1, a bit error exists and can be corrected; if only 1 bit is 1 in the exclusive or result of 3 bytes, it indicates that oob area is faulty; other cases all indicate that an uncorrectable error has occurred.

However, the above only gives the principle of implementing the checking of the ECC algorithm, and the checking capability of the data is different for different ECC algorithms, and the generated checking result is also different. Therefore, an ECC algorithm with a stronger checking capability generates more Bit checking results, and accordingly requires more space to store the checking results, while the spare area (oob area) of the Nand Flash physical page is limited, and the size of the checking results that can be stored in the oob area is limited, which affects the checking capability of the ECC algorithm.

Aiming at the problems, the embodiment of the invention provides a Nand Flash control method and device, which are used for solving the problem that the checking capability of an ECC algorithm is influenced because the storage space of an oob area on the Nand Flash is limited.

FIG. 1 is a schematic flow chart of a Nand Flash control method according to an embodiment of the present invention. As shown in fig. 1, the Nand Flash control method provided in the embodiment of the present invention includes:

step 101: the data to be written is encoded by adopting a check algorithm with the error correction digit larger than the preset error correction digit to obtain at least two groups of write encoded data, wherein each group of write encoded data comprises the following steps: and the write check data and the write check code corresponding to the write check data.

Specifically, since the existing ECC algorithm can correct only 1 bit of errors, 2 bit of errors are detected. Therefore, in the embodiment of the present invention, the size of the preset error correction bit number may be selected to be 2 bits or the like. It should be noted that the preset error correction bits are only used for representing the capability of the ECC algorithm to correct and detect errors, and the preset error correction bits are not limited in the present invention.

The principle of the ECC algorithm is that the original checksum generated during data writing and the new checksum generated during reading are subjected to bitwise XOR, so that if the checking capability of the ECC algorithm is to be improved, firstly, a checking algorithm with the error correction digit larger than the preset error correction digit is adopted during writing, and therefore, the embodiment of the invention mainly aims at the writing operation of Nand Flash.

Optionally, the check algorithm with the error correction bits larger than the preset error correction bits may be a reed-solomon RS (204, 188) encoding algorithm, and the encoding algorithm is operated according to groups, that is, each group of encoded data is stored as a whole in a length of 204 bytes, wherein the first 188 bytes are write check data, and the last 16 bytes are write check codes corresponding to the first 188 bytes of write check data.

Because the minimum reading and writing unit of the Nand Flash is a page, the data size of each page is 2048 bytes, and the upper layer application uses the data of the whole page to read and write, when the coding algorithm is used for coding the data to be written, at least two groups of writing and coding data can be obtained, and each group of writing and coding data comprises the writing and checking data and the writing and checking code corresponding to the writing and checking data. The length of each set of write-encoded data, the size of the write-check data, and the size of the write-check code depend on the capability of the check algorithm, and the embodiments of the present invention do not limit them.

Step 102: and writing the write check data included in each group of the at least two groups of write-coded data and the write check code corresponding to the write check data into the main areas of at least two adjacent pages of the Nand Flash in sequence.

As can be seen from the above analysis, the write-coded data includes write-check data and a write-check code corresponding to the write-check data, and in general, existing file systems or upper layer software operate and manage Nand Flash in units of whole pages, and at this time, when the write-coded data is operated, the write-check data stored in each page will become less, so that it is necessary to write the at least two sets of write-coded data into main areas of at least two adjacent pages of the Nand Flash in sequence to implement reading and writing of the whole page of data.

FIG. 2 is a schematic diagram of the arrangement of Nand Flash physical pages in the Nand Flash control method provided by the present invention. As shown in FIG. 2, one page of Nand Flash includes: a Main Area (Main Area)21 and a Spare Area (Spare Area)22, the Spare Area 22 is also called oob Area, correspondingly, the size of a page includes page size (pagesize) and oob Area size (oobsize), the size of the Main Area 21 is called page size, the size of the Spare Area 22 is called oob Area size, and the operation of upper layer application on Nand Flash is performed by using the page size as bytes, therefore, in order to improve the error correction capability of the ECC algorithm, the invention stores the generated write check code and the write check data at the position of the bytes corresponding to the page size, so that extra space is needed to store the occupied bytes, and since the size of oob Area generally does not satisfy the requirement, as shown in fig. 2, at least two adjacent pages of Nand Flash are merged into one page for storing at least two groups of encoded data, and further, the reading and writing of the whole page of data are realized.

According to the Nand Flash control method provided by the embodiment of the invention, at least two groups of write-coded data obtained by coding data to be written by adopting the check algorithm with the error correction digit larger than the preset error correction digit are sequentially written into the main areas of at least two adjacent pages of the Nand Flash, and each group of write-coded data comprises the write-check data and the corresponding check code thereof, so that the write-check data and the corresponding write-check code thereof are stored in the main areas together, the limitation that the byte number of the ECC check code and the storage space of the oob area on the Nand Flash are limited is broken, the capability of the ECC algorithm is improved, and the reliability of the operation data is enhanced.

FIG. 3 is a flowchart illustrating a second embodiment of a Nand Flash control method provided by the present invention. The second embodiment of the invention further explains the Nand Flash control method on the basis of the first embodiment. As shown in fig. 3, in the Nand Flash control method provided in the embodiment of the present invention, in step 102, that is, before writing the write check data included in each of the at least two sets of write-coded data and the write check code corresponding to the write check data into the main areas of at least two adjacent pages of the Nand Flash in sequence, the method further includes:

step 301: determining the Nand Flash page number occupied by at least two groups of write-coded data according to the group number of the write-coded data and the size of each group of write-coded data;

specifically, the total size of the write-coded data can be obtained by multiplying the number of groups of the write-coded data by the size of each group of the write-coded data, and then the number of Nand Flash pages occupied by the at least two groups of the write-coded data can be determined according to the physical page size of the Nand Flash.

Step 302: acquiring a physical page address corresponding to data to be written according to the acquired operation command function;

the upper layer application determines the operation type, the size of the operation data and the physical page address corresponding to the operation by issuing the operation command function, so that the physical page address corresponding to the data to be written specified by the upper layer application can be determined according to the obtained operation command function, and the write operation page address in the actual application can be accurately positioned only by determining the physical page address corresponding to the data to be written.

Step 303: and determining the write operation page addresses corresponding to the at least two groups of write coded data according to the Nand Flash page number occupied by the at least two groups of write coded data and the physical page address corresponding to the data to be written.

From the above analysis, when the upper layer application performs the read-write operation with the whole page as the unit, the upper layer application corresponds to at least two groups of write-coded data, and the at least two groups of write-coded data occupy the size of at least two adjacent pages, so in order to ensure that the data can be accurately written into the Nand Flash, it is necessary to determine the write-operation page addresses corresponding to the at least two groups of write-coded data according to the number of pages of the Nand Flash occupied by the at least two groups of write-coded data corresponding to the data to be written and the physical page address corresponding to the data to be written, thereby laying a foundation for the subsequent accurate write-in of the data.

For example, if the Nand Flash pages occupied by the at least two sets of write-coded data are two pages, the physical page address is multiplied by 2 to obtain the write operation page address corresponding to the at least two sets of write-coded data.

According to the Nand Flash control method provided by the embodiment of the invention, the number of Nand Flash pages occupied by all write-coded data can be determined by utilizing the number of groups of the write-coded data and the size of each group of the write-coded data, and the write operation page addresses corresponding to at least two groups of write-coded data can be determined according to the number of the Nand Flash pages and the obtained physical page addresses corresponding to the data to be written, so that a foundation is laid for accurately writing the write-coded data into pages, the compatibility of the existing file system and other software is realized, and the reliability of the data is enhanced.

FIG. 4 is a flowchart illustrating a third embodiment of a Nand Flash control method provided by the present invention. The third embodiment of the invention is a further description of the Nand Flash control method on the basis of the above embodiments. As shown in fig. 4, in the Nand Flash control method provided in the embodiment of the present invention, step 102 is to sequentially write the write check data included in each of the at least two sets of write-coded data and the write check code corresponding to the write check data into the main areas of at least two adjacent pages of the Nand Flash, and specifically includes:

step 401: determining the in-page offset corresponding to the data to be written according to the acquired operation command function;

specifically, the operation command function issued by the upper layer application further includes an intra-page offset corresponding to the data to be written, so that the intra-page offset specified by the upper layer application can be determined according to the obtained operation command function, and the writing start position of the data to be written in a certain physical page is further determined.

Step 402: determining the writing initial positions of at least two groups of writing coded data in the page corresponding to the writing operation page address according to the writing operation page address and the offset in the page;

by determining the address of the page to be written in the second embodiment and the offset in the page corresponding to the data to be written obtained in step 401, the accurate address corresponding to the at least two sets of write-encoded data, that is, the write start position in the page corresponding to the address of the page to be written can be accurately determined.

Step 403: and writing the write check data included in each group of the at least two groups of write-coded data and the write check code corresponding to the write check data into the main areas of the page corresponding to the address of the write operation page and the adjacent page from the write starting position in sequence.

Specifically, according to the writing rule of the page, the writing start position is firstly positioned, and the at least two groups of writing coded data are written into the main areas of the page corresponding to the address of the page to be written and the adjacent page from the start position in sequence, so that the writing operation on the Nand Flash is realized.

According to the Nand Flash control method provided by the embodiment of the invention, the write initial positions of at least two groups of write-coded data in the page corresponding to the write operation page address are obtained by obtaining the page offset corresponding to the data to be written and the determined write operation page address, and then the at least two groups of write-coded data are sequentially written into the main areas of the page corresponding to the write operation page address and the adjacent page from the write initial positions, so that the data writing is realized, the limitation that the check result can only be stored in the oob area of the page is broken through, and the reliability of the data in the read-write process is improved.

Further, in the Nand Flash control method provided in the above embodiment, if the preset error correction bit number is 1 byte, the check algorithm with the error correction bit number greater than the preset error correction bit number includes: a Reed-Solomon RS (204, 188) encoding algorithm for error checking ECC; the number of error correction bits of the RS (204, 188) encoding algorithm of the ECC is less than or equal to 8 bytes.

FIG. 5 is a schematic structural diagram of data storage distribution in the Nand Flash control method provided by the present invention. As shown in fig. 5, in this embodiment, taking the size of each page of Nand Flash as 2048 bytes as an example for explanation, after data to be written is encoded by using an RS (204, 188) encoding algorithm of ECC, since the length of each set of write-encoded data is 204, only 10 sets of write-encoded data can be written in each page, and the first 2040 bytes of each page are occupied. In each group of write-coded data, 16 bytes are stored in each 188 byte to greatly improve the checking and error correcting capability of the ECC algorithm, correspondingly, the RS (204, 188) coding algorithm of the ECC can correct 8 bytes at most, and the number of error bits in each byte can be 1-8.

Correspondingly, in step 101, that is, encoding data to be written by using a check algorithm with an error correction bit number greater than a preset error correction bit number to obtain at least two groups of write-encoded data, specifically, the method includes:

and coding the data to be written by adopting an RS (204, 188) coding algorithm of ECC to obtain 11 groups of write-coded data, wherein the first 188 bytes of each group of write-coded data are write check data, and the last 16 bytes of each group of write-coded data are write check codes.

When the existing file system or upper layer software reads, writes and manages Nand Flash, operation and management are performed by taking a whole page as a unit, therefore, if the size of the page is 2048 bytes, the size of data to be written should be 2048 bytes, and when data to be written is coded by adopting an RS (204, 188) coding algorithm of ECC, only 188 bytes of write check data of each group of write code data are valid, so that 2048 bytes of data can be coded to form 11 groups of write code data, the first 188 bytes of each group of write code data are write check data, and the last 16 bytes of each group of write code data are write check code corresponding to the write check data. Correspondingly, after the RS (204, 188) coding algorithm of the ECC is adopted, the utilization rate of the Nand Flash is 188/204.

Further, in the Nand Flash control method provided in the above embodiment, in step 101, that is, before encoding data to be written by using a check algorithm whose error correction bit number is greater than a preset error correction bit number to obtain at least two groups of write-encoded data, the method further includes:

obtaining an operation command function aiming at Nand Flash, wherein the operation command function comprises the following steps: operation command type, logical page address, offset within page;

specifically, the upper layer application notifies the Nand Flash of what operation is to be executed by issuing an operation command function, and therefore, the operation command function for the Nand Flash needs to be obtained first, and the operation command function includes an operation command type, a logical page address and an offset in a page, so as to specify the operation command type, and determine an address of an operated page and a starting position of addressing the page.

Optionally, the operating the command function further includes: a cache area of interactive operation data, a mark of physical page area operation and the like. The embodiment of the present invention is described only by taking an example that the operation command function includes an operation command type, a logical page address, and an offset in a page, and the present invention does not limit the specific composition of the operation command function.

Correspondingly, if the type of the operation command is a write operation command, reading the data to be written from the data cache region.

Specifically, when the operation command type specified by the upper layer application is a write operation command, the data cache area is used as a data interaction area between the upper layer application and the Nand Flash, and data to be written in is stored in the data interaction area, so that when the write operation command is executed, the data to be written is firstly read from the data cache area, then the data to be written is encoded according to a specified verification algorithm, and the encoded write data obtained after encoding is sequentially written into main areas of at least two adjacent pages of the Nand Flash.

It should be noted that, when writing to the oob area of the page, since the oob area is used as a spare part of the main area in Nand Flash, during the operation, it is not necessary to start the check function, and in the operation of merging at least two adjacent pages into a write operation page, it is only necessary to select the oob area in the first logical page to meet the requirements of the upper layer application. Therefore, unlike the operation of writing the main area, when the oob area is written, only a write command needs to be issued once, whereas when the Nand Flash controller is operated, only the in-page offset needs to be set to the size of the main area in the page, and the size of the write data is the space size of the oob area.

FIG. 6 is a flowchart illustrating a fourth embodiment of a Nand Flash control method provided by the present invention. The fourth embodiment of the invention is a further description of the Nand Flash control method on the basis of the above embodiments. As shown in fig. 6, the Nand Flash control method provided in the embodiment of the present invention further includes:

step 601: if the type of the operation command is a read operation command, determining the read operation page addresses corresponding to the at least two groups of read coded data according to the logical page address corresponding to the data to be read and the Nand Flash page number occupied by the at least two groups of read coded data corresponding to the data to be read;

specifically, similar to the write operation in the foregoing embodiment, if the operation command type is a read operation command, the read operation page address corresponding to the at least two sets of write encoded data needs to be determined according to the logical page address corresponding to the data to be read and the Nand Flash page number occupied by the at least two sets of read encoded data corresponding to the data to be read.

Step 602: determining the reading initial positions of at least two groups of reading coded data in the page corresponding to the reading operation page address according to the page offset corresponding to the data to be read and the reading operation page address;

similarly, according to the offset in the page and the logical read address of the data to be read in the operation command function, the read start position of at least two sets of read encoded data in the page corresponding to the read operation page can be determined, and then the data is read from the read start position.

Step 603: reading the at least two groups of read coded data from the main area of the page corresponding to the read operation page address and the adjacent page in sequence from the read starting position;

specifically, when the Nand Flash page number and the read starting position occupied by at least two sets of read coding data corresponding to the data to be read are determined, the at least two sets of read coding data can be read from the main area of the page corresponding to the read operation page address and the adjacent page in sequence from the read starting position, and then stored in a cache area where the upper layer application interacts with the Nand Flash data.

Step 604: and decoding the at least two groups of read coding data according to a check algorithm with the error correction digit larger than the preset error correction digit to obtain the data to be read.

Specifically, since the data to be written is encoded by using the check algorithm with the error correction bits larger than the preset error correction bits, the at least two sets of read encoded data are decoded by using the check algorithm with the error correction bits larger than the preset error correction bits, so that the read check data and the corresponding read check code in the read encoded data can be obtained, and the data to be read corresponding to the read check data can be obtained.

It should be noted that, when the oob area of the page is read, since the oob area is used as a spare part of the main area in the Nand Flash, it is not necessary to start the check function, and in the operation of merging at least two adjacent pages into one read operation page, it is also necessary to select the oob area in the first logical page to meet the requirements of the upper layer application. Therefore, unlike the operation of reading the main area, when reading the oob area, it is only necessary to initiate a read command once, and when operating the Nand Flash controller, it is only necessary to set the offset amount in the page to the size of the main area in the page, and the size of the read data is the space size of oob area.

According to the Nand Flash control method provided by the embodiment of the invention, the read operation page address corresponding to the read encoding data can be determined according to the logic page address corresponding to the data to be read and the Nand Flash page number occupied by at least two groups of read encoding data corresponding to the data to be read, then the read starting position of at least two groups of read encoding data in the page corresponding to the read operation page address can be determined according to the offset in the page corresponding to the data to be read, so that the corresponding at least two groups of read encoding data can be sequentially read from the main area of the page corresponding to the read operation page address and the adjacent page from the read starting position, and finally the at least two groups of read encoding data are decoded according to the check algorithm that the error correction digit is greater than the preset error correction digit to obtain the data to be read. According to the technical scheme, when the read check data is read, the read check codes are read out from the main area of the page together, the limitation of the number of bytes of the original ECC check code and the limited storage space of the oob area on the Nand Flash is broken, the ECC algorithm capability is improved, and the reliability of the operation data is enhanced.

It should be noted that the write operation for Nand Flash must be performed in a blank area, and if the designated operation area of Nand Flash already has data, the data must be written after being erased, so the erase operation is the basic operation of Nand Flash, and Nand Flash performs the erase operation in units of blocks. The Nand Flash mainly depends on a Nand controller, the main information required by the Nand controller is a block address, and operation data does not need to be checked when the Nand Flash performs the erasing operation.

FIG. 7 is a schematic flow chart of a fifth embodiment of a Nand Flash control method provided by the present invention. The fifth embodiment of the present invention is a further description of the Nand Flash control method based on the above embodiments. The embodiment of the invention mainly aims at managing the bad blocks in the Nand Flash. Specifically, as shown in fig. 7, the Nand Flash control method provided in the embodiment of the present invention further includes:

step 701: acquiring basic information of Nand Flash;

wherein, the basic information comprises: device ID, page size, block size, and total device size.

For the device information of Nand Flash, the device information is directly specified by a program in a Flash information acquisition module, is the inherent characteristic of device hardware, does not need additional operation, and mainly comprises the following information: device ID, page size, oob area size, block size, and in-device size. Based on the above scheme of merging at least two adjacent pages into an operation page, the result is that the operable pages contained in each block are correspondingly reduced by at least two times, so that the block size of each block is correspondingly reduced by at least two times, the total size of the device is reduced by at least two times, but the number of blocks appears unchanged.

Step 702: determining the total page number of the Nand Flash according to the total size of the equipment and the page size;

when the data to be operated is coded by adopting a check algorithm with the error correction digit larger than the preset error correction digit, and the corresponding page of the Nand Flash is read and written, the total size of the equipment is the total size after operation, the page size is the operable size of each page, and the total size of the equipment is divided by the page size according to the obtained total size of the equipment and the page size, so that the total page number of the Nand Flash can be obtained.

Step 703: determining the total block number of Nand Flash according to the total size of the equipment and the block size;

correspondingly, the total size of the equipment is divided by the block size according to the total size and the block size of the equipment acquired by the Flash information acquisition module, so that the total block number of the Nand Flash can be calculated.

Step 704: determining the number of pages contained in each block in the Nand Flash according to the block size and the page size;

step 705: establishing an array block table containing the corresponding relation between the blocks and the pages according to the total page number, the total block number and the page number contained in each block;

specifically, the array block table is an array, and is an array which is constructed by calculating the total number of pages and the total number of blocks contained in the Flash device based on Nand Flash device parameters specified by the Flash information acquisition module, wherein each array member represents the state of a corresponding block.

Step 706: reading data of each page oob area contained in each block in the array block table;

the program corresponding to the upper layer application can read oob area data of each page by traversing all pages contained in each block in the array block table, and determines whether the block is a bad block according to the positive and wrong conditions of oob area data of each page. Specifically, the determination can be made based on the second byte of the 0 th page oob area of each block.

Step 707: if the data of all the pages oob contained in each block has errors, the block is marked as a bad block, and a bad block table is formed.

If the data of all the page oob areas contained in each block is wrong, which indicates that errors occur during the read-write operation of the block, the blocks are marked as bad blocks, and the combination of all the bad blocks forms a bad block table, so that the bad blocks are skipped when the Nand Flash is operated, and the reliability of the data is ensured.

The Nand Flash control method provided by the embodiment of the invention determines the total number of pages and the total number of blocks contained in the Flash device by using the total size, the page size and the block size of the Nand Flash device, further establishes an array block table containing a plurality of members of the total block, screens out bad blocks according to data in each page oob area contained in each block in the array block table to form a bad block table, and further skips over the bad blocks when the Nand Flash is subsequently operated, thereby ensuring the reliability of the data.

FIG. 8 is a schematic structural diagram of a Nand Flash control device according to an embodiment of the present invention. As shown in fig. 8, the Nand Flash control device provided in the embodiment of the present invention includes:

the encoding module 801 is configured to encode data to be written by using a check algorithm with an error correction bit number greater than a preset error correction bit number to obtain at least two groups of write encoded data;

wherein each set of write coded data includes: and the write check data and the write check code corresponding to the write check data.

The write operation module 802 is configured to sequentially write the write check data included in each of the at least two groups of write-coded data obtained by the encoding module 801 and the write check code corresponding to the write check data into the main areas of the at least two adjacent pages of the Nand Flash.

The Nand Flash control device provided by the embodiment of the invention can be used for executing the technical scheme of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, and are not described herein again.

FIG. 9 is a schematic structural diagram of a Nand Flash control device according to a second embodiment of the present invention. The embodiment of the invention is further explained for the Nand Flash control device on the basis of the embodiment. As shown in fig. 9, the Nand Flash control device provided in the embodiment of the present invention further includes: an operating page number determination module 901, a physical page address acquisition module 902, and a write address determination module 903.

The operating page number determining module 901 is configured to determine, before the write operating module 802, a Nand Flash page number occupied by at least two groups of write coded data according to the number of groups of write coded data and the size of each group of write coded data;

the physical page address obtaining module 902 is configured to obtain a physical page address corresponding to data to be written according to the obtained operation command function;

the write address determining module 903 is configured to determine write operation page addresses corresponding to at least two groups of write coding data according to the Nand Flash page number occupied by the at least two groups of write coding data determined by the operation page number determining module 901 and the physical page address corresponding to the data to be written acquired by the physical page address acquiring module 902.

The Nand Flash control device provided by the embodiment of the invention can be used for executing the technical scheme of the method embodiment shown in fig. 3, and the implementation principle and the technical effect are similar, and are not described herein again.

FIG. 10 is a schematic structural diagram of a Nand Flash control device according to a third embodiment of the present invention. The embodiment of the invention is further explained for the Nand Flash control device on the basis of the embodiment. As shown in fig. 10, in the Nand Flash control device according to the embodiment of the present invention, the write operation module 802 includes:

an offset determining unit 1001, configured to determine, according to the obtained operation command function, an intra-page offset corresponding to the data to be written;

a write start position determining unit 1002, configured to determine, according to the write operation page address and the intra-page offset, a write start position of at least two sets of write encoded data in a page corresponding to the write operation page address;

the write operation unit 1003 is configured to sequentially write, from a write start position, write verification data included in each set of write-coded data of the at least two sets of write-coded data and a write verification code corresponding to the write verification data into a page corresponding to the write operation page address and a main area of an adjacent page.

The Nand Flash control device provided by the embodiment of the invention can be used for executing the technical scheme of the method embodiment shown in fig. 4, and the implementation principle and the technical effect are similar, and are not described herein again.

Further, in the Nand Flash control device provided in the above embodiment, if the preset number of error correction bits is 1 byte, the check algorithm that the number of error correction bits is greater than the preset number of error correction bits includes: Reed-Solomon (RS) (204, 188) encoding algorithm for Error Checking and Correction (ECC); the number of error correction bits of the RS (204, 188) encoding algorithm of the ECC is less than or equal to 8 bytes;

the encoding module 801 is specifically configured to encode the data to be written by using an RS (204, 188) encoding algorithm of an ECC to obtain 11 groups of write-encoded data, where the first 188 bytes of each group of write-encoded data are write check data, and the last 16 bytes of each group of write-encoded data are write check codes.

Further, the Nand Flash control device provided in the above embodiment further includes: the device comprises an operation command acquisition module and a write data acquisition module.

The operation command acquiring module is configured to acquire an operation command function for Nand Flash before the encoding module 801, where the operation command function includes: operation command type, logical page address, offset within page;

the write data acquisition module is used for reading data to be written from the data cache region when the operation command type is a write operation command.

FIG. 11 is a schematic structural diagram of a fourth embodiment of a Nand Flash control device provided by the present invention. The embodiment of the invention is further explained for the Nand Flash control device on the basis of the embodiment. As shown in fig. 11, the Nand Flash control device provided in the embodiment of the present invention further includes:

the read address determining module 1101 is configured to determine, when the operation command type is a read operation command, read operation page addresses corresponding to at least two sets of read encoding data according to a logical page address corresponding to the data to be read and a Nand Flash page number occupied by the at least two sets of read encoding data corresponding to the data to be read;

a read start position determining unit 1102, configured to determine, according to the in-page offset and the read operation page address corresponding to the data to be read, a read start position of at least two sets of read encoding data in a page corresponding to the read operation page address;

a read operation module 1103, configured to read at least two sets of read encoded data from the main area of the page corresponding to the read operation page address and the adjacent page in sequence from the read start position;

and the decoding module 1104 is configured to decode the at least two sets of read coding data according to a check algorithm that the error correction bits are greater than the preset error correction bits, so as to obtain data to be read.

The Nand Flash control device provided by the embodiment of the invention can be used for executing the technical scheme of the method embodiment shown in fig. 6, and the implementation principle and the technical effect are similar, and are not described herein again.

FIG. 12 is a schematic flow chart of a fifth embodiment of the Nand Flash control device provided by the present invention. The fifth embodiment of the present invention is a further description of the Nand Flash control device based on the above embodiments. The embodiment of the invention mainly aims at managing the bad blocks in the Nand Flash. Specifically, as shown in fig. 12, the Nand Flash control device provided in the embodiment of the present invention further includes:

a basic information obtaining module 1201, configured to obtain basic information of Nand Flash;

a total page number determining module 1202, configured to determine the total page number of the Nand Flash according to the total size of the device and the page size obtained by the basic information obtaining module 1201;

a total block number determining module 1203, configured to determine a total block number of the Nand Flash according to the total size and the block size of the device obtained by the basic information obtaining module 1201;

a block in page number determining module 1204, configured to determine, according to the block size and the page size obtained by the basic information obtaining module 1201, a number of pages included in each block in the Nand Flash;

an array block table establishing module 1205, configured to establish an array block table including a corresponding relationship between blocks and pages according to the total page number determined by the total page number determining module 1202, the total block number determined by the total block number determining module 1203, and the page number included in each block determined by the page number in block determining module 1204;

an oob area data obtaining module 1206, configured to read data of each page oob area included in each block in the array block table established by the array block table establishing module 1205;

a bad block table marking module 1207, configured to mark each block as a bad block when the data in all the pages oob included in the block has an error, so as to form a bad block table.

The Nand Flash control device provided by the embodiment of the invention can be used for executing the technical scheme of the method embodiment shown in fig. 7, and the implementation principle and the technical effect are similar, and are not described herein again.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Nand Flash control method is characterized by comprising the following steps:

encoding data to be written by adopting a check algorithm with the error correction digit larger than the preset error correction digit to obtain at least two groups of write encoded data, wherein each group of write encoded data comprises: the write check data and a write check code corresponding to the write check data; the preset error correction bit number is the bit number of errors which can be corrected by the verification algorithm and is used for representing the error correction and detection capability of the verification algorithm;

writing the write check data included in each group of write-coded data in the at least two groups of write-coded data and the write check code corresponding to the write check data into main areas of at least two adjacent pages of the Nand Flash in sequence;

and the at least two adjacent pages are combined into one write operation page, and the at least two groups of write coded data are stored in the combined write operation page.

2. The method according to claim 1, before the writing check data included in each of the at least two sets of write-coded data and the write check code corresponding to the write check data are sequentially written into the main areas of at least two adjacent pages of Nand Flash, the method further comprises:

determining the Nand Flash page number occupied by the at least two groups of write-coded data according to the group number of the write-coded data and the size of each group of the write-coded data;

acquiring a physical page address corresponding to the data to be written according to the acquired operation command function;

and determining the write operation page addresses corresponding to the at least two groups of write coded data according to the Nand Flash page number occupied by the at least two groups of write coded data and the physical page address corresponding to the data to be written.

3. The method according to claim 2, wherein the writing check data included in each of the at least two sets of write-coded data and the write check code corresponding to the write check data are sequentially written into main areas of at least two adjacent pages of Nand Flash, specifically comprising:

determining the in-page offset corresponding to the data to be written according to the acquired operation command function;

determining the writing initial positions of the at least two groups of writing coded data in the page corresponding to the writing operation page address according to the writing operation page address and the in-page offset;

and writing the write check data included in each group of write-coded data in the at least two groups of write-coded data and the write check code corresponding to the write check data into the main areas of the page corresponding to the write operation page address and the adjacent page from the write starting position in sequence.

4. The method of claim 1, wherein if the predetermined number of error correction bits is 1 byte, the checking algorithm that the number of error correction bits is greater than the predetermined number of error correction bits comprises: a Reed-Solomon RS (204, 188) encoding algorithm for error checking ECC; the number of error correction bits of the RS (204, 188) encoding algorithm of the ECC is less than or equal to 8 bytes;

the encoding of the data to be written by using the check algorithm with the error correction bits larger than the preset error correction bits to obtain at least two groups of write-encoded data specifically includes:

and encoding the data to be written by adopting the RS (204, 188) encoding algorithm of the ECC to obtain 11 groups of write encoding data, wherein the first 188 bytes of each group of write encoding data are write check data, and the last 16 bytes of each group of write encoding data are write check codes.

5. The method according to any one of claims 1 to 4, wherein before the encoding the data to be written by using the check algorithm with the error correction bits larger than the preset error correction bits to obtain at least two sets of write-encoded data, the method further comprises:

obtaining an operation command function aiming at the Nand Flash, wherein the operation command function comprises the following steps: operation command type, logical page address, offset within page;

and if the operation command type is a write operation command, reading the data to be written from the data cache region.

6. The method of claim 5, further comprising:

if the operation command type is a read operation command, determining read operation page addresses corresponding to at least two groups of read encoding data according to a logical page address corresponding to the data to be read and a Nand Flash page number occupied by at least two groups of read encoding data corresponding to the data to be read;

determining the reading initial positions of the at least two groups of reading coded data in the page corresponding to the reading operation page address according to the page offset corresponding to the data to be read and the reading operation page address;

reading the at least two groups of read coded data from the main areas of the page corresponding to the read operation page address and the adjacent page in sequence from the read starting position;

and decoding the at least two groups of read coding data according to a check algorithm that the error correction digit is greater than the preset error correction digit to obtain the data to be read.

7. A Nand Flash control device is characterized by comprising:

the encoding module is used for encoding data to be written by adopting a check algorithm with the error correction digit being greater than the preset error correction digit to obtain at least two groups of write-encoded data, wherein each group of write-encoded data comprises: the write check data and a write check code corresponding to the write check data; the preset error correction bit number is the bit number of errors which can be corrected by the verification algorithm and is used for representing the error correction and detection capability of the verification algorithm;

and the write operation module is used for sequentially writing write check data included in each group of the at least two groups of write-coded data obtained by the coding module and write check codes corresponding to the write check data into main areas of at least two adjacent pages of Nand Flash, the at least two adjacent pages are combined into one write operation page, and the at least two groups of write-coded data are stored in the write operation page obtained after combination.

8. The apparatus of claim 7, further comprising: the device comprises an operation page number determining module, a physical page address acquiring module and a writing address determining module;

the operating page number determining module is used for determining the Nand Flash page number occupied by the at least two groups of write-coded data according to the group number of the write-coded data and the size of each group of write-coded data before the write operating module;

the physical page address acquisition module is used for acquiring a physical page address corresponding to the data to be written according to the acquired operation command function;

and the write address determining module is used for determining the write operation page addresses corresponding to the at least two groups of write coded data according to the Nand Flash page number occupied by the at least two groups of write coded data and the physical page address corresponding to the data to be written.

9. The apparatus of claim 8, wherein the write module comprises:

the offset determining unit is used for determining the in-page offset corresponding to the data to be written according to the acquired operation command function;

a write start position determining unit, configured to determine, according to the write operation page address and the intra-page offset, a write start position of the at least two sets of write encoded data in a page corresponding to the write operation page address;

and the write operation unit is used for sequentially writing the write verification data included in each group of write-coded data in the at least two groups of write-coded data and the write verification code corresponding to the write verification data into the main areas of the page corresponding to the write operation page address and the adjacent page from the write starting position.

10. The apparatus of claim 7, wherein if the predetermined number of error correction bits is 1 byte, the checking algorithm that the number of error correction bits is greater than the predetermined number of error correction bits comprises: a Reed-Solomon RS (204, 188) encoding algorithm for error checking ECC; the number of error correction bits of the RS (204, 188) encoding algorithm of the ECC is less than or equal to 8 bytes;

the encoding module is specifically configured to encode the data to be written by using an RS (204, 188) encoding algorithm of the ECC to obtain 11 groups of write-encoded data, where the first 188 bytes of each group of write-encoded data are write check data, and the last 16 bytes of each group of write-encoded data are write check codes.

11. The apparatus of any one of claims 7 to 10, further comprising: the device comprises an operation command acquisition module and a write data acquisition module;

the operation command obtaining module is configured to obtain an operation command function for the Nand Flash before the encoding module, where the operation command function includes: operation command type, logical page address, offset within page;

and the write data acquisition module is used for reading the data to be written from the data cache region when the operation command type is a write operation command.

12. The apparatus of claim 11, further comprising:

the read address determining module is used for determining the read operation page addresses corresponding to the at least two groups of read coding data according to the logical page address corresponding to the data to be read and the Nand Flash page number occupied by the at least two groups of read coding data corresponding to the data to be read when the operation command type is a read operation command;

a reading start position determining unit, configured to determine, according to the in-page offset corresponding to the data to be read and the read operation page address, a reading start position of the at least two sets of read encoding data in a page corresponding to the read operation page address;

the reading operation module is used for reading the at least two groups of reading coded data from the reading initial position from the main area of the page corresponding to the reading operation page address and the adjacent page in sequence;

and the decoding module is used for decoding the at least two groups of read coding data according to a check algorithm that the error correction digit is greater than the preset error correction digit to obtain the data to be read.