KR101308616B1 - Non-volatile memory system - Google Patents

Abstract

The nonvolatile memory system includes at least one NAND flash memory device, a nonvolatile memory device storing previous correction bit information for each of page data stored in the NAND flash memory device, and a page from the NAND flash memory device in response to a read command signal. Reads the data, corrects the bits of the page data read based on the previous correction bit information to generate bit corrected page data, and performs BC correction on the bit corrected page data to generate error corrected page data And a controller for outputting error corrected page data as read data to the host, and storing new correction bit information in a nonvolatile memory device to update previous correction bit information. Thus, the nonvolatile memory system can improve the error checking and correction function without improving the correction capability of the IC.

Description

Nonvolatile Memory System {NON-VOLATILE MEMORY SYSTEM}

TECHNICAL FIELD The present invention relates to a semiconductor memory system, and more particularly, to a nonvolatile memory system that provides an error check and correction function.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device according to whether data can be stored in a state where power is not supplied. Recently, a NAND flash memory device having Multi Level Cells (MLCs) among nonvolatile memory devices has been widely used for miniaturization and large capacity. In general, a NAND flash memory device performs a write operation and a read operation on data (hereinafter, page data) in units of pages, and includes multi level cells (MLCs). As NAND flash memory devices are miniaturized and large in capacity, sufficient margins may not be secured in the threshold voltage distribution during a read operation on page data, and thus an error may occur.

Accordingly, a nonvolatile memory system including a NAND flash memory device may provide an error check and correction function by including an Error Correction Code (ECC) unit (that is, an ECC engine) in a controller. However, since Mr. Lee's correction capability is limited, when error checking and correction is performed on one page data, if the error for the page data increases, the correction capability of Mr. Lee exceeds, The NAND flash memory device should perform an erase refresh operation for writing the page data to another block and erasing the block in which the page data is written. As a result, the erase refresh operation is frequently performed, and thus, the overall performance and lifespan of the nonvolatile memory system are greatly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error check and correction function for at least one NAND flash memory device, thereby improving error checking and correction without improving the error correction capability of an ECC. To provide a nonvolatile memory system that can be. It should be understood, however, that the present invention is not limited to the above-described embodiments, but may be variously modified without departing from the spirit and scope of the invention.

In order to achieve the object of the present invention, the nonvolatile memory system according to the embodiments of the present invention is at least one NAND flash memory device, prior correction bit for each of the page data stored in the NAND flash memory device A non-volatile memory device storing information, and reading page data from the NAND flash memory device in response to a read command signal, and correcting bits of the read page data based on the previous correction bit information. Generates corrected page data, generates error corrected page data by performing Error Correction Code (ECC) decoding on the bit corrected page data, and hosts the error corrected page data. output as read data to the host), and the new correction bit information is Was stored in a speech memory device may include a controller that updates the previous correction bit information.

According to an embodiment, the previous correction bit information may include information about a location where an error occurs and information about a bit value at the location where the error occurs.

According to an embodiment, the controller may correct the bits of the read page data based on the information on the location of the error and the information on the bit value at the location of the error.

In example embodiments, the controller may cause the NAND flash memory device to perform an erasure refresh operation when the number of locations where the error occurs is equal to or greater than a preset value.

According to an embodiment, when the previous correction bit information for the read page data is not stored in the nonvolatile memory device, the controller performs the BC decoding on the read page data to correct the error. Generated page data.

According to an embodiment, the controller receives write data from the host in response to a write command signal, generates the page data by performing BC encoding on the write data in units of pages, and generates the page data. Data may be stored in the NAND flash memory device.

In example embodiments, the controller may store flag cell information regarding the page data in the nonvolatile memory device in response to the write command signal.

In example embodiments, the controller may read the page data from the NAND flash memory device based on the flag cell information stored in the nonvolatile memory device in response to the read command signal.

In example embodiments, the nonvolatile memory device may be a phase-change random access memory (PRAM) device capable of performing an overwrite operation.

According to an embodiment, the nonvolatile memory system may be manufactured as an embedded multimedia card (EMMC).

A nonvolatile memory system according to embodiments of the present invention includes at least one NAND flash memory device, and in providing an error check and correction function for the NAND flash memory device, the page data stored in the NAND flash memory device. Storing previous correction bit information for each of them in a nonvolatile memory device, and when reading page data from the NAND flash memory device, correcting the bits of the page data using the previous correction bit information for the page data. It is possible to improve the error checking and correction function without improving the error correction capability of ECC. As a result, deterioration of the overall performance and lifespan of the nonvolatile memory system can be prevented. However, the effects of the present invention are not limited thereto, and various modifications may be made without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a nonvolatile memory system according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating an example in which page data is written to a NAND flash memory device in the nonvolatile memory system of FIG. 1.
3 is a diagram illustrating an example in which page data is written to a NAND flash memory device in the nonvolatile memory system of FIG. 1.
4A through 4C are flowcharts illustrating an example in which page data is read from a NAND flash memory device in the nonvolatile memory system of FIG. 1.
FIG. 5 is a diagram illustrating an example in which page data is read from a NAND flash memory device in the nonvolatile memory system of FIG. 1.
6 is a block diagram illustrating a nonvolatile memory system according to another exemplary embodiment of the present invention.
FIG. 7 is a flowchart illustrating an example in which page data is written to a NAND flash memory device in the nonvolatile memory system of FIG. 6.
FIG. 8 is a flowchart illustrating an example in which page data is read from a NAND flash memory device in the nonvolatile memory system of FIG. 6.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a nonvolatile memory system according to an embodiment of the present invention.

Referring to FIG. 1, the nonvolatile memory system 100 may include a NAND flash memory device 120, a nonvolatile memory device 140, and a controller 160. Although one NAND flash memory device 120 and one nonvolatile memory device 140 are illustrated in FIG. 1, this is for convenience of description, and the nonvolatile memory system 100 may include at least one NAND flash memory device ( 120 and at least one nonvolatile memory device 140.

The NAND flash memory device 120 may perform write and read operations on data (hereinafter, page data PDAT) in units of pages, and perform erasure operations in units of blocks. . Although not shown in FIG. 1, the NAND flash memory device 120 may include a memory cell array composed of single level cells (SLCs) or multi level cells (MLCs); A page buffer may be included, and the controller 160 may interact with the controller 160 based on a NAND interface protocol. The nonvolatile memory device 140 may provide the previous correction bit information OCBI to the controller 160 and receive the new correction bit information NCBI from the controller 160 to update the previous correction bit information OCBI. (update) In detail, the non-volatile memory device 140 stores previous correction bit information OCBI for each of the page data PDAT stored in the NAND flash memory device 120. In this case, when the page data PDAT stored in the NAND flash memory device 120 is read, the non-volatile memory device 140 may output the previous correction bit information OCBI for the read page data PDAT. ) Can be provided. As a result, the controller 160 may correct the bits of the read page data PDAT based on previous correction bit information OCBI. On the other hand, when the controller 160 generates error corrected page data by performing Error Correction Code decoding on the read page data PDAT, a new correction on the read page data PDAT. Bit information NCBI can be obtained. Therefore, the controller 160 may update the previous correction bit information OCBI with respect to the read page data PDAT by storing the new correction bit information NCBI in the nonvolatile memory device 140. In one embodiment, since the nonvolatile memory device 140 needs to operate at a higher speed than the NAND flash memory device 120, a phase-change random access memory capable of performing an overwrite operation may be used. PRAM) device. However, this is only one example, and the type of the nonvolatile memory device 140 is not limited to only a PRAM device.

The controller 160 may receive the write data WDAT from a host (not shown) based on the write command signal WCMD, and based on the read command signal RCMD. Read data RDAT can be output to the host. Although not shown in FIG. 1, the controller 160 includes a host, a universal serial bus (USB), a multimedia card (MMC), a PCI (PCI), a PC-Express (PCI-Express), an ATA, and a serial device. Interact with the host based on standard protocols such as S-ATA, Parallel-A-P, SCSI, SCSI, ESDI, SAS and IDE can do. Specifically, the controller 160 receives the write data WDAT from the host in response to the write command signal WCMD when writing the page data PDAT to the NAND flash memory device 120. The page data PDAT may be generated by performing the IC encoding on a page basis for the WDAT, and the page data PDAT may be stored in the NAND flash memory device 120. That is, the write operation of the nonvolatile memory system 100 may be substantially the same as the write operation of the conventional nonvolatile memory system. On the other hand, in outputting the read data RDT to the host, the controller 160 reads the page data PDAT from the NAND flash memory device 120 in response to the read command signal RCMD, and generates a nonvolatile memory device. Bit-corrected page data may be generated by correcting bits of the read page data PDAT based on previous correction bit information OCBI provided from 140. Thereafter, the controller 160 may perform error correction on the bit corrected page data to generate error corrected page data, and output the error corrected page data as read data (RDAT) to a host. At this time, when the error corrected page data is generated, the controller 160 obtains the new correction bit information NCBI for the read page data PDAT. By storing in the nonvolatile memory device 140, the previous correction bit information OCBI with respect to the read page data PDAT may be updated.

In one embodiment, the controller 160 generates the bit-corrected page data by correcting the bits of the page data PDAT read from the NAND flash memory device 120 during a read operation of the nonvolatile memory system 100. The page unit PDAT is generated by performing BC encoding on a page basis for the correction unit and the write data WDAT input from the host during a write operation of the nonvolatile memory system 100, and generates the nonvolatile memory system 100. ) May include an IC unit (ie, an IC engine) that generates error-corrected page data by performing IC decoding on the bit-corrected page data during a read operation. At this time, the bit correction unit and the BC unit may be implemented in hardware, or may be implemented in software, it is preferable that the non-volatile memory system 100 is implemented in hardware to operate at high speed. Do. Furthermore, as the ECC provided by the CC unit, a Low Density Parity Check (LDPC) code, a Bose Chaudhuri Hocquenghem (BCH) code, a hamming code, or the like may be used, but is not limited thereto. Meanwhile, the previous correction bit information OCBI may include information about a location where an error occurs and information about a bit value at a location where an error occurs, and the controller 160 reads an operation of the nonvolatile memory system 100. The time bit correction unit may cause the bits of the read page data PDAT to be corrected based on information on a location where an error occurs and information on a bit value at a location where an error occurs. As a result, since the IC unit provided in the controller 160 only needs to perform error check and correction on the bit corrected page data, more errors are compared with the ECC's correction capability provided by the IC unit. Correction is possible. For example, in the case where the BC unit provides the correction capability of the IC which can correct 40 bits, even if the page data PDAT read from the NAND flash memory device 120 has errors of 45 bits, The errors in the read page data PDAT are corrected based on previous bit correction information (eg, information about 35 bits of error), so the BCC unit has only 10 bits of error correction. Error check and correction may be performed on the page data. Accordingly, the nonvolatile memory system 100 is capable of error checking and correcting page data PDAT having 45 bits of errors with a BC unit providing a correcting capability of 40 bits that can correct 40 bits. Can be.

Meanwhile, in the read operation of the nonvolatile memory system 100, the controller 160 displays the previous correction bit information OCBI with respect to the page data PDAT read from the NAND flash memory device 120. If not stored in the CDMA, the error-corrected page data can be directly generated by performing the decoding of the BC data on the read page data PDAT. That is, the previous correction bit information OCBI for the page data PDAT read from the NAND flash memory device 120 is lost (or deleted) for various reasons, or written to the NAND flash memory device 120. If the previous correction bit information (OCBI) does not exist since it has not been read since, the controller 160 directly generates error-corrected page data by performing BC-C decoding on the read page data PDAT. The error corrected page data is output to the host. Even in this case, since the new correction bit information NCBI for the read page data PDAT is obtained when the error corrected page data is generated, the read page data is read in the new correction bit information NCBI. It may be stored in the nonvolatile memory device 140 as previous correction bit information (OCBI) for the PDAT. Further, according to an embodiment, the controller 160 checks the new correction bit information NCBI obtained as the error corrected page data is generated or the previous correction bit information OCBI stored in the nonvolatile memory device 140. Specifically, the NAND flash memory device 120 causes the NAND flash memory device 120 to determine if the number of locations in which the error occurs in the page data PDAT is greater than or equal to a preset value. It is possible to artificially perform an erase refresh operation. That is, since an error occurring in one page data PDAT tends to increase continuously due to disturbance or retention, a high operating stability can be achieved by artificially performing an erase refresh operation under a specific condition. To secure. As described above, the nonvolatile memory system 100 aims to improve overall performance and lifespan by minimizing an erase refresh operation. However, when the number of locations where an error occurs in the page data PDAT is larger than a preset value. The NAND flash memory device 120 may be caused to artificially perform an erase refresh operation.

As described above, the conventional non-volatile memory system, for example, when the ECC engine provides the correction ability of the CCC that can correct 40 bits, the page data (stored in the NAND flash memory device 120 ( When 38 bits of errors occur in the PDAT, since 40 or more errors may occur within a short time, the NAND flash memory device 120 writes the page data PDAT into another block, and the page data. The erase refresh operation which erases the block in which (PDAT) has been written must be performed. However, since the NAND flash memory device 120 needs to perform an erase operation in units of blocks and writes the page data PDAT to another block, a merge operation may be performed. The ease refresh operation may significantly degrade the overall performance of the nonvolatile memory system 100. In addition, since the lifespan of the cells included in the NAND flash memory device 120 decreases as the write and erase operations are repeated, the erase refresh operation greatly reduces the overall lifetime of the nonvolatile memory system 100. You can. Accordingly, in the nonvolatile memory system 100 providing an error check and correction function for the NAND flash memory device 120, a previous correction bit for each of the page data PDATs stored in the NAND flash memory device 120 is provided. When the information NCBI is stored in the nonvolatile memory device 140 and the page data PDAT is read from the NAND flash memory device 120, the previous correction bit information NCBI for the page data PDAT is read. By using this to correct the bits of the page data PDAT, the error checking and correction function can be improved without improving the correction capability of the CC. As a result, the degradation of the overall performance and lifespan of the nonvolatile memory system 100 can be prevented, as well as including a CCC unit that provides a relatively low ICC correction capability compared to a conventional nonvolatile memory system. It can be produced at low cost and miniaturization. Thus, the nonvolatile memory system 100 may be manufactured in various forms, for example, an embedded multi-media card (EMMC), a secure digital card, a compact flash card (CF card). , A memory stick, an XD picture card, or the like.

2 is a flowchart illustrating an example in which page data is written to a NAND flash memory device in the nonvolatile memory system of FIG. 1, and FIG. 3 is an example of writing page data in a NAND flash memory device in the nonvolatile memory system of FIG. 1. It is a figure which shows an example.

2 and 3, when the nonvolatile memory system 100 of FIG. 1 receives the write command signal WCMD from a host (not shown) (Step S120), the nonvolatile memory system 100 receives the write data WDAT from the host ( After step S140, page data PDAT may be generated by performing ECC encoding on a page basis with respect to the write data WDAT. Thereafter, the nonvolatile memory system 100 of FIG. 1 may store the page data PDAT in the NAND flash memory device 120 (Step S180). That is, when looking at the side of the controller 160 in the nonvolatile memory system 100, the controller 160 may include an ICC unit 164 and a bit correction unit 162, which is illustrated in FIG. 1. The write operation of 100 may be substantially the same as the write operation of the conventional nonvolatile memory system. That is, the BC unit 164 generates page data PDAT by performing BC encoding on a page basis with respect to the write data WDAT input from the host during the write operation of the nonvolatile memory system 100 of FIG. 1. The bit correction unit 162 does not perform a specific operation during the write operation of the nonvolatile memory system 100 of FIG. 1. As described above, a low density parity check (LDPC) code, a Bose Chaudhuri Hocquenghem (BCH) code, a hamming code, and the like may be used as the error correction code of the BC unit 164, but is not limited thereto. Do not. In some embodiments, an interleaving operation may be performed when the page data PDAT is stored in the NAND flash memory device 120 in the nonvolatile memory system 100.

4A through 4C are flowcharts illustrating an example in which page data is read from a NAND flash memory device in the nonvolatile memory system of FIG. 1, and FIG. 5 is a diagram illustrating page data from a NAND flash memory device in the nonvolatile memory system of FIG. 1. It is a figure which shows an example to be read.

4A through 4C and 5, when the nonvolatile memory system 100 of FIG. 1 receives a read command signal RCMD from a host (not shown) (Step S210), the NAND flash memory device 120 may be used. In operation S220, it may be determined whether the previous correction bit information OCBI for the page data PDAT to be read from is stored in the nonvolatile memory device 140. At this time, when the previous correction bit information OCBI for the page data PDAT to be read from the NAND flash memory device 120 is stored in the nonvolatile memory device 140, the NAND flash memory device 120 is stored from the NAND flash memory device 120. The page data PDAT may be read (Step S230), and the previous correction bit information OCBI of the page data PDAT may be read from the nonvolatile memory device 140 (Step S240). Thereafter, the nonvolatile memory system 100 of FIG. 1 generates the bit-corrected page data CDAT by correcting the bits of the page data PDAT based on previous correction bit information OCBI (Step S250). Error corrected page data may be generated by performing ECC decoding on the bit corrected page data CDAT (Step S260). As described above, when BC error decoding is performed on the bit corrected page data CDAT, when the error corrected page data is generated, new correction bit information NCBI for the page data PDAT is obtained. Since the nonvolatile memory system 100 of FIG. 1 may store the new correction bit information NCBI in the nonvolatile memory device 140 (Step S270), the previous correction bit information OCBI may be updated. . The nonvolatile memory system 100 of FIG. 1 may output the error corrected page data to the host as read data RDTAT (Step S280).

On the other hand, in the nonvolatile memory system 100 of FIG. 1, the previous correction bit information OCBI for the page data PDAT to be read from the NAND flash memory device 120 is not stored in the nonvolatile memory device 140. If not, the page data corrected by reading the page data PDAT from the NAND flash memory device 120 (Step S290), and then performing the IC decoding on the page data PDAT (Step S300). Can be generated. As described above, when the error corrected page data is generated by performing the IC decoding on the page data PDAT, new correction bit information NCBI for the page data PDAT can be obtained. The nonvolatile memory system 100 of FIG. 1 may store the new correction bit information NCBI in the nonvolatile memory device 140 as the previous correction bit information OCBI to be used later (Step S310). Meanwhile, the nonvolatile memory system 100 of FIG. 1 may output the error corrected page data to the host as read data RDTAT (Step S320). As described above, the nonvolatile memory system 100 of FIG. 1 corrects bits of the page data PDAT by using the previous correction bit information NCBI for the page data PDAT in a read operation. It is possible to improve the error checking and correction function without improving the capability. Furthermore, since the bit corrected page data CPAT has fewer errors than the page data PDAT, the IC unit 164 can perform error check and correction quickly and accurately. As a result, operation stability and operation reliability of the nonvolatile memory system 100 of FIG. 1 may also be greatly improved.

6 is a block diagram illustrating a nonvolatile memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the nonvolatile memory system 200 may include a NAND flash memory device 220, a nonvolatile memory device 240, and a controller 260. Although one NAND flash memory device 220 and one nonvolatile memory device 240 are illustrated in FIG. 6, this is for convenience of description, and the nonvolatile memory system 200 may include at least one NAND flash memory device ( 220 and at least one non-volatile memory device 240 will be construed as including. In the nonvolatile memory system 200, when the page data PDAT is read from the NAND flash memory device 220, the page data PDAT is read based on the previous correction bit information OCBI stored in the nonvolatile memory device 240. Since the contents of the bits of the page data PDAT have been described with reference to FIG. 1, duplicate description thereof will be omitted. 6, the flag cell information FCI is stored in the nonvolatile memory device 240.

The NAND flash memory device 220 may perform a write operation and a read operation on data (hereinafter, page data PDAT) on a page basis and an erase operation on a block basis. Although not shown in FIG. 6, the NAND flash memory device 220 may include a memory cell array and a page buffer composed of multi level cells (MLCs). In general, since the multi-level cells (MLC) in the NAND flash memory device 220 are programmed by performing a Least Significant Bit (LSB) program and a Most Significant Bit (MSB) program, one word is used. Multi-level cells (MLC) belonging to the line may have one of a plurality of states. For example, when the multi-level cells (MLC) can each store two bits of data, each of the multi-level cells (MLC) belonging to one word line, the first state, the second state, the third state and the fourth Can be programmed to one of the states, respectively, and the first, second, third and fourth states correspond to binary "11", binary "01", binary "10" and binary "00", respectively. can do. In this case, the first to fourth states mean threshold voltage distributions of cells each having a threshold voltage higher than a predetermined verify voltage. In this case, a flag cell may be provided to determine whether there is a multi-level cell (MLC) in which an MSB is programmed in each word line (ie, page). That is, it may be determined whether there is a multi-level cell (MLC) in which the MSB is programmed in each word line based on the bit of the flag cell. For example, if the bit of the flag cell is binary "1", it may be determined that there is no multi-level cell (MLC) in which the MSB is programmed in the word line. If the bit of the flag cell is binary "0", the word It can be determined that there is a multi-level cell (MLC) in which the MSB is programmed in the line.

However, the information on the bits of the flag cell, that is, the flag cell information FCI is referred to only in the NAND flash memory device 220, and the host (not shown) does not need to refer to the flag cell information FCI. Furthermore, since an erroneous read operation is performed when an error occurs in the flag cell and the flag cell information FCI is incorrect, the bit of the flag cell for each word line may be set to two or more bits. As such, the nonvolatile memory system 200 may improve read performance based on the flag cell information FCI. For example, assume that multi-level cells (MLCs) included in the NAND flash memory device 220 can store two bits of data. At this time, if the bit of the flag cell is binary " 1 " A read operation of the NAND flash memory device 220 may be completed based on one verification voltage for distinguishing one state (eg, an erased state) from the remaining second to fourth states. have. On the other hand, if the bit of the flag cell is binary "0", it is determined that there is a multi-level cell (MLC) in which the MSB is programmed in the corresponding word line, and the controller 260 performs a read operation on the corresponding word line. Read to the NAND flash memory device 220 based on three verification voltages for distinguishing the first state from the second state, the second state from the third state, and the third state from the third state. The operation can be completed. However, this may be variously changed depending on the conditions required as an example.

In the nonvolatile memory system 200, the nonvolatile memory device 240 may store flag cell information FCI for page data PDAT written in the NAND flash memory device 220. Thus, the flag cell information FCI for each of the page data PDAT stored in the NAND flash memory device 220 is stored in the nonvolatile memory device 240. In detail, the controller 260 stores the page data PDAT in the NAND flash memory device 220 during a write operation of the nonvolatile memory system 200, while the flag cell information FCI for the page data PDAT is stored. May be stored in the nonvolatile memory device 240. Thereafter, the controller 260 reads the page data PDAT from the NAND flash memory device 220 based on the flag cell information FCI stored in the nonvolatile memory device 240 during a read operation of the nonvolatile memory system 200. ) Can be read. In one embodiment, since the nonvolatile memory device 240 needs to operate at a higher speed than the NAND flash memory device 220, a phase-change random access memory capable of performing an overwrite operation may be used. PRAM) device. However, this is only one example, and the type of the nonvolatile memory device 240 is not limited to a PRAM device. As described above, the nonvolatile memory system 200 performs a read operation on the NAND flash memory device 220 based on the flag cell information FCI stored in the nonvolatile memory device 240. The read performance of the NAND flash memory device may be improved, and even if an error occurs in the flag cell of the NAND flash memory device 220, the read operation may be accurately performed. In addition, although description is omitted in FIG. 6, in the read operation of the NAND flash memory device 220, the page data is based on the previous correction bit information NCBI for the page data PDAT. By correcting the bits of the (PDAT), it is possible to improve the error checking and correction function without improving the corrective ability of Mr. Lee.

FIG. 7 is a flowchart illustrating an example in which page data is written to a NAND flash memory device in the nonvolatile memory system of FIG. 6, and FIG. 8 is an example of reading page data from a NAND flash memory device in the nonvolatile memory system of FIG. 6. It is a flowchart showing an example.

7 and 8, when the nonvolatile memory system 200 of FIG. 6 receives the write command signal WCMD from the host (not shown) (Step S420), the nonvolatile memory system 200 receives the write data WDAT from the host ( After the step S440, the flag cell information FCI for the write data WDD is stored in the nonvolatile memory device 240 (Step S460), and the NAND flash memory is written in units of pages. The write operation may be performed by storing the page data PDAT in the device 220 (Step S480). For convenience of description, in FIG. 7, the non-volatile memory system 200 of FIG. 6 omits the BC encoding of the write data WDD in the page unit during the write operation. In the nonvolatile memory system 200, the BC data encoding is performed on a page basis for the write data WDAT. Subsequently, when the nonvolatile memory system 200 of FIG. 6 receives the read command signal RCMD from the host (Step S520), the flag cell information FCI for the page data PDAT is transmitted from the nonvolatile memory device 240. Read (Step S540), read the page data (PDAT) from the NAND flash memory device 220 based on the flag cell information (FCI) (Step S560), and corresponds to the page data (PDAT) The read operation may be performed by outputting the read data RDAT to the host (Step S580). Similarly, for convenience of description, although the description of performing the IC decoding on the page data PDAT in the read operation of the nonvolatile memory system 200 of FIG. 6 is omitted, the nonvolatile memory of FIG. 6 is omitted. The system 200 performs ICC decoding on the page data PDAT, and corrects the bits of the page data PDAT based on previous correction bit information OCBI before performing the BCC decoding. As mentioned above, although the nonvolatile memory system according to the embodiments of the present invention has been described with reference to the drawings, the above description is illustrative and should be provided to those skilled in the art without departing from the spirit of the present invention. It may be modified and changed by.

The present invention can be applied to a nonvolatile memory system that provides an ECC function. Accordingly, the present invention provides a multimedia card, an embedded multimedia card, a secure digital card, a CF card, a memory stick, a memory stick, an XD picture card. XD picture card).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100: nonvolatile memory system 120: NAND flash memory device
140: nonvolatile memory device 160: controller
162: bit correction unit 164: ECC unit

Claims (10)

At least one NAND flash memory device;
A nonvolatile memory device storing previous correction bit information for each of page data stored in the NAND flash memory device; And
Read page data from the NAND flash memory device in response to a read command signal, generate bits corrected page data by correcting bits of the read page data based on the previous correction bit information, and Error Correction Code (ECC) decoding is performed on the corrected page data to generate error corrected page data, and the error corrected page data is output to the host as read data. And a controller for storing correction bit information in the nonvolatile memory device to update the previous correction bit information. The non-volatile memory system of claim 1, wherein the previous correction bit information includes information about a location where an error occurs and information about a bit value at the location where the error occurs. The nonvolatile memory as claimed in claim 2, wherein the controller corrects the bits of the read page data based on the information on the location of the error and the information on the bit value at the location of the error. system. The nonvolatile memory of claim 3, wherein the controller causes the NAND flash memory device to perform an erase refresh operation when the number of locations where the error occurs is equal to or larger than a preset value. system. The error correction method of claim 1, wherein the controller is further configured to perform the IC decoding on the read page data when the previous correction bit information of the read page data is not stored in the nonvolatile memory device. Nonvolatile memory system, characterized in that it generates generated page data. The apparatus of claim 1, wherein the controller receives write data from the host in response to a write command signal, generates the page data by performing BC encoding on the write data on a page basis, and generates the page data. And storing data in the NAND flash memory device. The nonvolatile memory system of claim 6, wherein the controller stores flag cell information for the page data in the nonvolatile memory device in response to the write command signal. The nonvolatile memory of claim 7, wherein the controller reads the page data from the NAND flash memory device based on the flag cell information stored in the nonvolatile memory device in response to the read command signal. system. The nonvolatile memory system of claim 1, wherein the nonvolatile memory device is a phase-change random access memory (PRAM) device capable of performing an overwrite operation. 10. The non- volatile memory system of claim 9, wherein the non-volatile memory system is made of an embedded multimedia card (EMMC).

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