CN107546230B - Method for depositing gate line gap oxide of 3D NAND device - Google Patents
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Abstract
The embodiment of the invention provides a deposition method of oxide in a gate line gap of a 3D NAND device, wherein the oxide is deposited after a gate line is formed through the gate line gap and cleaned, and the method comprises the following steps: and placing the substrate in a reaction chamber for depositing an oxide, dehumidifying the substrate, and then depositing the gate line gap oxide. The uniform deposition of the oxide on the gate line gap of the 3D NAND device is realized, the coverage rate of the oxide deposition on the surface of the gate line gap is improved, the insulativity of the oxide is improved, the short circuit is reduced, and the performance of the device is optimized.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for depositing a gate line gap oxide of a 3D NAND device.
Background
The NAND flash memory is a non-volatile storage product with light weight and good performance, the 3D NAND is a three-dimensional flash memory type, the limitation of a plane (2D) NAND flash memory is solved by stacking memory particles together, and a stacked memory structure is realized by vertically stacking a plurality of layers of data storage units.
In the manufacturing process of the 3D NAND, as shown in fig. 1, a stacked layer 101 of a silicon nitride layer (not shown) and a silicon oxide layer 102 is first formed on a substrate 100, a channel hole 103 is formed in the stacked layer, and a channel layer is formed in the channel hole; then, a gate line gap 104(gate line) is formed on the stacked layer, the silicon nitride layer in the stacked layer is removed through the gate line gap, the hollow area where the silicon nitride is removed is filled with metal, a gate line 105 is formed, and the gate line is to be used as a control gate of the formed memory device. After the gate line 105 is formed, an oxide film 106 is deposited to separate the gate line 105 from a subsequent metal fill 107, preventing a short circuit from occurring.
In the prior art, the performance of a device is reduced due to poor coverage and uneven thickness of a deposited oxide film, and therefore a method capable of improving the coverage of the film deposited on the surface of a gap of a grid line is needed.
Disclosure of Invention
The invention provides a method for depositing a gate line gap oxide of a 3D NAND device, which improves the covering capability of an oxide film, improves the insulating property of the oxide and optimizes the performance of the device.
The invention provides a deposition method of a gate line gap oxide of a 3D NAND device, which is used for depositing the oxide after a gate line is formed through a gate line gap and cleaned, and comprises the following steps:
placing a substrate in a reaction chamber for oxide deposition, and dehumidifying the substrate;
and depositing the gate line gap oxide.
Optionally, the dehumidification process comprises a plurality of cycles, each cycle comprising: carrying out vacuum treatment on the reaction cavity; and introducing nitrogen or inert gas into the reaction cavity.
Optionally, the vacuum treatment is performed by pumping gas from the reaction chamber through a vacuum pump.
Optionally, the pressure in the reaction chamber after the vacuum treatment is in the range of 0-0.5 torr.
Optionally, the time of the vacuum treatment is determined by the volume of the reaction chamber and the power of the vacuum pump.
Optionally, the number of the cyclic treatment is 20-60.
Optionally, the method further comprises: detecting the humidity in the reaction cavity through a humidity detector; and if the humidity in the reaction chamber is lower than the humidity threshold value, stopping the dehumidification treatment.
Optionally, the forming of the gate line through the gate line slit includes: and filling the metal material and etching back the metal material.
Optionally, the metal material is tungsten.
Optionally, the gate line gap oxide is deposited by atomic layer deposition.
According to the deposition method of the oxide in the gate line gap of the 3D NAND device, after the gate line is formed through the gate line gap and cleaned, the oxide is deposited, the substrate is placed in a reaction cavity for oxide deposition, dehumidification is carried out on the substrate, and then the oxide in the gate line gap is deposited. According to the method, before the gate line gap oxide is deposited, dehumidification is carried out, so that no cleaning liquid is left in the gate line gap before deposition, the gate line gap is dry from top to bottom, the uniform deposition of the gate line gap oxide of the 3D NAND device is improved, the coverage rate of the oxide deposition on the surface of the gate line gap can be effectively improved, the insulating property of the oxide is improved, the short circuit is reduced, and the performance of the device is optimized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 shows a schematic cross-sectional structure of a 3D NAND device after gate line gap oxide deposition;
figure 2 shows a TEM photograph of a 3D NAND device gate line gap oxide formed by a prior art method;
FIG. 3 shows a flowchart of a method for gate line gap oxide deposition for a 3D NAND device in accordance with an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating a deposition process of a gate line gap oxide of a 3D NAND device according to an embodiment of the present application;
fig. 5 shows a TEM photograph of a 3D NAND device gate line gap oxide formed according to the method of the embodiments of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First, in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and it will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
A TEM (transmission electron microscope) photograph of the gate line gap oxide of the 3D NAND device formed by the prior art method as shown in fig. 2, wherein, the images (a), (B), and (C) are photographs of the top, middle, and bottom of the gate line gap, respectively, it can be seen that the oxide deposition in the prior art has different thicknesses at different positions of the gate line gap, for example, in fig. 2: the average thickness of the oxide film at the top of the gate line gap is 22.9nm, the average thickness at the middle is 19.2nm, the average thickness at the bottom is 15.6nm, and the ratio of the average thickness at the bottom to the average thickness at the top is used to obtain that the coverage rate of the oxide at the bottom of the gate line gap is 68.1%, the oxide film is not uniform, and particularly, the oxide film at the bottom of the gate line gap is small in thickness and poor in coverage. Referring to fig. 2(C), in order to clearly see the film formation morphology of the bottom oxide film, the photograph is a photograph after depositing a tungsten film on the oxide film, wherein the black material at the bottom is the tungsten film, and the interface of the oxide film can be highlighted by comparison.
In view of the above problems, the applicant has studied and found that the non-uniformity of the gate line gap oxide, especially the thickness of the oxide thin film from top to bottom, is continuously reduced, which is related to the moisture remaining after the cleaning process, in the 3d nand manufacturing process, the thickness of the formed stacked layer is very thick, having a thickness of several micrometers, the hole depth of the formed gate line gap also reaches several micrometers, after the cleaning, the moisture is easily remained in the deep hole, and the more the moisture remains in the lower portion closer to the hole, the more the non-uniformity of the gate line gap oxide deposition is caused, especially the poorer the coverage in the lower portion closer to the hole is.
Based on the research and discovery, the application provides a deposition method of oxide in a gate line gap of a 3D NAND device, the oxide is deposited after a gate line is formed through the gate line gap and cleaned, and before deposition, a substrate is placed in a reaction cavity for oxide deposition, and dehumidification treatment is carried out on the substrate. For the sake of understanding, the following description is made with respect to the gate line slit, and a process of forming the gate line through the gate line slit and cleaning the same will be described in detail.
As shown in fig. 1, in the manufacturing process of the 3D NAND, a stacked layer 101 of a silicon nitride layer (not shown) and a silicon oxide layer 102 is first formed on a substrate 100. A channel hole 103 is formed in the stacked layer, and a channel layer, which may be a silicon oxide-silicon nitride-silicon oxide-polysilicon-oxide, is formed in the channel hole 103, and may be adjusted according to actual conditions. Forming a gate line gap 104 on the stacking layer, forming an oxide layer on the side wall of the gate line gap, forming a doped region under the gate line gap, wherein the gate line gap is made of a metal material and used for replacing the metal layer in the stacking layer in the manufacturing process, and after the gate line gap is formed, the gate line gap divides the whole storage region into a plurality of block storage regions and finger storage regions on one hand and plays a common source (common source) role on the other hand.
In the embodiment of the present application, the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. As shown in fig. 1, in the present embodiment, the substrate 100 is a bulk silicon substrate for supporting a device structure thereon while being capable of improving film characteristics.
The number of stacked layers determines the number of memory cells in the vertical direction, and the number of stacked layers may be, for example, 8, 32, 64, or the like, and the greater the number of layers, the higher the integration level. The stacked layers may be formed by alternately depositing silicon nitride and silicon oxide in sequence using chemical vapor deposition, atomic layer deposition, or other suitable deposition methods.
Specifically, a photoresist layer is spin-coated on the stacked layer, a patterned photoresist layer is formed through steps such as exposure and development, the pattern of the photoresist layer can be determined by a mask plate used for forming the channel hole in the 3D NAND memory manufacturing process, and the channel hole 103 exposing the substrate is formed through etching the stacked layer by using the patterned photoresist layer as a mask.
After the formation of the channel hole 103, a removal of the photoresist and a formation of a storage layer in the channel hole are performed, the storage layer including a charge trapping layer, which may be, for example, an ONO structure, i.e., a stack of oxide, nitride and oxide, and a channel layer, which may be, for example, a polysilicon layer.
Etching the stacked layer to form the gate line gap 104 may specifically be spin-coating a photoresist layer on the stacked layer; then, forming a patterned photoresist layer through steps of exposure, development and the like, wherein the photoresist pattern is determined by a mask plate; then, performing an etching process, for example, RIE (reactive ion etching) may be adopted to etch the stack layer to form a gate line gap exposing the substrate, which may be stopped when the substrate is etched, or may be used to etch a portion of the substrate; and finally, removing the photoresist layer and cleaning the wafer.
The forming of the gate line through the gate line gap may specifically be: and filling the metal material through the grid line gap and etching back the metal material. By removing the silicon nitride layer in the stack through the gate line slit 104, an acid solution with a high selectivity ratio of silicon nitride to silicon oxide, such as phosphoric acid (H) in general, can be selectively removed3PO4) And then cleaning the acid liquor. The original silicon nitride region is filled with a metal layer 105 and etched back to form a gate line, which serves as the control gate of the memory device. The metal layer may be tungsten, or may be other metal that can be used as a gate, and is not limited herein.
The metal material is etched back, the metal layer is etched back by the solution with the high selection ratio of the metal and the silicon oxide in the embodiment of the application, so that the silicon oxide layer is exposed to form the grid line, further, the surface of the metal material is sunken to some extent relative to the surface of the silicon oxide layer by etching back the metal material, and for a device, the safety is improved.
After the grid line is formed, the substrate needs to be cleaned to prevent the residual solution from corroding the metal layer, and the cleaning mode can be solvent or specific solution. After cleaning, an oxide film 106 is deposited to separate the metal layer, which is the control gate, from the subsequent metal fill 107, preventing shorts from occurring.
After cleaning, deposition of gate line gap oxide is performed, and as shown in fig. 3, the application provides a deposition method of gate line gap oxide of a 3D NAND device. The steps of the oxide deposition method are as follows.
Step 301, placing a substrate in a reaction chamber for oxide deposition, and performing dehumidification treatment on the substrate.
The dehumidification treatment comprises a plurality of circulation treatments, and each circulation treatment comprises the following steps: carrying out vacuum treatment on the reaction cavity; and introducing nitrogen or inert gas into the reaction cavity. The control of the dehumidification process may include opening and closing of a vacuum pump and control of introducing nitrogen or inert gas, and in actual operation, the control may be performed manually or by program setting, which is not limited herein.
The reaction chamber is used for oxide deposition, a vacuum pump used for vacuum treatment and an air inlet pipe used for introducing air are connected, the vacuum pump extracts the air in the reaction chamber, the air in the reaction chamber is reduced, the internal air pressure is reduced, and a low-pressure environment relative to the atmospheric pressure is formed. In the low pressure environment, the moisture at the bottom of the grid line gap is reduced because of the boiling point, the water vapor is easily evaporated to be diffused into the reaction cavity and then is pumped away by the vacuum pump, and through the circulation operation, the moisture in the grid line gap and the reaction cavity is gradually reduced.
The effect of introducing nitrogen or inert gas is to supplement the gas pumped out from the cavity, so that the gas pressure in the cavity is raised to atmospheric pressure, and meanwhile, the nitrogen or inert gas has stable chemical properties and can be used as protective gas in the reaction cavity. In other embodiments of the present disclosure, after the nitrogen gas or the inert gas is introduced, the pressure in the cavity may not be equal to the atmospheric pressure, and the implementation of the embodiments of the present disclosure is not affected.
The vacuum treatment of the reaction cavity can be realized by vacuumizing the reaction cavity by using a vacuum pump or by other vacuum realization modes. The pressure after the vacuum treatment is determined by the power of the vacuum pump and the volume of the reaction chamber, and in the embodiment of the present application, the measurement of the result of the dehumidification treatment can be based on the pressure after the vacuum treatment and the number of times of the vacuum treatment. Preferably, the pressure after the vacuum treatment may be 0 to 0.5torr, and the number of cycles may be 20 to 60. In other embodiments of the present application, the pressure after vacuum treatment and the number of cycles can be adjusted appropriately according to the power of the vacuum pump and the volume of the reaction chamber, so as to achieve effective dehumidification of the substrate.
The nitrogen or inert gas can be introduced into the reaction cavity by connecting a nitrogen or inert gas cylinder through a gas inlet pipe, and the flow of the gas is controlled by a control valve to introduce the gas into the reaction cavity, so that the low pressure in the reaction cavity after vacuum treatment is increased, and the next cycle treatment can be conveniently carried out. Wherein, too big gas flow can lead to the gaseous pressure unstability in the chamber and gas waste, and too little flow leads to the time waste easily. In practice, it is preferred that nitrogen or inert gas is introduced into the reaction chamber at a flow rate of 5SLM (L/min) for 1-5 minutes in the specific embodiment of the present application.
After step S01, it is also possible to: detecting the humidity in the reaction cavity through a humidity detector; and if the humidity in the reaction chamber is lower than the humidity threshold value, stopping the dehumidification treatment.
The humidity detector can detect the moisture content and is used for monitoring the water vapor content in the reaction cavity, when the humidity in the reaction cavity reaches a certain degree, the moisture in the gap of the grid line is completely removed, the dehumidification treatment can be stopped, and the next operation is carried out.
And the purpose of carrying out dehumidification treatment on the substrate is to remove residual moisture on the surface of the gap of the grid line. Through the cyclic vacuum treatment and let in nitrogen gas or inert gas, make the moisture of grid line gap depths evaporate gradually to being taken out by the vacuum pump, reaching the purpose of dehumidification, and then making oxide film's deposit go on smoothly, form even film, thereby have better insulating effect.
Specifically, after the gate line is formed, in order to avoid the corrosion effect of the residual solution on the metal layer, the surface of the gate line gap needs to be cleaned, a small amount of moisture remains at the bottom of the gate line gap, and in the subsequent oxide deposition process, the moisture is evaporated in the reaction chamber, so that the film formation of an oxide film is influenced. Since the deposition of oxide is generally vapor deposition, it is necessary to react and deposit the vapor of gaseous or liquid reactant and other gases required for reaction on the surface of the substrate under vacuum during the deposition process. In a vacuum state, the presence of moisture can cause the moisture to vaporize to form a large number of water molecules in the reaction chamber, directly affecting the reaction and deposition of the gases.
Fig. 4 is a schematic diagram showing the actual operation of the embodiment of the present application, wherein the abscissa of the diagram is time, the ordinate is air pressure, and the air pressure after vacuum treatment is 0.3 torr. In the present embodiment, the volume of the reaction chamber for depositing the oxide is 230-250L, which corresponds to 4.6KW of vacuum pump power for vacuum treatment in the time range of 1 minute. In other embodiments of the present application, the time of the vacuum treatment may be adjusted. The nitrogen was introduced into the reaction chamber for 1 minute and the number of cycles was 50.
Step S02, depositing gate line gap oxide.
The oxide layer can be oxide, the gate line gap oxide can be deposited by CVD (chemical vapor deposition), other deposition modes can be adopted, and the thickness of the gate line gap oxide can be selected according to actual needs. As shown in fig. 4, specifically, the pressure during the oxide deposition is 3torr, and in other embodiments of the present application, the pressure during the oxide deposition may also be adjusted according to actual conditions.
As shown in fig. 5, TEM photographs of gate line gap oxide of a 3D NAND device formed according to the method of the embodiment of the present application are shown, wherein, the photographs of the top, middle and bottom of the gate line gap are shown in (a), (B) and (C), respectively. It can be seen that the average thickness of the oxide at the top of the gate line gap is 28.2nm, the average thickness at the middle is 27.6nm, the average thickness at the bottom is 27.8nm, the ratio of the average thickness at the bottom to the average thickness at the top is used to obtain 98.6% coverage of the oxide at the bottom of the gate line gap, and the oxide at the bottom forms a uniform film.
According to the method for detecting the channel deep hole by the deposition method of the oxide in the gate line gap of the 3D NAND device, the oxide is deposited after the gate line is formed through the gate line gap and cleaned, the substrate is placed in a reaction cavity for oxide deposition, dehumidification is carried out on the substrate, and deposition of the oxide in the gate line gap is carried out. The uniform deposition of the oxide of the gate line gap of the 3DNAND device is realized, the coverage rate of the oxide deposition on the surface of the gate line gap is improved, the insulativity of the oxide is improved, the existence of short circuit is reduced, and the performance and the quality of the device are optimized.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, they are described in a relatively simple manner, and reference may be made to some descriptions of method embodiments for relevant points. The above-described system embodiments are merely illustrative, wherein the modules or units described as separate parts may or may not be physically separate, and the parts displayed as modules or units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Claims (10)
1. A deposition method of oxide on a gate line gap of a 3D NAND device is characterized in that after a gate line is formed through the gate line gap and cleaned, the oxide is deposited, and the deposition method comprises the following steps:
placing a substrate in a reaction chamber for oxide deposition, and dehumidifying the substrate;
depositing the gate line gap oxide;
wherein the dehumidification process comprises a plurality of cycles, each cycle comprising:
carrying out vacuum treatment on the reaction cavity to reduce the air pressure in the reaction cavity;
when the air pressure in the reaction cavity is lower than the atmospheric pressure, gas is introduced into the reaction cavity so as to raise the low air pressure after vacuum treatment in the reaction cavity.
2. The method of claim 1, wherein said introducing gas into the reaction chamber comprises:
and introducing nitrogen or inert gas into the reaction cavity.
3. The method of claim 2, wherein the vacuum processing comprises: and pumping the gas in the reaction cavity through a vacuum pump.
4. The method of claim 3, wherein the pressure in the reaction chamber after the vacuum treatment is in the range of 0-0.5 torr.
5. The method of claim 4, wherein the time of the vacuum treatment is determined by the volume of the reaction chamber and the power of the vacuum pump.
6. The method of claim 2, wherein the number of cycles is 20-60.
7. The method according to any one of claims 1-6, further comprising:
detecting the humidity in the reaction cavity through a humidity detector;
and if the humidity in the reaction chamber is lower than the humidity threshold value, stopping the dehumidification treatment.
8. The method of any of claims 1-6, wherein forming the grid lines through the grid line gaps comprises:
and filling the metal material and etching back the metal material.
9. The method of claim 8, wherein the metallic material is tungsten.
10. The method of any of claims 1-6, wherein the depositing of the gridline gap oxide is performed using atomic layer deposition.
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