CN107546114B - Preparation method of junction terminal of SiC high-voltage power device - Google Patents
Preparation method of junction terminal of SiC high-voltage power device Download PDFInfo
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- CN107546114B CN107546114B CN201710801218.0A CN201710801218A CN107546114B CN 107546114 B CN107546114 B CN 107546114B CN 201710801218 A CN201710801218 A CN 201710801218A CN 107546114 B CN107546114 B CN 107546114B
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Abstract
The invention discloses a preparation method of a junction terminal of a SiC high-voltage power device. Firstly, the step number is determined according to the blocking voltage requirements of different levels (2)nLevel) and performing mask layout graphic structure design; then, a multi-step structure is formed on the SiC sample wafer through a multi-step preparation process (including preparing a hard mask layer, etching a step region and removing a silicon oxide hard mask layer), and finally, 2 steps are formed through n +1 step etchingnA step; for manufacturing the junction terminal of the SiC high-voltage power device with the multi-stage steps, the preparation can be completed only by carrying out step etching for a few times; therefore, the method can realize multi-step, greatly improve the blocking voltage of the SiC high-voltage power device, and greatly simplify the preparation process of the multi-step junction terminal, thereby having great application prospect in the SiC high-voltage power device.
Description
Technical Field
The invention belongs to the technical field of ultra large scale integrated circuit (ULSI) process manufacturing, and particularly relates to a preparation method of a junction terminal of a SiC-based high-voltage power device.
Background
The basic characteristics of the power semiconductor device are high voltage, large current and high temperature resistance, which requires the manufacturing material to have a wider forbidden band, a higher critical avalanche breakdown electric field strength and a higher thermal conductivity. Compared with the traditional silicon material, the silicon carbide is favored in the application fields of high temperature, high frequency, high power, radiation resistance and the like due to the comprehensive dominant physical characteristics (high breakdown electric field intensity, superior thermal stability, high carrier saturation drift velocity and high thermal conductivity) of the silicon carbide, is an ideal material for realizing high-voltage high-power devices, and also becomes one of the mainstream development directions of modern power devices.
The development of the power device towards a higher voltage direction is theoretically limited by the avalanche breakdown phenomenon, which is closely related to the electric field distribution inside the device structure, and the thicker the drift layer of the power device is, the lower the doping concentration is, the higher the blocking voltage can be realized. In an actual SiC power device, due to problems such as SiC material defects, the thickness of the drift layer cannot grow too thick in the SiC power device material growth process. On the other hand, in the SiC power device, due to the discontinuity of the junction, there is curvature at the edges and corners of the junction, resulting in dense surface electric line, and the electric field intensity outside the junction is higher than that inside the device, resulting in premature breakdown of the device. This effect seriously affects the blocking characteristics of the power device. For SiC high-voltage power devices, the junction termination expansion technology is an effective means for relieving the electric field concentration effect at the outer edge of the junction and improving the breakdown voltage of the devices, and has the advantages of simple process realization, low requirement on junction depth, high efficiency of improving the breakdown voltage, small occupied area of the devices and the like.
The junction termination technology is to improve the breakdown voltage of the device by relieving the electric field concentration effect at the outer edge of the junction, and can be divided into an edge extension structure and an etching step structure according to the difference of the structures, and mainly comprises a field limiting ring structure, a metal field plate structure and a JTE technology. The field limiting ring structure has the advantage of simple process, but is very sensitive to interface charges and puts strict requirements on the precise control of junction depth. Field plate terminations are a conventional technique for device edge terminations, with high fields supported by an oxide layer under a metal field plate, however, in SiC devices the electric field in the blocking state can be very high and high oxide fields can lead to long term reliability issues. JTE technology, proposed by Temple in 1977 on IEEE Transactions on electronic devices, can be modified to mitigate the electric field concentration effect by selectively increasing the charge in the junction to form junction termination extension regions, and its implementation methods include ion implantation and step etching. Compared with an ion implantation method, the step etching method is simpler in process and high in efficiency, and the problems of defect damage, surface roughening and the like caused by high-temperature annealing are solved, so that an etching JTE structure is generally adopted for SiC devices with the voltage of more than 10 kV.
For the etching JTE technology, the more gentle the charge distribution gradient, the more significant the effect of alleviating the concentration of the outer edge electric field, and the more significant the increase of the blocking voltage of the power device, which requires the preparation of as many as tens of steps to realize high blocking voltage. However, if a plurality of steps are prepared in a manner of preparing one step by each step of etching process, the complexity and the manufacturing cost of the device preparation are greatly increased, and the reliability and the repeatability of the device are greatly reduced by as many as tens of times of etching. Therefore, the invention provides a process preparation method for preparing a multistage etched step JTE structure aiming at the problems, the method can realize the multistage etched step JTE structure, does not increase the complexity of the device preparation process, and has very obvious application prospect in high-voltage power devices.
Disclosure of Invention
Aiming at the problems of the junction terminal of the SiC high-voltage power device, the invention provides a preparation method of the junction terminal of the SiC high-voltage power device, which effectively simplifies the process technology of the junction terminal preparation while realizing multi-stage step etching and finally achieves the purpose of greatly improving the blocking voltage of the SiC high-voltage power device.
The technical scheme of the invention is as follows:
a preparation method of a junction terminal of a SiC high-voltage power device is characterized by comprising the following preparation steps:
(1) providing a SiC semiconductor substrate for preparing a high-voltage power device; the thickness of the SiC material used for preparing the material layer of the junction terminal structure is D;
(2) a level 1 step area was prepared. Defining a 1-level step region by photoetching, and removing photoresist to form a SiC etching hard mask after reactive ions etch away a silicon oxide layer in the 1-level step region; then, etching a step area by etching methods such as Reactive Ion Etching (RIE) and inductively coupled plasma etching (ICP) with the etching depth d1, and removing the silicon oxide hard mask layer by methods such as hydrofluoric acid (HF) or buffered oxide etching solution (BOE) to form a level 1 step;
(3) a level 2 step area was prepared. On the level 1 step, firstly, manufacturing a silicon oxide hard mask layer (the manufacturing method is the same as the method in the step 2), then etching the step region by etching methods such as RIE and ICP, the etching depth is (D-D1)/2, and then removing the silicon oxide hard mask layer by methods such as HF acid or BOE, and forming a level 2 step region;
(4) preparation 2nA stepped region. The same manufacturing method is adopted according to design requirements, 2 n-1A silicon oxide hard mask layer is manufactured on the step, and then etching is carried out to manufacture 2nStep level with etching depth of (D-D1)/2nThen removing the silicon oxide hard mask layer to form 2nA step, wherein n > 1;
(5) and preparing a high-voltage device isolation region. The same method of preparation, in 2nFirstly, a silicon oxide hard mask layer is manufactured on the step, and then a step area is etched by etching methods such as RIE and ICP, wherein the etching depth is (D-D1)/2n + dOE μm，dOEThe value range of the isolation over-etching amount is 1 ~ 3 mu m, and then the silicon oxide hard mask layer is removed by adopting methods such as HF acid or BOE and the like, so that the isolation of the SiC high-voltage power device is completed.
The semiconductor material includes, but is not limited to, Si material, SiC material, GaN material, AlN material, or the like.
Compared with the prior art, the invention has the beneficial effects that:
by the design of the etching mask, the invention can effectively reduce the etching times in the device preparation process, reduce the process complexity and greatly save the device preparation cost while realizing the multi-stage etching of the step junction terminal and improving the blocking voltage of the high-voltage power device. Taking the implementation of 16-level JTE structure as an example, a common etching method needs 16 etching steps to complete the preparation of 16-level JTE structure. By adopting the method provided by the invention, the JTE structure with 16 levels of steps can be completed only by etching for 5 times, so that the etching times are greatly reduced. If a JTE structure with more stages of steps is realized, the method can more obviously reduce the etching times. Compared with the traditional etching method, the method can more simply realize the JTE structure of the multistage steps, greatly improve the blocking characteristic of the SiC power device, obviously reduce the manufacturing cost of the device and improve the reliability and repeatability of the prepared device.
Drawings
Fig. 1-8 are step-by-step flow charts of the present invention for preparing junction terminals of SiC high voltage power devices.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
by taking the preparation of the SiC high-voltage power device with 16 steps as an example, etching is performed for 5 times, and according to the preparation schematic diagram of the junction terminal of the SiC high-voltage power device shown in the figures 1 to 8, the specific preparation steps are as follows:
step 1: a SiC material structure for preparing a high-voltage power device is provided. As shown in fig. 1, the thickness of the layer of SiC material in which the junction termination is made is D. Wherein the semiconductor material can be Si material, SiC material, GaN material, AlN material, etc.
Step 2: to carry out
And (4) level etching to manufacture a level 1 step. Depositing a silicon oxide layer on the SiC material layer, defining a 1-level well region through photoetching, etching the silicon oxide layer in the 1-level step region through RIE, and removing the photoresist to form a SiC etching hard mask. And etching the SiC step region by etching methods such as RIE (reactive ion etching) and ICP (inductively coupled plasma) to an etching depth d1, removing the silicon oxide hard mask layer by using methods such as HF (hydrogen fluoride) acid or BOE (boron oxide) to form a SiC 1-level step, and finishing as shown in FIG. 2.
And step 3: to carry out
And (4) level etching to manufacture a 2-level step. Firstly, a silicon oxide hard mask layer is manufactured (the manufacturing method is the same as the method in the step 2), then the SiC step region is etched by etching methods such as RIE and ICP, the etching depth is (D-D1)/2, then the silicon oxide hard mask layer is removed by methods such as HF acid or BOE, a SiC 2-level step is formed, and the graph shown in FIG. 3 is completed.
And 4, step 4: to carry outAnd (4) making 4-level steps by level etching. Firstly, a silicon oxide hard mask layer is manufactured (the manufacturing method is the same as the method in the step 2), then the SiC step area is etched by etching methods such as RIE and ICP, the etching depth is (D-D1)/4, and then the method is adoptedAnd removing the silicon oxide hard mask layer by using HF acid or BOE and other methods to form a SiC 4-level step, and finishing the process shown in FIG. 4.
And 5: to carry out
And (4) making 8-level steps by level etching. Firstly, a silicon oxide hard mask layer is manufactured (the manufacturing method is the same as the method in the step 2), then the SiC step region is etched by etching methods such as RIE and ICP, the etching depth is (D-D1)/8, then the silicon oxide hard mask layer is removed by methods such as HF acid or BOE, the SiC 8-level step is formed, and the graph shown in FIG. 5 is completed.
Step 6: to carry out
The level etching makes 16 steps. Firstly, a silicon oxide hard mask layer is manufactured (the manufacturing method is the same as the method in the step 2), then the SiC step region is etched by etching methods such as RIE and ICP, the etching depth is (D-D1)/16, then the silicon oxide hard mask layer is removed by methods such as HF acid or BOE, the SiC 16-level step is formed, and the graph shown in FIG. 6 is completed.
And 7: and carrying out isolation etching on the SiC high-voltage device. Firstly, a silicon oxide hard mask layer is manufactured (the manufacturing method is the same as the method in the step 2), and then the SiC step region is etched by etching methods such as RIE and ICP, and the etching depth is (D-D1)/16+ DOE μm，dOEThe isolation over-etching amount (the value range is 1 ~ 3 μm) is adopted, and the isolation etching of the SiC high-voltage power device shown in FIG. 7 is completed.
And 8: the isolation mask is removed. And removing the silicon oxide hard mask layer by adopting methods such as HF acid or BOE and the like to form a final structure of the junction terminal of the SiC high-voltage device, and finishing as shown in the figure 8.
The invention can effectively realize the multi-stage step junction terminal structure, thereby obviously improving the blocking voltage of the SiC high-voltage power device; meanwhile, compared with the conventional multi-step etching method, the method can greatly reduce the process etching times of the SiC multi-step junction terminal, reduce the process complexity and the device preparation cost, and improve the reliability and the repeatability of the preparation of the SiC power device. In general, compared with the existing process preparation method, the preparation method of the SiC high-voltage power device multi-stage step junction terminal can obviously improve the blocking voltage of the SiC high-voltage power device and effectively reduce the process complexity, and has a very obvious application prospect in the SiC high-voltage power device.
The above method for preparing the junction terminal of the SiC-based high-voltage power device proposed by the present invention is described in detail through the preferred embodiments, and it should be understood by those skilled in the art that the above is only the preferred embodiments of the present invention, and certain modifications or alterations may be made to the manufacturing method of the present invention within the scope not departing from the spirit of the present invention, for example, a junction terminal structure with any step number may be implemented by using the method; the preparation method is not limited to the disclosure in the examples, and all equivalent changes and modifications made according to the claims of the present invention should be covered by the scope of the present invention.
Claims (3)
1. A preparation method of a junction terminal of a SiC high-voltage power device is characterized by comprising the following preparation steps:
(1) providing a SiC semiconductor substrate for preparing a high-voltage power device; the thickness of the SiC material used for preparing the material layer of the junction terminal structure is D;
(2) defining a 1-level step region by photoetching, and removing photoresist to form a SiC etching hard mask after reactive ions etch away a silicon oxide layer in the 1-level step region; then, etching the step area with the etching depth of d1, and then removing the silicon oxide hard mask layer to form a level 1 step;
(3) on the level 1 step, firstly, manufacturing a silicon oxide hard mask layer, then etching the step region to the etching depth of (D-D1)/2, and then removing the silicon oxide hard mask layer to form a level 2 step region;
(4) the same manufacturing method is adopted according to design requirements, 2 n-1A silicon oxide hard mask layer is manufactured on the step, and then etching is carried out to manufacture 2nStep level with etching depth of (D-D1)/2nThen removing the silicon oxide hard mask layer to form 2nA step, wherein n > 1;
(5) in 2nFirst, silicon oxide is made on the stepHard mask layer, and etching the step region to a depth of (D-D1)/2n + dOE μm，dOEIs to isolate the over-etching amount, dOEThe value range of the silicon oxide hard mask layer is 1 ~ 3 mu m, and then the silicon oxide hard mask layer is removed to finish the isolation of the SiC high-voltage power device.
2. The method for preparing the junction terminal of the SiC high-voltage power device according to claim 1, wherein: the etching method adopted by the etching step area is a reactive ion etching method or an inductive coupling plasma etching method.
3. The method for preparing the junction terminal of the SiC high-voltage power device according to claim 1, wherein: and the silicon oxide hard mask layer is removed by adopting hydrofluoric acid or buffered oxide etching liquid.
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| CN109378270A (en) * | 2018-09-29 | 2019-02-22 | 大连芯冠科技有限公司 | The preparation method of the more field plates of power device |
| CN109473354A (en) * | 2018-10-10 | 2019-03-15 | 华中科技大学 | A kind of preparation method and product of the drift step recovery diode based on silicon carbide |
| CN109950300B (en) * | 2019-03-04 | 2021-12-10 | 中国工程物理研究院电子工程研究所 | Bidirectional voltage-resistant power device reverse terminal structure based on drift region step etching |
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