CN107527913A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents

A kind of semiconductor devices and its manufacture method and electronic installation Download PDF

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Publication number
CN107527913A
CN107527913A CN201610443324.1A CN201610443324A CN107527913A CN 107527913 A CN107527913 A CN 107527913A CN 201610443324 A CN201610443324 A CN 201610443324A CN 107527913 A CN107527913 A CN 107527913A
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China
Prior art keywords
bit line
dielectric layer
layer
interlayer dielectric
core space
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CN201610443324.1A
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CN107527913B (en
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罗文军
杨海玩
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND

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  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention provides a kind of semiconductor devices and its manufacture method and electronic installation, is related to technical field of semiconductors.The semiconductor devices includes：Substrate, the substrate include core space, are provided with interlayer dielectric layer on the substrate；Spaced some first bit lines on the interlayer dielectric layer in the core space；The first dielectric layer of the interlayer dielectric layer in first bit line and the core space is covered, wherein, formed with air-gap in first dielectric layer between adjacent first bit line in the core space.The semiconductor devices of the present invention sets air-gap between adjacent bit lines, reduce bit line capacitance, and then reduce the coupled noise between bit line, the also homogeneous unit of availability, such as, the homogeneous unit of the homogeneous unit of threshold voltage (Vt), Random telegraph noise, and improve the RC retardation ratio of bit line so that device has higher performance.

Description

A kind of semiconductor devices and its manufacture method and electronic installation
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and manufacture Method.
Background technology
As the size reduction of NAND-flash memory is to 2Xnm, 1Xnm node and following, to adjacent bit lines (Bit Line, abbreviation BL) between the size of space (CD) requirement control mutually strain more and more strictly, therefore, air-gap (Air Gap scheme) is paid close attention to because it has advantages below, first, capacitance is reduced using air-gap, to reduce between bit line Coupled noise (coupling noise), secondly, by reducing capacitance, the homogeneous unit of availability is gone back, for example, threshold value The homogeneous unit of the homogeneous unit of voltage (Vt), Random telegraph noise (Random telegraphic noise, abbreviation RTN), In addition, using air-gap, it can also improve the RC retardation ratio of bit line.
In the bit line forming process of current nand flash memory, often using W or Cu mosaic technology, first depositing bitlines Between sull, then etching oxide film, redeposition forms W or Cu, therefore, sky is hardly formed between bit line Air gap.
And in view of the plurality of advantages of air-gap, it is necessary to a kind of manufacture method of new semiconductor devices is proposed, to improve The performance of device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices, including：
Substrate, the substrate include core space, are provided with interlayer dielectric layer on the substrate；
Spaced some first bit lines on the interlayer dielectric layer in the core space；
The first dielectric layer of the interlayer dielectric layer in first bit line and the core space is covered, wherein, Formed with air-gap in first dielectric layer between adjacent first bit line in the core space.
Further, some first conductive plungers are provided with the interlayer dielectric layer of the corresponding core space, it is each described First conductive plunger electrically connects with drain electrode below or source electrode, wherein, part first bit line is corresponding to being disposed below First conductive plunger electrical connection.
Further, the substrate also includes peripheral region, is each formed with including floating in the peripheral region and the core space Grid, separation layer, some gate stacks of control gate, the interlayer dielectric layer cover some gate stacks.
Further, in the interlayer dielectric layer of the corresponding peripheral region formed with some second conductive plungers, each Second conductive plunger electrically connects with the gate stack being disposed below.
Further, it is provided with second bit line at some intervals on the interlayer dielectric layer of the peripheral region, described Two bit lines are parallel with first bit line, and each second bit line is electrically connected second conduction being disposed below Connector.
Further, first dielectric layer also covers the part interlayer in second bit line and the peripheral region Dielectric layer.
Further, it is additionally provided with the second dielectric layer on first dielectric layer.
Further, the spacing distance between adjacent first bit line is less than the spacer between adjacent second bit line From.
Further, the material of first bit line and second bit line is tungsten.
Further, between two first bit lines electrically connected respectively with adjacent first conductive plunger, also It is provided with some first bit lines not electrically connected with first conductive plunger.
Further aspect of the present invention provides a kind of manufacture method of semiconductor devices, including：
Substrate is provided, the substrate includes core space and peripheral region, on the substrate formed with interlayer dielectric layer, in institute The hard mask layer that patterning is formed on the interlayer dielectric layer in core space is stated, the hard mask layer of the patterning includes some open Mouthful, the pattern of the first bit line in the corresponding predetermined core space formed of opening；
The hard mask layer that bit line material layer covers the patterning is formed, and in the core space and the peripheral region cruelly The interlayer dielectric layer of dew；
The photoresist layer of patterning is formed on the bit line material layer in the peripheral region；
Using the photoresist layer of the patterning as mask, the bit line material layer is etched, is located at the core space to be formed The first interior bit line, and some spaced second bit lines in the peripheral region, wherein, in the core space Interior, the etching stopping is on the top surface of the hard mask layer, and in the peripheral region, the etching stopping is situated between in the interlayer On the surface of electric layer, first bit line is parallel with second bit line；
Remove the photoresist layer of the hard mask layer and the patterning；
The first dielectric layer is formed, to cover first bit line and second bit line and the interlayer dielectric of exposure Layer, wherein, formed with air-gap in first dielectric layer between adjacent first bit line in the core space.
Further, the method for forming the hard mask layer of the patterning, comprises the following steps：
Hard mask layer is formed on the interlayer dielectric layer, is formed and is arranged at intervals on the hard mask layer in the core space Some core patterns；
Clearance wall is formed in the side wall of each core pattern；
Remove the core pattern；
Using the clearance wall as hard mask layer described in mask etching, stop on the interlayer dielectric layer formed it is some described Opening, and the clearance wall is removed, to form the hard mask layer of the patterning.
Further, before the hard mask layer is formed, in addition to the first etch-stop is formed on the interlayer dielectric layer Only the step of layer.
Further, also include forming the second etching stop layer on the hard mask layer before the core pattern is formed The step of.
Further, be each formed with including in the peripheral region and the core space floating boom, separation layer, control gate it is some Gate stack, the interlayer dielectric layer cover some gate stacks.
Further, some first conductive plungers are provided with the interlayer dielectric layer of the corresponding core space, it is each described First conductive plunger electrically connects with drain electrode below or source electrode, wherein, part first bit line is corresponding to being disposed below First conductive plunger electrical connection.
Further, in the interlayer dielectric layer of the corresponding peripheral region formed with some second conductive plungers, each Second conductive plunger electrically connects with the gate stack being disposed below, and each second bit line is electrically connected and is located at Second conductive plunger below.
Further, the material of the hard mask layer includes α carbon.
Further, the bit line material layer includes tungsten.
Further, the bit line material layer is formed using sputtering method.
Further, after first dielectric layer is formed, in addition to deposition forms second on first dielectric layer The step of dielectric layer.
Further aspect of the present invention also provides a kind of electronic installation, and it includes foregoing semiconductor devices.
The semiconductor devices of the present invention sets air-gap between adjacent bit lines, reduces bit line capacitance, and then reduce bit line Between coupled noise, the also homogeneous unit of availability, for example, the homogeneous unit of threshold voltage (Vt), Random telegraph noise Homogeneous unit, and improve the RC retardation ratio of bit line so that device has higher performance.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the sectional view of the semiconductor devices in the specific embodiment of the present invention；
Fig. 2A-Fig. 2 I show a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention The sectional view of the structure of formation；
Fig. 3 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the present of invention；
Fig. 4 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention can be able to without one or more of these details Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation, The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore, Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and structure will be proposed in following description, to explain this hair The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention There can also be other embodiment.
Embodiment one
Detailed introduction is done to the semiconductor devices of the present invention below with reference to Fig. 1, wherein, Fig. 1 shows the one of the present invention The sectional view of semiconductor devices in specific embodiment.
The semiconductor devices of the present invention can be any semiconductor devices well known to those skilled in the art, as showing Example, the semiconductor devices is nand flash memory.
The semiconductor devices of the present invention includes following primary structure：Substrate, the substrate includes core space, in the substrate On be provided with interlayer dielectric layer；Spaced some first bit lines on the interlayer dielectric layer in the core space, its In, first bit line extends in a first direction；The first dielectric layer is set to cover in first bit line and the core space The interlayer dielectric layer, wherein, in first dielectric layer between adjacent first bit line in the core space Formed with air-gap.
Specifically, as shown in figure 1, the substrate 100 includes core space and peripheral region, in Fig. 1 on the left of cut-off rule shown in For core space, the non-peripheral region shown in cut-off rule right side, wherein being each formed with including in the peripheral region and the core space Floating boom, separation layer, some gate stacks of control gate.
Wherein, wherein the core space has higher integrated level, gate stack is intensive, wherein the number of the gate stack Mesh is not limited to a certain number range, and the peripheral region has several gate stacks, and gate stack is sparse, for simplification figure In do not show that gate stack.
The substrate 100 includes Semiconductor substrate, and some gate stacks in peripheral region and core space are arranged at semiconductor The top of substrate, to put it more simply, only showing substrate 100 with a blank in Fig. 1.
The Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI), Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and Germanium on insulator (GeOI) etc..Can also be formed with fleet plough groove isolation structure (not shown) in the Semiconductor substrate.
Exemplarily, it is also formed with depositing tunnel oxide 101, the tunnelling between gate stack and Semiconductor substrate Oxide layer is oxide, in the present invention optional SiO2Layer is used as tunnel oxide, and the thickness of the tunnel oxide can be 1-20nm, but the thickness is not limited solely to, those skilled in the art can be adjusted as needed, to obtain more preferable effect Fruit.
Wherein, the material of floating boom can select semi-conducting material, such as silicon, polysilicon or Ge etc., it is not limited to certain A kind of material selection polysilicon of material, in this embodiment floating boom.
Formed with separation layer on floating boom, wherein the material of the separation layer can select insulating materials commonly used in the art, Such as the one or more in oxide, nitride.
Such as (structure of oxidenitride oxide is exhausted by the material selection ONO of the separation layer in this embodiment Edge separation layer).
Control gate is provided with the separation layer, wherein, the material of the control gate can select semi-conducting material, example Such as silicon, polysilicon or Ge, it is not limited to the material selection polycrystalline of a certain material, the in this embodiment control gate Silicon.
Wherein, it is also formed with source/drain in the Semiconductor substrate of the part of grid pole lamination side in the core space.
Interlayer dielectric layer 101 is provided with the substrate 100, the interlayer dielectric layer further covers the core space With all gate stacks in peripheral region.Interlayer dielectric layer can use such as SiO2, fluorocarbon (CF), carbon doped silicon oxide Or carbonitride of silicium (SiCN) etc. (SiOC).Or the film that SiCN films are formd on fluorocarbon (CF) can also be used Deng.Fluorocarbon is with fluorine (F) and carbon (C) for main component.Fluorocarbon can also be used with noncrystal (noncrystalline Property) construction material.Interlayer dielectric layer can also use the Porous such as carbon doped silicon oxide (SiOC) to construct.
In one example, some first conductive plungers are provided with the interlayer dielectric layer 101 of the corresponding core space 1021, each first conductive plunger 1021 electrically connects with corresponding drain electrode or source electrode below, for example, in the core It is spaced apart in area to be electrically connected first conductive plunger 1021 formed with several drain electrodes, then each drain electrode.
In one example, it is conductive formed with some second in the interlayer dielectric layer 101 of the corresponding peripheral region Connector 1022, each second conductive plunger 1022 electrically connect with the gate stack being disposed below.
Wherein, first conductive plunger 1021 and second conductive plunger 1022 can be that those skilled in the art are ripe Any kind of conductive plunger known, it can be the tungsten conductive plunger that material is tungsten (W).
Further, spaced some first bit lines 1031 on the interlayer dielectric layer 101 in the core space, Wherein, first bit line 1031 extends on the surface of the interlayer dielectric layer 101.
Wherein, first bit line 1,031 first conductive plunger 1021 corresponding with being disposed below in part is electrically connected Connect.
Further, in two first bit lines 1031 electrically connected respectively with adjacent first conductive plunger 1021 Between, it is additionally provided with some first bit lines 1031 not being connected with any first conductive plunger electricity 1021.
In one example, the second at some intervals is provided with the interlayer dielectric layer 101 of the peripheral region Line 1032, second bit line 1032 is parallel with first bit line 1031, and each second bit line 1032 is electrically connected respectively Connect second conductive plunger 1022 being disposed below.
Wherein, the spacing distance between adjacent first bit line 1031 is less than between adjacent second bit line 1032 Spacing distance.
The material of first bit line 1031 and second bit line 1032 can use well known to those skilled in the art Any conductive material, such as metal material, metal material can include but is not limited to one kind in Cu, Al, W, Ag Or it is several, in the present embodiment, the preferably materials'use tungsten (W) of first bit line 1031 and second bit line 1032.
Further, to set the first dielectric layer 105 to cover described in first bit line 1031 and the core space Interlayer dielectric layer 101, wherein, first dielectric layer between adjacent first bit line 1031 in the core space Formed with air-gap 1051 in 105.
Due to the K values of air it is more much lower than the K values of oxide (air K values are about 1, the K values of oxide be about 3.9), because This air-gap can reduce the electric capacity between bit line, and then reduce the coupled noise (coupling noise) between bit line, secondly, By reducing capacitance, the also homogeneous unit of availability, for example, the homogeneous unit of threshold voltage (Vt), random telegraph are made an uproar The homogeneous unit of sound (Random telegraphic noise, abbreviation RTN), in addition, using air-gap, can also improve bit line RC retardation ratio.
Wherein, the first dielectric 105 also further covers whole peripheral region layer by layer, specifically, first dielectric layer 105 Cover the part interlayer dielectric layer 101 in second bit line 1032 and the peripheral region.Due to adjacent second bit line Spacing distance between 1032 is big, is not in air-gap between the second bit line therefore.
First dielectric layer 105 can be silicon oxide layer, be manufactured using thermal chemical vapor deposition (thermal CVD) The material layer for having doped or undoped silica that technique or high-density plasma (HDP) manufacturing process are formed, such as not Doped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
In addition, the first dielectric layer 105 can also be the spin cloth of coating-type glass (spin-on- for adulterating boron or adulterating phosphorus Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or adulterate boron tetraethoxysilane (BTEOS), with positive tetrem Silica, high-aspect-ratio technique (the high aspect of base silicon (tetraethyl orthosilicate, TEOS) formation Ratio process, HARP) formed silica or other suitable materials.First dielectric layer 105 can also be by individual layer or more Layer film is formed.
In the present embodiment, silica that the first dielectric layer 105 is formed preferably with Plasma Enhanced Chemical Vapor Deposition (PECVD).
In one example, in the core space, the interlayer dielectric layer between adjacent first bit line 1031 101 and first between dielectric layer 105, are additionally provided with etching stop layer 104.
Etching stop layer 104 may include a dielectric material, such as material, nitrogenous material, carbonaceous material or homologue.
One kind that etching stop layer 104 can be selected in SiCN, SiN, SiC, SiOF, SiON in the present invention, but carve Erosion stop-layer 104 is not limited to above-mentioned example.In the present embodiment, etching stop layer 104 can use SiN layer.
In one example, the second dielectric layer 106 is additionally provided with first dielectric layer 105, wherein, the second dielectric Layer 106 has flat top surface.
Second dielectric layer 106 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process Or the material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, such as without mixing Miscellaneous silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
Second dielectric layer 106 can also be adulterate boron or adulterate phosphorus spin cloth of coating-type glass (spin-on-glass, SOG), adulterate the tetraethoxysilane (PTEOS) of phosphorus or adulterate the tetraethoxysilane (BTEOS) of boron, with positive silicon tetraethyl The silica, high-aspect-ratio technique (high aspect ratio of (tetraethyl orthosilicate, TEOS) formation Process, HARP) formed silica or other suitable materials.Second dielectric layer 106 can also be by single or multiple lift film Form.
So far the introduction of the key structure of the semiconductor devices to the present invention is completed, also includes other for complete device Part, then this does not repeat.
In summary, semiconductor devices of the invention sets air-gap between adjacent bit lines, reduces bit line capacitance, and then The coupled noise between bit line, the also homogeneous unit of availability are reduced, for example, the homogeneous unit of threshold voltage (Vt), random The homogeneous unit of thump telegraph repeater, and improve the RC retardation ratio of bit line so that device has higher performance.
Embodiment two
In view of the superior function of above-mentioned semiconductor device, the present invention also provides a kind of manufacture method of semiconductor devices, such as Shown in Fig. 3, the semiconductor devices mainly includes the following steps that：
Step S301：Substrate is provided, the substrate includes core space and peripheral region, is situated between on the substrate formed with interlayer Electric layer, the hard mask layer of patterning, the hard mask layer bag of the patterning are formed on the interlayer dielectric layer in the core space Some openings are included, the opening corresponds to the pattern of the first bit line in the predetermined core space formed；
Step S302：Form the hard mask layer that bit line material layer covers the patterning, and the core space and described The interlayer dielectric layer of peripheral region exposure；
Step S303：The photoresist layer of patterning is formed on the bit line material layer in the peripheral region；
Step S304：Using the photoresist layer of the patterning as mask, the bit line material layer is etched, is located at institute to be formed The first bit line in core space, and some spaced second bit lines in the peripheral region are stated, wherein, described In core space, the etching stopping is on the top surface of the hard mask layer, and in the peripheral region, the etching stopping is in described On the surface of interlayer dielectric layer, first bit line is parallel with second bit line；
Step S305：Remove the photoresist layer of the hard mask layer and the patterning；
Step S306：The first dielectric layer is formed, to cover first bit line and the institute of second bit line and exposure Interlayer dielectric layer is stated, wherein, formed in first dielectric layer between adjacent first bit line in the core space There is air-gap.
Specifically, the manufacture method of the semiconductor devices in the specific embodiment of the present invention is done with reference to figure 2A to Fig. 2 I It is discussed in detail, wherein, Fig. 2A-Fig. 2 I show a kind of phase of the manufacture method of semiconductor devices in one embodiment of the invention Close the sectional view for the structure that step is formed.
First, as shown in Figure 2 A, there is provided substrate 200, the substrate 200 includes core space and peripheral region, in the substrate Formed with interlayer dielectric layer 201 on 200, hard mask layer 204 is formed on the interlayer dielectric layer 201, in the core space Hard mask layer 204 on form spaced some core patterns 2061.
The substrate 200 includes core space and peripheral region, in Fig. 2A to Fig. 2 I on the left of cut-off rule shown in for core space, point Non- peripheral region shown on the right side of secant, wherein be each formed with including in the peripheral region and the core space floating boom, separation layer, Some gate stacks of control gate.
Wherein, wherein the core space has higher integrated level, gate stack is intensive, wherein the number of the gate stack Mesh is not limited to a certain number range, and the peripheral region has several gate stacks, and gate stack is sparse, for simplification figure In do not show that gate stack.
The substrate 200 includes Semiconductor substrate, and some gate stacks in peripheral region and core space are arranged at semiconductor The top of substrate, to put it more simply, only showing substrate 100 with a blank herein.
The Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI), Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and Germanium on insulator (GeOI) etc..Can also be formed with fleet plough groove isolation structure (not shown) in the Semiconductor substrate.
Exemplarily, it is also formed with depositing tunnel oxide 101, the tunnelling between gate stack and Semiconductor substrate Oxide layer is oxide, in the present invention optional SiO2Layer is used as tunnel oxide, and the thickness of the tunnel oxide can be 1-20nm, but the thickness is not limited solely to, those skilled in the art can be adjusted as needed, to obtain more preferable effect Fruit.
Wherein, the material of floating boom can select semi-conducting material, such as silicon, polysilicon or Ge etc., it is not limited to certain A kind of material selection polysilicon of material, in this embodiment floating boom.
Formed with separation layer on floating boom, wherein the material of the separation layer can select insulating materials commonly used in the art, Such as the one or more in oxide, nitride.
Such as (structure of oxidenitride oxide is exhausted by the material selection ONO of the separation layer in this embodiment Edge separation layer).
Control gate is provided with the separation layer, wherein, the material of the control gate can select semi-conducting material, example Such as silicon, polysilicon or Ge, it is not limited to the material selection polycrystalline of a certain material, the in this embodiment control gate Silicon.
Wherein, it is also formed with source/drain in the Semiconductor substrate of the part of grid pole lamination side in the core space.
Interlayer dielectric layer 201 is provided with the substrate 200, the interlayer dielectric layer 201 further covers the core All gate stacks in heart district and peripheral region.Interlayer dielectric layer can use such as SiO2, fluorocarbon (CF), carbon dope oxygen SiClx (SiOC) or carbonitride of silicium (SiCN) etc..Or it can also use and form SiCN films on fluorocarbon (CF) Film etc..Fluorocarbon is with fluorine (F) and carbon (C) for main component.Fluorocarbon, which can also use, has noncrystal (non-knot Crystalline substance) construction material.Interlayer dielectric layer 201 can also use the Porous such as carbon doped silicon oxide (SiOC) to construct.
In one example, some first conductive plungers are provided with the interlayer dielectric layer 201 of the corresponding core space 2021, each first conductive plunger 2021 electrically connects with corresponding drain electrode or source electrode below, for example, in the core It is spaced apart in area to be electrically connected first conductive plunger 2021 formed with several drain electrodes, then each drain electrode.
In one example, it is conductive formed with some second in the interlayer dielectric layer 201 of the corresponding peripheral region Connector 2022, each second conductive plunger 2022 electrically connect with the gate stack being disposed below.
Wherein, first conductive plunger 2021 and second conductive plunger 2022 can be that those skilled in the art are ripe Any kind of conductive plunger known, it can be the tungsten conductive plunger that material is tungsten (W).
Hard mask layer 204 is formed on the interlayer dielectric layer 201, the material of the hard mask layer can be with this step From oxide, nitride or metal etc., for example, the materials'use α carbon of the hard mask layer 204 in the present embodiment, α carbon Also referred to as amorphous carbon, it can be formed by any suitable method well known to those skilled in the art, such as plasma chemical gas The methods of mutually depositing.
Wherein, the thickness of the hard mask layer is 5~100nm, but is not limited to the scope.
In one example, before the hard mask layer 204 is formed, first formed for the first quarter on the interlayer dielectric layer Lose stop-layer 203.
First etching stop layer 203 may include a dielectric material, such as material, nitrogenous material, carbonaceous material or similar Thing.
One kind that the first etching stop layer 203 can be selected in SiCN, SiN, SiC, SiOF, SiON in the present invention, but It is that the first etching stop layer 203 is not limited to above-mentioned example.In the present embodiment, the first etching stop layer 203 can use SiN layer.It can use and first etching is formed the methods of such as chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition Stop-layer 203.
Then, spaced some core patterns 2061 are formed on the hard mask layer 204 in the core space.
The core pattern 2061 can be formed using any suitable method well known to those skilled in the art, for example, utilizing Self-aligned double patterning case technology (self aligned double patterning, SaDPT).The core pattern 2061 is opened by some Mouth is isolated, and each opening can be of the same size.
Further, the material of core pattern 2061 can be the core figure well known to those skilled in the art that can be used as The material of case, for example, bottom antireflective coating (Bottom Anti Reflective Coating, BARC), or, α carbon etc., In the present embodiment, core pattern 2061 is preferably α carbon.
Forming the method for core pattern 2061 can include：The second etching stop layer is formed on hard mask layer 204 first 205, second etching stop layer 205 can be SiON etc. it is any it is suitable can be as the material of etching stop layer, then the Core pattern material layer is formed on two etching stop layers 205, SiON layers are also optionally formed in core pattern material layer 2062, the core photoresist layer of patterning is formed on SiON layers by photoetching process, the region of core photoresist layer covering is pre- The region of core pattern is shaped as, using the core photoresist layer of patterning as mask, is sequentially etched SiON layers 2062 and core pattern Material layer, until the second etching stop layer 205 of exposure, to form some core patterns 2061 isolated by opening, finally, remove The core photoresist layer of patterning.
Then, as shown in Figure 2 B, clearance wall 207 is formed in the side wall of each core pattern 2061.
The material of the clearance wall 207 can be oxide, nitride, oxynitride or its combination.
Specifically, first conformal deposited, which forms spacer material layer, can use any deposition side well known to those skilled in the art Method is formed, including but not limited to chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method.In the present embodiment, compared with Goodly, deposit to form spacer material layer using atomic layer deposition method.
Afterwards, the spacer material layer is etched, to form the gap in each side wall of core pattern 2061 Wall 207.
The spacer material layer is etched from dry etching, in the present invention using CxFyDry method as etching agent Plasma etch process realizes the etching to the spacer material layer 205a, the CxFyEtching agent can be CF4、CHF3、 C4F8And C5F8In one or more.In the embodiment of the present invention, the dry etching can select CF4、 CHF3, in addition plus N2、CO2In it is a kind of as etching atmosphere, wherein gas flow is CF410-200sccm, CHF310- 200sccm, N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, etch period 5-120s, preferably For 5-60s, more preferably 5-30s.
Due to the presence of the difference in height of the top and bottom of height core pattern, therefore the etching in the step is mainly for position In the portion gap wall material bed of material on the top of core pattern and the surface of SiON layers 2062, the side of core pattern 2061 is only located to be formed Clearance wall 207 on wall.
Wherein, in this step, the SiON layers 2062 in the core pattern 2061 are also etched removal.
Then, as shown in Figure 2 C, the core pattern is removed.
Suitable method can be selected to remove the core pattern according to the material of core pattern, for example, can use wet etching or Person's dry etching.
In one example, when the material of core pattern is α carbon, plasma etching processing procedure can be used to remove α carbon, can The etching gas used include oxygen and diluent gas, and diluent gas can be argon gas.Or can also use hydrogeneous grade from Daughter, the method for ashing can also be used to remove α carbon.
Then, as shown in Figure 2 D, the layer is stopped at for hard mask layer 204 described in mask etching with the clearance wall 207 Between form some openings on dielectric layer 201, and the clearance wall is removed, to form the hard mask layer 204 of the patterning.
Wherein, the first bit line in the corresponding predetermined core space formed of opening in the hard mask layer 204 of the patterning Group, which define position and the pattern dimension of the first bit line.
In one example, it is that mask is sequentially etched the second etching stop layer 205, described covered firmly with the clearance wall 207 The etching stop layer 203 of film layer 204 and first, stops on the interlayer dielectric layer 201 and forms some openings, and remove institute Clearance wall is stated, to form the hard mask layer 204 of the patterning.
Dry etching or wet etching can be used to carry out the etching in this step, dry etch process includes but unlimited In：Reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting.Carved for example with plasma Erosion, etching gas can use and be based on oxygen (O2- based) gas.
Then, as shown in Figure 2 E, the hard mask layer 204 that bit line material layer 208 covers the patterning is formed, and it is described Core space and the interlayer dielectric layer 201 of peripheral region exposure.
Specifically, the material of the bit line material layer 208 can use it is well known to those skilled in the art it is any have lead Electrical material, such as metal material, metal material can include but is not limited to the one or more in Cu, Al, W, Ag, this reality Apply in example, preferably the materials'use tungsten (W) of bit line material layer 208.
The depositing operations such as vapour deposition method, sputtering method, chemical vapour deposition technique, physical vaporous deposition can be used to form the position The wire rod bed of material 208, wherein, in the present embodiment, deposit to form bit line material layer 208 preferably with sputtering method.
Then, as shown in Figure 2 F, the photoresist layer 209 of patterning is formed on the bit line material layer 208 in peripheral region, should The photoresist layer 209 of patterning defines position and the pattern dimension of the second bit line.The photoresist layer 209 of the patterning exposes core Bit line material floor 208 in area, and the part being entirely covered in peripheral region is the position of predetermined the second bit line formed.
Then, as shown in Figure 2 G, it is mask with the photoresist layer 209 of the patterning, etches the bit line material layer 208, to form the first bit line 2081 in the core space, and it is some spaced in the peripheral region Second bit line 2082, wherein, in the core space, the etching stopping is on the top surface of the hard mask layer 204, described In peripheral region, the etching stopping is on the surface of the interlayer dielectric layer 201, first bit line 2081 and the second Line 2082 is parallel.
Exemplarily, first bit line 2081 is parallel with second bit line 2082 in the table of interlayer dielectric layer 208 Extended in one direction on face.
Wherein, first bit line 2,081 first conductive plunger 2021 corresponding with being disposed below in part is electrically connected Connect, to realize the first bit line 2081 and the drain electrode of device or the electrical connection of source electrode.
Further, in two first bit lines 1031 electrically connected respectively with adjacent first conductive plunger 1021 Between, it is additionally provided with some first bit lines 1031 not being connected with any first conductive plunger electricity 1021.
In one example, it is conductive slotting to be electrically connected described second be disposed below for each second bit line 2082 Plug 2022.
Exemplarily, dry etch process can be used, in the case where being passed through the etching condition of boron chloride and chlorine, to bit line material Layer performs etching, and reaction room pressure can be 5~20 millitorrs (mTorr)；Power：300-800W；Time：5-15s；The chlorination The range of flow of boron and chlorine can be 0~150 cc/min (sccm) and 50~200 cc/mins (sccm). It should be noted that what above-mentioned lithographic method was merely exemplary, it is not limited to which this method, those skilled in the art can be with From other conventional methods.
Afterwards, the photoresist layer of the hard mask layer and the patterning is removed.
Exemplarily, can be by the method for ashing by hard mask layer and photoresist layer one when the hard mask layer is α carbon And remove.
Plasma etching processing procedure can also be used to remove α carbon and photoresist layer, workable etching gas include oxygen And diluent gas, diluent gas can be argon gas.Or hydrogeneous plasma can also be used.
Then, as illustrated in figure 2h, the first dielectric layer 210 is formed, to cover first bit line 2081 and the second Line 2082 and the interlayer dielectric layer 201 of exposure, wherein, adjacent first bit line 2081 in the core space it Between first dielectric layer 210 in formed with air-gap 211.
Be not in sky between the second bit line therefore because the spacing distance between adjacent second bit line 2082 is big Air gap.
First dielectric layer 210 can be silicon oxide layer, be manufactured using thermal chemical vapor deposition (thermal CVD) The material layer for having doped or undoped silica that technique or high-density plasma (HDP) manufacturing process are formed, such as not Doped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
In addition, the first dielectric layer 210 can also be the spin cloth of coating-type glass (spin-on- for adulterating boron or adulterating phosphorus Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or adulterate boron tetraethoxysilane (BTEOS), with positive tetrem Silica, high-aspect-ratio technique (the high aspect of base silicon (tetraethyl orthosilicate, TEOS) formation Ratio process, HARP) formed silica or other suitable materials.First dielectric layer 210 can also be by individual layer or more Layer film is formed.
In the present embodiment, silica that the first dielectric layer 210 is formed preferably with Plasma Enhanced Chemical Vapor Deposition (PECVD).
Then, as shown in figure 2i, the second dielectric layer 211 is formed on first dielectric layer 210, wherein, the second dielectric Layer 211 has flat top surface.
Second dielectric layer 211 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process Or the material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, such as without mixing Miscellaneous silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
Second dielectric layer 211 can also be adulterate boron or adulterate phosphorus spin cloth of coating-type glass (spin-on-glass, SOG), adulterate the tetraethoxysilane (PTEOS) of phosphorus or adulterate the tetraethoxysilane (BTEOS) of boron, with positive silicon tetraethyl The silica, high-aspect-ratio technique (high aspect ratio of (tetraethyl orthosilicate, TEOS) formation Process, HARP) formed silica or other suitable materials.Second dielectric layer 211 can also be by single or multiple lift film Form.
After deposition forms the second dielectric layer can also cmp be carried out to its surface, it is more smooth to obtain Surface.
So far, the introduction of the committed step of the manufacture method of the semiconductor devices to the present invention is completed, for complete Device fabrication it may also be desirable to other prior steps, intermediate steps or subsequent step, then this is not being repeated.
In summary, manufacturing method according to the invention, air-gap is formed between bit line, reduces bit line capacitance, entered And the coupled noise between bit line is reduced, the homogeneous unit of performance is have also obtained, for example, the homogeneous unit of threshold voltage (Vt), The homogeneous unit of Random telegraph noise (Random telegraphic noise, abbreviation RTN), and the RC for improving bit line prolongs Late, the performance of semiconductor devices is finally improved.
Embodiment three
Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment one, the semiconductor device Part is prepared according to the methods described of embodiment two.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV Any electronic product such as machine, VCD, DVD, navigator, DPF, camera, video camera, recording pen, MP3, MP4, PSP is set It is standby, or any intermediate products including circuit.The electronic installation of the embodiment of the present invention, due to having used above-mentioned circuit, Thus there is better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401 Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment one, and the semiconductor devices includes： Substrate, the substrate include core space, are provided with interlayer dielectric layer on the substrate；The interlayer in the core space Spaced some first bit lines on dielectric layer, wherein, first bit line extends in a first direction；First dielectric layer is set The interlayer dielectric layer in first bit line and the core space is covered, wherein, the adjacent institute in the core space State in first dielectric layer between the first bit line formed with air-gap.
In the present invention by forming air-gap between bit line, bit line capacitance is reduced, and then is reduced between bit line Coupled noise, the homogeneous unit of performance is have also obtained, for example, the homogeneous unit of threshold voltage (Vt), Random telegraph noise (Random telegraphic noise, abbreviation RTN) homogeneous unit, and the RC retardation ratio of bit line is improved, finally improve The performance of semiconductor devices, and then the electronic installation including the semiconductor devices also has higher performance accordingly.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (22)

  1. A kind of 1. semiconductor devices, it is characterised in that including：
    Substrate, the substrate include core space, are provided with interlayer dielectric layer on the substrate；
    Spaced some first bit lines on the interlayer dielectric layer in the core space；
    The first dielectric layer of the interlayer dielectric layer in first bit line and the core space is covered, wherein, described Formed with air-gap in first dielectric layer between adjacent first bit line in core space.
  2. 2. semiconductor devices as claimed in claim 1, it is characterised in that set in the interlayer dielectric layer of the corresponding core space Some first conductive plungers are equipped with, each first conductive plunger electrically connects with drain electrode below or source electrode, wherein, part First bit line the first conductive plunger electrical connection corresponding with being disposed below.
  3. 3. semiconductor devices as claimed in claim 1, it is characterised in that the substrate also includes peripheral region, around described Some gate stacks for including floating boom, separation layer, control gate are each formed with area and the core space, the interlayer dielectric layer covers Cover some gate stacks.
  4. 4. semiconductor devices as claimed in claim 3, it is characterised in that the interlayer dielectric layer in the corresponding peripheral region In formed with some second conductive plungers, each second conductive plunger electrically connects with the gate stack being disposed below.
  5. 5. semiconductor devices as claimed in claim 4, it is characterised in that set on the interlayer dielectric layer of the peripheral region Second bit line at some intervals is equipped with, second bit line is parallel with first bit line, and each second bit line difference Electrically connect second conductive plunger being disposed below.
  6. 6. semiconductor devices as claimed in claim 5, it is characterised in that first dielectric layer also covers second bit line And the part interlayer dielectric layer in the peripheral region.
  7. 7. semiconductor devices as claimed in claim 1, it is characterised in that be additionally provided with second Jie on first dielectric layer Electric layer.
  8. 8. semiconductor devices as claimed in claim 5, it is characterised in that the spacing distance between adjacent first bit line is small Spacing distance between adjacent second bit line.
  9. 9. semiconductor devices as claimed in claim 5, it is characterised in that the material of first bit line and second bit line For tungsten.
  10. 10. semiconductor devices as claimed in claim 2, it is characterised in that respectively with adjacent first conductive plunger Electrical connection two first bit lines between, be additionally provided with it is some do not electrically connected with first conductive plunger described first Bit line.
  11. A kind of 11. manufacture method of semiconductor devices, it is characterised in that including：
    Substrate is provided, the substrate includes core space and peripheral region, on the substrate formed with interlayer dielectric layer, in the core The hard mask layer of patterning is formed on interlayer dielectric layer in heart district, the hard mask layer of the patterning includes some openings, institute State the pattern of the first bit line in the corresponding predetermined core space formed of opening；
    Form the hard mask layer that bit line material layer covers the patterning, and exposure in the core space and the peripheral region Interlayer dielectric layer；
    The photoresist layer of patterning is formed on the bit line material layer in the peripheral region；
    Using the photoresist layer of the patterning as mask, the bit line material layer is etched, to be formed in the core space First bit line, and some spaced second bit lines in the peripheral region, wherein, in the core space, institute Etching stopping is stated on the top surface of the hard mask layer, in the peripheral region, the etching stopping is in the interlayer dielectric layer Surface on, first bit line is parallel with second bit line；
    Remove the photoresist layer of the hard mask layer and the patterning；
    The first dielectric layer is formed, to cover first bit line and second bit line and the interlayer dielectric layer of exposure, Wherein, formed with air-gap in first dielectric layer between adjacent first bit line in the core space.
  12. 12. manufacture method as claimed in claim 11, it is characterised in that the method for forming the hard mask layer of the patterning, Comprise the following steps：
    Hard mask layer is formed on the interlayer dielectric layer, if being formed on the hard mask layer in the core space spaced Dry core pattern；
    Clearance wall is formed in the side wall of each core pattern；
    Remove the core pattern；
    Using the clearance wall as hard mask layer described in mask etching, stop on the interlayer dielectric layer and form some described open Mouthful, and the clearance wall is removed, to form the hard mask layer of the patterning.
  13. 13. the manufacture method as described in claim 11 or 12, it is characterised in that before the hard mask layer is formed, also wrap Include form the first etching stop layer on the interlayer dielectric layer the step of.
  14. 14. the manufacture method as described in claim 11 or 12, it is characterised in that also include before the core pattern is formed Form the second etching stop layer on the hard mask layer the step of.
  15. 15. manufacture method as claimed in claim 11, it is characterised in that be respectively formed in the peripheral region and the core space Have including floating boom, separation layer, control gate some gate stacks, the interlayer dielectric layer covers some gate stacks.
  16. 16. manufacture method as claimed in claim 11, it is characterised in that set in the interlayer dielectric layer of the corresponding core space Some first conductive plungers are equipped with, each first conductive plunger electrically connects with drain electrode below or source electrode, wherein, part First bit line the first conductive plunger electrical connection corresponding with being disposed below.
  17. 17. manufacture method as claimed in claim 15, it is characterised in that the interlayer dielectric layer in the corresponding peripheral region In formed with some second conductive plungers, each second conductive plunger electrically connects with the gate stack being disposed below, and Each second bit line is electrically connected second conductive plunger being disposed below.
  18. 18. manufacture method as claimed in claim 11, it is characterised in that the material of the hard mask layer includes α carbon.
  19. 19. manufacture method as claimed in claim 11, it is characterised in that the bit line material layer includes tungsten.
  20. 20. manufacture method as claimed in claim 11, it is characterised in that form the bit line material layer using sputtering method.
  21. 21. manufacture method as claimed in claim 11, it is characterised in that after first dielectric layer is formed, in addition to The step of forming the second dielectric layer is being deposited on first dielectric layer.
  22. 22. a kind of electronic installation, it is characterised in that including the semiconductor devices as described in any one of claim 1 to 10.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582335A (en) * 2019-09-29 2021-03-30 芯恩（青岛）集成电路有限公司 Semiconductor device and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291030B1 (en) * 1999-12-21 2001-09-18 Promos Technologies, Inc. Method for reducing capacitance in metal lines using air gaps
US6303464B1 (en) * 1996-12-30 2001-10-16 Intel Corporation Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer
CN101901810A (en) * 2009-05-26 2010-12-01 旺宏电子股份有限公司 Memory device and methods for fabricating and operating the same
US20120070944A1 (en) * 2010-09-17 2012-03-22 Hyu-Jung Kim Methods of Manufacturing Three Dimensional Semiconductor Devices
CN103456606A (en) * 2012-06-04 2013-12-18 中芯国际集成电路制造(上海)有限公司 Method for forming hard mask layer
CN103681677A (en) * 2012-09-06 2014-03-26 三星电子株式会社 Semiconductor device and method of manufacturing the same
CN103871964A (en) * 2014-03-11 2014-06-18 上海华虹宏力半导体制造有限公司 Interconnecting wire structure and forming method thereof
US20160064237A1 (en) * 2014-08-29 2016-03-03 Macronix International Co., Ltd. Method of forming semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303464B1 (en) * 1996-12-30 2001-10-16 Intel Corporation Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer
US6291030B1 (en) * 1999-12-21 2001-09-18 Promos Technologies, Inc. Method for reducing capacitance in metal lines using air gaps
CN101901810A (en) * 2009-05-26 2010-12-01 旺宏电子股份有限公司 Memory device and methods for fabricating and operating the same
US20120070944A1 (en) * 2010-09-17 2012-03-22 Hyu-Jung Kim Methods of Manufacturing Three Dimensional Semiconductor Devices
CN103456606A (en) * 2012-06-04 2013-12-18 中芯国际集成电路制造(上海)有限公司 Method for forming hard mask layer
CN103681677A (en) * 2012-09-06 2014-03-26 三星电子株式会社 Semiconductor device and method of manufacturing the same
CN103871964A (en) * 2014-03-11 2014-06-18 上海华虹宏力半导体制造有限公司 Interconnecting wire structure and forming method thereof
US20160064237A1 (en) * 2014-08-29 2016-03-03 Macronix International Co., Ltd. Method of forming semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582335A (en) * 2019-09-29 2021-03-30 芯恩（青岛）集成电路有限公司 Semiconductor device and preparation method thereof
CN112582335B (en) * 2019-09-29 2023-08-11 芯恩（青岛）集成电路有限公司 Semiconductor device and preparation method thereof

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