CN112582335B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN112582335B CN112582335B CN201910931434.6A CN201910931434A CN112582335B CN 112582335 B CN112582335 B CN 112582335B CN 201910931434 A CN201910931434 A CN 201910931434A CN 112582335 B CN112582335 B CN 112582335B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: providing a substrate, and forming a first dielectric layer on the substrate; etching the first dielectric layer, and forming an inclined groove with a preset included angle with the surface of the substrate in the first dielectric layer; a second dielectric layer is rapidly deposited at the openings of the first dielectric layer and the trench to form an air gap inside the trench. Because the air gap is formed in the groove, the duty ratio of the air medium is increased, namely the duty ratio of the low-k medium is increased, the RC delay of the semiconductor device can be greatly reduced, the electric signal transmission rate of the semiconductor device is improved, the power consumption of the system is reduced, the service environment of the semiconductor device is improved, and the service life of the semiconductor device is prolonged. The formation mode of the air gap is simpler and more effective than the traditional process steps.
Description
Technical Field
The invention relates to the technical field of integrated circuit preparation, in particular to a semiconductor device and a preparation method thereof.
Background
With the development of semiconductor technology, various types of problems or challenges continue to occur in the fabrication process of semiconductor devices. Particularly, as the size of semiconductor devices is continuously reduced, one of the most remarkable problems that occurs is that the capacitance between metal wires, the interlayer capacitance, and the resistance of the metal wires are increased, resulting in an increase in the metal wiring RC (resistance-capacitance) delay. Particularly for sensors, power devices and the like, the RC delay is increased, so that the working efficiency of the devices is reduced, the power consumption of the system is increased, the service life of the devices is greatly reduced, and even certain potential safety hazards are caused when the system is in a working environment with high load and high temperature for a long time.
The most common method for reducing the RC delay of the metal wiring is to select a dielectric with low dielectric constant k as the insulating layer of the metal interconnection layer. In order to obtain a dielectric constant k as low as possible, this is usually achieved by increasing the porosity, but such a method is theoretically still unable to achieve a level of dielectric constant k=1.0 for air. The formation of air gaps in the interconnect layer is a desirable choice for semiconductor devices such as CMOS devices. The existing method for forming the air gap is complex in process, more in raw material consumption, longer in process time and lower in production efficiency.
Disclosure of Invention
In view of the above-mentioned drawbacks and shortcomings of the prior art methods of forming air gaps, the present invention provides a semiconductor device and a method of fabricating the same, in which a first dielectric layer is etched to form an inclined trench by inclined plasma flow or inclined substrate, and a second dielectric layer is formed at the openings of the first dielectric layer and the trench to form an inclined air gap. The method has the advantages of simple process, less raw material loss and high production efficiency.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, and forming a first dielectric layer on the substrate;
etching the first dielectric layer, and forming an inclined groove with a preset included angle with the surface of the substrate in the first dielectric layer;
a second dielectric layer is formed by rapid deposition at the first dielectric layer and at the opening of the trench to form an air gap inside the trench.
Optionally, before forming the first dielectric layer on the substrate, forming an etching stop layer on the substrate, and stopping the etching stop layer when etching the first dielectric layer.
Optionally, before etching the first dielectric layer, a step of forming a metal interconnection layer in the first dielectric layer is further included.
Optionally, the first dielectric layer is etched by:
etching the first dielectric layer by adopting an inclined plasma flow, wherein a second preset included angle is formed between the inclined plasma flow and the surface of the substrate; or alternatively
Tilting the substrate, etching the first dielectric layer by adopting vertical plasma flow, wherein the second preset included angle is formed between the substrate and the horizontal plane.
Alternatively, the oblique plasma flow may be obtained by:
generating a tilted plasma stream having said second predetermined angle with the substrate surface using a tilted plasma stream generating device; or alternatively
And applying an external electric field in the horizontal direction to the plasma generating device by adopting the vertical plasma flow generating device, so that the plasma flow generated by the plasma generating device deflects, and the deflected inclined plasma flow has the second preset included angle with the surface of the substrate.
Optionally, the voltage of the applied electric field applied in the plasma generating device is between 0.3V and 1000V.
Optionally, the second predetermined angle is between 0 ° and 90 °.
Optionally, the predetermined angle between the trench and the horizontal surface of the substrate is between 10 ° and 90 °.
Optionally, the depth of the groove extending in the vertical direction is betweenWith a horizontal width between The length extending in the horizontal direction is between +.>The width of the groove is between
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a substrate comprising a first dielectric layer;
forming an inclined trench in the first dielectric layer having a predetermined angle with the surface of the substrate;
a second dielectric layer formed over the first dielectric layer and at an opening of the trench;
wherein the second dielectric layer and the trench form an air gap.
Optionally, a metal interconnection layer is further formed in the first dielectric layer.
Optionally, an etch stop layer is also provided between the substrate and the first dielectric layer.
Optionally, the predetermined angle between the trench and the surface of the substrate is between 10 ° and 90 °.
Optionally, the depth of the groove extending in the vertical direction is betweenThe length extending in the horizontal direction is between +.>The width of the groove is between->
As described above, the semiconductor device and the method of manufacturing the same of the present invention have the following technical effects:
according to the preparation method, the first dielectric layer formed on the substrate is directly etched, the inclined groove is formed in the first dielectric layer, and then the second dielectric layer is rapidly deposited on the upper portion of the first dielectric layer and the opening of the inclined groove, so that the inclined groove is sealed, and an inclined air gap is formed. The angled trenches may be formed by etching the first dielectric layer with an angled plasma flow or by etching the first dielectric layer with an angled substrate with a plasma flow. The process has the advantages of simple process, less raw material loss, preparation cost saving and production efficiency improvement.
According to the preparation method, an inclined air gap is formed in the groove, so that the duty ratio of an air medium is increased, namely, the duty ratio of a low-k medium is increased, RC delay of the semiconductor device can be greatly reduced, the electric signal transmission rate of the semiconductor device is improved, the power consumption of a system is reduced, the service environment of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.
According to the method, the second dielectric layer is rapidly deposited above the first dielectric layer and at the opening of the inclined groove to form the air gap, and the groove is inclined, so that when the groove is sealed by depositing the second dielectric layer to form the air gap, the integrity of the seal can be improved, and the structural integrity and the functional reliability of the air gap are ensured.
The semiconductor device provided by the invention is prepared by the method, has the inclined air gap, and therefore has lower RC delay and better performance.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:
fig. 1 is a flowchart of a semiconductor manufacturing method according to an embodiment of the invention.
Fig. 2 is a schematic view showing the structure of the substrate provided in fig. 1.
Fig. 3 is a schematic diagram of the structure of fig. 1 in which a mask layer is formed over the first dielectric layer shown in fig. 2.
Fig. 4 is a schematic diagram showing a structure of etching the mask layer shown in fig. 3 to form a patterned mask layer.
Fig. 5 is a schematic diagram of a structure of etching a first dielectric layer to form a trench.
FIG. 6 is a schematic diagram showing a structure of depositing a second dielectric layer at the trench opening and over the first dielectric layer.
Fig. 7 is a schematic diagram of a structure for planarizing the second dielectric layer shown in fig. 6.
Fig. 8 shows a schematic structure of a plasma etching apparatus for generating an oblique plasma flow used in the method of the first embodiment.
Fig. 9 shows a schematic structure of a plasma etching apparatus generating an oblique plasma flow used in the semiconductor manufacturing method provided in the second embodiment.
Fig. 10 shows a schematic structure of a plasma etching apparatus generating an oblique plasma flow used in the semiconductor manufacturing method provided in the third embodiment.
Reference numerals
100. Substrate and method for manufacturing the same
101. A first dielectric layer
102. Etching stop layer
103. Mask layer
103' patterned mask layer
104. Groove(s)
105. Second dielectric layer
105' planarized second dielectric layer
200. Plasma etching apparatus
201. Sample stage
202-1 plasma generation chamber
202-2 plasma etch chamber
203. Inclined plasma jet
204. Bias power supply
300. Plasma etching apparatus
301. Sample stage
302-1 plasma generation chamber
302-2 plasma etch chamber
303. Perpendicular plasma jet
303' inclined plasma jet
304. Offset generator
305. External electric field
400. Plasma etching apparatus
401. Sample stage
402-1 plasma generation chamber
402-2 plasma etch chamber
403. Perpendicular plasma jet
404. Offset generator
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
In the following embodiments of the present invention, terms indicating orientations, such as "upper", "lower", "left", "right", "horizontal", "vertical", etc., are merely used to facilitate a better understanding of the present invention by those skilled in the art and are not to be construed as limiting the present invention.
Example 1
The embodiment provides a method for manufacturing a semiconductor device, as shown in fig. 1, the method includes the following steps:
providing a substrate, and forming a first dielectric layer on the substrate;
etching the first dielectric layer, and forming an inclined groove with a preset included angle with the substrate in the first dielectric layer;
a second dielectric layer is formed by rapid deposition at the first dielectric layer and at the opening of the trench to form an air gap inside the trench.
The above-described semiconductor manufacturing method will now be described in detail with reference to fig. 2 to 8.
First, as shown in fig. 2, a substrate 100 is provided, a first dielectric layer 101 is formed on the substrate 100, then the first dielectric layer 101 is etched, an inclined trench 104 is formed in the first dielectric layer 101 as shown in fig. 5, then a second dielectric layer 105 is deposited at the opening of the inclined trench 104 and above the first dielectric layer 101, the trench 104 is sealed, and an inclined air gap 104' is formed inside the trench 104. The grooves 104 (air gaps 104') have a predetermined angle α with the surface of the substrate 100, which in the preferred embodiment is between 10 ° and 90 °. In the preferred embodiment of the present embodiment, the depth L1 of the trench 104 extending in the vertical direction is betweenThe length L2 extending in the horizontal direction is between +.>The width W of the trench 104 is between +.>The inclined air gap 104' increases the duty ratio of the air medium, namely, the duty ratio of the low-k medium, so that the RC delay of the semiconductor device can be greatly reduced, the electric signal transmission rate of the semiconductor device is improved, the power consumption of the system is reduced, the service environment of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.
In this embodiment, the trench 104 may have a regular shape with uniform width from the opening to the bottom, or may have an irregular shape with non-uniform width from the opening to the inner width, such as a trapezoid, a cone, or the like.
In a preferred embodiment of the present embodiment, the substrate 100 may be a semiconductor substrate commonly used in the art, such as silicon, silicon-on-insulator, germanium, or silicon germanium, etc. The first dielectric layer 101 may be SiO 2 、Si 3 N 4 And amorphous silicon materials. As shown in fig. 1, an etch stop layer 102 is preferably formed on the substrate 100 before the first dielectric layer 101 is formed to control the etching depth of the first dielectric layer 101 at a later stage. More preferably, a metal interconnection layer (not shown) is formed in the first dielectric layer 101, and the metal interconnection layer may be formed by a well-known damascene process.
In forming the air gap 104' shown in fig. 5, first, as shown in fig. 3, a mask layer 103, which may be, for example, a photoresist or the like, is formed over the first dielectric layer 101. Then, as shown in fig. 4, the mask layer 103 is subjected to photolithography to form an patterned mask layer 103 'having an opening pattern forming a trench, and then the first dielectric layer is etched with the patterned mask layer 103' until the etching stop layer 102 is stopped, thereby forming an inclined trench 104.
In a preferred embodiment of the present embodiment, the first dielectric layer 101 is etched using a tilted plasma flow. As shown in fig. 8, the substrate 100 having the structure shown in fig. 4 is etched using the plasma etching apparatus 200 having the inclined plasma generating chamber 202-1 in the present embodiment. The inclined plasma-generating chamber 202-1 is capable of generating and reflecting a plasma flow 203 having an angle beta with respect to the horizontal plane, said plasma flow 103 having an angle beta with respect to the horizontal plane of between 10 and 90 in order to obtain an air gap 104' between the substrates 100 having the above-mentioned predetermined angle alpha.
As shown in fig. 8, the plasma etching apparatus 200 further includes an etching chamber 202-2, the etching chamber 202-2 including a sample stage 201 disposed at a bottom thereof, the sample stage 201 being coupled to a bias power supply 204. The bias power supply 204 is typically a power supply of up to about 500W, and has a frequency of about 13.56MHz, and is capable of generating continuous or pulsed power. Alternatively, the bias power supply 204 may be a DC power supply or a pulsed DC power supply. The substrate 100 with patterned mask layer 103 'is placed on the sample stage 201 and then the plasma etching apparatus is started to generate the above-mentioned inclined plasma flow 203, and the first dielectric layer 101 on the substrate 100 is etched under the action of the patterned mask layer 103' until the etching stop layer 102 stops, forming the inclined trench 104 shown in fig. 5.
Thereafter, the patterned masking layer 103' is removed and the sloped trench 104 is then capped, for example, in a preferred embodiment of the present invention, by rapidly depositing a second dielectric layer 105 at the opening of the trench 104 and over the first dielectric layer 101 using CVD (chemical vapor deposition), PVD (physical vapor deposition) or spin-on deposition (spin-on) to obtain the structure illustrated in fig. 6. The deposited second dielectric layer 105 is then planarized, as shown in fig. 7, for example by CMP (chemical mechanical planarization) to obtain a second dielectric layer 105' of desired thickness. Because the trench 104 is sloped, the integrity of the seal can be improved when the second dielectric layer is deposited to seal the trench to form an air gap, thereby ensuring structural integrity and functional reliability of the air gap.
Example two
The embodiment also provides a method for manufacturing a semiconductor device, which is the same as that of the first embodiment, and is different from that of the first embodiment in that:
as shown in fig. 9, in this embodiment, the first dielectric layer 101 is etched using an inclined plasma flow as well. The difference from the first embodiment is that the plasma generation chamber 302-1 of the plasma etching apparatus 300 of the present embodiment is a vertical chamber that generates a vertical plasma flow 303. To obtain an angled plasma flow 303', a horizontally applied electric field 305 is applied in the plasma etching chamber 302-2 of the plasma etching apparatus, which applied electric field 305 deflects the vertical plasma flow 303, forming an angled plasma flow 303'. The voltage intensity of the applied electric field 305 is 3V-1000V, and the included angle gamma between the inclined plasma flow 303' and the horizontal direction is 10-90 deg. Sample stage 301 of plasma etching apparatus 300 is also coupled to bias power supply 304. The bias power supply 304 is typically a power supply of up to about 500W, and has a frequency of about 13.56MHz, and is capable of generating continuous or pulsed power. Alternatively, the bias power supply 304 may be a DC power supply or a pulsed DC power supply. The horizontally placed substrate 101 is etched using the angled plasma flow 303 'to obtain the angled trenches 104 shown in fig. 5, further resulting in an angled air gap 104'.
Example III
The present embodiment also provides a method for manufacturing a semiconductor device, which is the same as that of the first and second embodiments, and is different from that of the first and second embodiments in that:
as shown in fig. 10, in this embodiment, the first dielectric layer 101 is etched using a vertical plasma flow as well. As in the embodiment, the plasma generation chamber 402-1 of the plasma etching apparatus 400 of the present embodiment is a vertical chamber that generates a vertical plasma flow 403. Sample stage 401 of plasma etching apparatus 400 is also coupled to bias power supply 404. The bias power supply 404 is typically a power supply of up to about 500W, and has a frequency of about 13.56MHz, and is capable of generating continuous or pulsed power. Alternatively, the bias power supply 404 may be a DC power supply or a pulsed DC power supply. The difference is that in the present embodiment, the sample stage 401 of the plasma etching apparatus 400 is inclined at an angle with respect to the horizontal directionTo obtain the angle alpha with the substrate surface shown in figure 6An inclined air gap 104', in this embodiment, the sample stage 401 is inclined at an angle +.>Between 10 and 90 degrees.
Example IV
The present embodiment provides a semiconductor device, referring also to fig. 7, including:
a substrate 100, said substrate 100 comprising a first dielectric layer 101;
an inclined trench 104 formed in the first dielectric layer 101 at a predetermined angle α to the substrate;
a second dielectric layer 105 'formed over the first dielectric layer 101 and at the opening of the trench 104, wherein the second dielectric layer and the trench form an air gap 104'.
In a preferred embodiment of the present embodiment, the substrate 100 may be a semiconductor substrate commonly used in the art, such as silicon, silicon-on-insulator, germanium, or silicon germanium, etc. The first dielectric layer 101 may be SiO 2 、Si 3 N 4 And amorphous silicon materials. As shown in fig. 1, an etch stop layer 102 is preferably formed on the substrate 100 before the first dielectric layer 101 is formed to control the etching depth of the first dielectric layer 101 at a later stage.
Although not shown, a metal interconnection layer is also formed in the first dielectric layer 101, as is well known to those skilled in the art. Preferably, the metal interconnection layer may be formed by a well-known damascene process.
An etch stop layer 102 is also provided between the substrate 100 and the first dielectric layer 101, so that the formation of an air gap 104' in etching the first dielectric layer 101 is a control of the depth of the etch.
In a preferred embodiment of this embodiment, the predetermined angle α between the trench 104 and the substrate surface is between 10 ° and 90 °. The grooves 104 having the predetermined included angle, i.e., the air gaps 104', may be formed by the method of embodiments one to three, for example.
In another embodiment of the present inventionIn a preferred embodiment, the trenches 104 extend to a depth in the vertical direction that is between The length extending in the horizontal direction is between +.>The width of the groove is betweenThe angled air gap 104' thus formed in the trench 104 increases the air dielectric duty cycle, i.e., increases the low-k dielectric duty cycle, thereby greatly reducing the RC delay of the semiconductor device, making the performance of the semiconductor device more advantageous.
In summary, the semiconductor device and the preparation method thereof have the following technical effects:
according to the preparation method, the first dielectric layer formed on the substrate is directly etched, the inclined groove is formed in the first dielectric layer, and then the second dielectric layer is rapidly deposited on the upper portion of the first dielectric layer and the opening of the inclined groove, so that the inclined groove is sealed, and an inclined air gap is formed. The angled trenches may be formed by etching the first dielectric layer with an angled plasma flow or by etching the first dielectric layer with an angled substrate with a plasma flow. The process has the advantages of simple process, less raw material loss, preparation cost saving and production efficiency improvement.
According to the preparation method, an inclined air gap is formed in the groove, so that the duty ratio of an air medium is increased, namely, the duty ratio of a low-k medium is increased, RC delay of the semiconductor device can be greatly reduced, the electric signal transmission rate of the semiconductor device is improved, the power consumption of a system is reduced, the service environment of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.
According to the method, the second dielectric layer is rapidly deposited above the first dielectric layer and at the opening of the inclined groove to form the air gap, and the groove is inclined, so that when the groove is sealed by depositing the second dielectric layer to form the air gap, the integrity of the seal can be improved, and the structural integrity and the functional reliability of the air gap are ensured.
The semiconductor device provided by the invention is prepared by the method, has the inclined air gap, and therefore has lower RC delay and better performance.
The above-described embodiments illustrate only the principle of the invention and its efficacy, but are not intended to limit the invention, as various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (12)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, and forming a first dielectric layer on the substrate;
etching the first dielectric layer, and forming an inclined groove with a preset included angle with the surface of the substrate in the first dielectric layer, wherein the groove is in a regular shape with uniform width from the opening to the bottom, and the preset included angle between the groove and the surface of the substrate is 10-90 degrees;
a second dielectric layer is formed by rapid deposition at the first dielectric layer and at the opening of the trench to form an air gap inside the trench.
2. The method of claim 1, further comprising forming an etch stop layer on the substrate prior to forming a first dielectric layer on the substrate, the etch stop layer stopping upon etching the first dielectric layer.
3. The method of claim 1, further comprising the step of forming a metal interconnect layer in the first dielectric layer prior to etching the first dielectric layer.
4. The method of manufacturing according to claim 1, wherein the first dielectric layer is etched by:
etching the first dielectric layer by adopting an inclined plasma flow, wherein a second preset included angle is formed between the inclined plasma flow and the surface of the substrate; or alternatively
Tilting the substrate, etching the first dielectric layer by adopting vertical plasma flow, wherein a second preset included angle is formed between the substrate and the horizontal plane.
5. The method of claim 4, wherein the oblique plasma flow is obtainable by:
generating a tilted plasma stream having said second predetermined angle with the substrate surface using a tilted plasma stream generating device; or alternatively
And applying an external electric field in the horizontal direction to the plasma generating device by adopting the vertical plasma flow generating device, so that the plasma flow generated by the plasma generating device deflects, and the deflected inclined plasma flow has the second preset included angle with the surface of the substrate.
6. The method according to claim 5, wherein the voltage of the applied electric field applied to the plasma generator is 0.3V to 1000V.
7. The method according to claim 4 or 5, wherein the second predetermined angle is between 0 ° and 90 °.
8. The method of claim 1, wherein the trench extends to a depth of 10 a to 100 μm in a vertical direction, extends to a length of 10 a to 100 μm in a horizontal direction, and has a width of 10 a to 1000 a.
9. A semiconductor device, comprising:
a substrate comprising a first dielectric layer;
forming an inclined groove with a preset included angle with the surface of the substrate in the first dielectric layer, wherein the groove is in a regular shape with uniform width from the opening to the bottom, and the preset included angle between the groove and the horizontal surface of the substrate is 10-90 degrees;
a second dielectric layer formed over the first dielectric layer and at an opening of the trench;
wherein the second dielectric layer and the trench form an air gap.
10. The semiconductor device of claim 9, wherein the first dielectric layer further has a metal interconnect layer formed therein.
11. The semiconductor device of claim 9, further comprising an etch stop layer between the substrate and the first dielectric layer.
12. The semiconductor device of claim 9, wherein the trench extends in a vertical direction to a depth of 10 a to 100 μm and in a horizontal direction to a length of 10 a to 100 μm, and wherein the trench has a width of 10 a to 1000 a.
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| CN104037118A (en) * | 2013-03-04 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| TW201729248A (en) * | 2015-11-16 | 2017-08-16 | 英特爾公司 | Structures and methods for improved lithographic processing |
| CN107527913A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| CN107564810A (en) * | 2016-06-30 | 2018-01-09 | 英飞凌科技股份有限公司 | Use directed ion beam formation electrode trenches and the semiconductor devices containing trenched electrode structures |
| CN106548977A (en) * | 2016-10-26 | 2017-03-29 | 上海集成电路研发中心有限公司 | A kind of manufacture method of air-gap structure |
| WO2019035661A1 (en) * | 2017-08-16 | 2019-02-21 | 주식회사 엘지화학 | Method for manufacturing mold substrate for diffraction grating light guide plate and method for manufacturing diffraction grating light guide plate |
| CN109585363A (en) * | 2018-11-13 | 2019-04-05 | 长江存储科技有限责任公司 | A kind of forming method and semiconductor devices of semiconductor devices |
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