TWI736820B - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming a first mask layer on a substrate on which a material layer is formed, and then forming a patterned mask layer on the first mask layer in which the patterned mask layer has a pattern opposite to the predetermined lines. By using the patterned mask layer as an etching mask, a portion of the exposed first mask layer is removed for transferring the pattern into the first mask layer so as to form a plurality of trenches, and the material layer is not exposed from the trenches. A second mask layer is formed in the trenches, and the exposed first mask layer is removed by using the second mask layer as an etching mask until the material layer is exposed to form the plurality of lines.

Description

Manufacturing method of semiconductor element

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that can avoid the problem of line wiggle.

Dynamic Random Access Memory (DRAM) is composed of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor, and each memory cell is electrically connected to each other by a word line and a bit line.

In order to increase the integration degree of the dynamic random access memory and meet the trend of miniaturization of components, a very small critical dimension (CD) is required, but too small a critical dimension (CD) can easily lead to a wiggle phenomenon in the formed line.

The invention provides a method for manufacturing a semiconductor element, which can integrate the existing manufacturing process and achieve the effect of avoiding the phenomenon of wire swing.

The manufacturing method of the semiconductor device of the present invention includes forming a first mask layer on a substrate on which a material layer has been formed, and then forming a patterned mask layer on the first mask layer, wherein the patterned mask The curtain layer has a pattern opposite to the predetermined number of lines. Use the patterned mask layer as an etching mask to remove part of the exposed first mask layer, and transfer the pattern to the first mask layer to form several trenches, and the trenches are not exposed Material layer. Then, a second mask layer is formed in the trench, and the second mask layer is used as an etching mask, and the exposed first mask layer is removed until the material layer is exposed to form the line.

In an embodiment of the present invention, the method for forming the second mask layer includes depositing a hard mask material on the substrate to fill the trench, and then planarize the hard mask material until the first mask layer is exposed. Mask layer.

In an embodiment of the present invention, the hard mask material includes silicon nitride or silicon.

In an embodiment of the present invention, the ratio of the depth of the trench to the thickness of the first mask layer is 40% to 80%.

In an embodiment of the present invention, the ratio of the height of the line to the distance between the two lines is less than 4, such as 2~3.

In an embodiment of the present invention, the above-mentioned method for removing the exposed part of the first mask layer includes dry etching.

In an embodiment of the present invention, after the above-mentioned lines are formed, the lines can also be used as an etching mask to remove the exposed material layer.

Based on the above, the present invention first forms a pattern with lines opposite to the predetermined small CD on the first mask layer, and then uses the second mask layer filled with the pattern as the actual etching mask. Compared with the etching mask composed of multiple layers of different materials in the existing manufacturing process, the present invention can reduce the aspect ratio of the pattern in the etching mask, and thus avoid the line swing phenomenon.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, some embodiments are listed in conjunction with the accompanying drawings for detailed description, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in accordance with the original dimensions. To facilitate understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "include", "have" and so on used in the text are all open terms; that is, it means including but not limited to. Moreover, the directional terms mentioned in the text, such as "上", "下", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

1A, a first mask layer 104 is formed on a substrate 100 on which a material layer 102 has been formed. The substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator, SOI) on an insulating layer. The material layer 102 may be an inner dielectric layer, such as spin on dielectrics (SOD); the first mask layer 104 may be a silicon oxide layer or borophosphosilicate glass (BPSG), and may be It is formed by molecular layer deposition (MLD) or tetraethoxysilane (TEOS) as raw materials. There may also be various semiconductor device structures on the substrate 100. For example, taking a dynamic random access memory (DRAM) as an example, the substrate 100 has formed an isolation structure 108 that defines a plurality of active regions 106 on the substrate 100. There are already word line groups 110 in each active area 106, and each word line group 110 has two buried word lines 112a, 112b. The isolation structure 108 is, for example, a shallow trench isolation structure (STI). The buried word lines 112a and 112b respectively include a gate 114 and a gate dielectric layer 116. In addition, there is a silicon oxide layer 118 between the material layer 102 and the substrate 100, and a silicon nitride layer 120 between the material layer 102 and the character line group 110, and the like. The manufacturing process of this embodiment is to form the bit line contact window (not shown) in the DRAM on the active area 106; however, the present invention is not limited to this, and the ratio of line width to space (Line/Space) is different. If the lithography process is too large, such as the line width is small but the spacing is large, the process of the present invention can be used to improve the line wobble problem without having the DRAM structure in the embodiment. Then, a patterned mask layer 122 is formed on the first mask layer 104, and the patterned mask layer 122 is, for example, a photoresist. In this embodiment, the patterned mask layer 122 has a pattern 124 that is opposite to the predetermined number of lines, that is, the position of the predetermined line is at the position 124 where the first mask layer 104 is exposed.

Next, referring to FIG. 1B, using the patterned mask layer 122 as an etching mask, the exposed part of the first mask layer 104 is removed, and the pattern is transferred to the first mask layer 104 to form a plurality of trenches 126. Moreover, the trench 126 does not expose the material layer 102. In one embodiment, the method of removing the exposed part of the first mask layer 104 is dry etching, and the depth d of the trench 126 can be controlled by controlling the process parameters of the dry etching. For example, the depth d of the trench 126 accounts for 40% to 80% of the thickness t1 of the first mask layer 104, such as 50% to 70%. Afterwards, the patterned mask layer 122 can be removed, but the invention is not limited to this.

Then, referring to FIG. 1C, in order to form a second mask layer in the trench 126, a hard mask material 128 may be deposited on the substrate 100 to fill the trench 126, wherein the hard mask material 128 is for example silicon nitride , Silicon or other materials with a high etching selection ratio with the first mask layer 104.

Next, referring to FIG. 1D, the hard mask material 128 of FIG. 1C is planarized by a method such as etch-back or chemical mechanical polishing (CMP) until the first mask layer 104 is exposed to form a second mask in the trench 126 The curtain layer 128a. Since the depth d of the trench 126 accounts for 40% to 80% of the thickness t1 of the first mask layer 104, the thickness of the second mask layer 128a may be 40% to the thickness t1 of the first mask layer 104. 80%. However, the present invention is not limited to this. The thickness of the second mask layer 128a may also be slightly lower than the above range.

Afterwards, referring to FIG. 1E, the second mask layer 128a is used as an etching mask, and the first mask layer 104 exposed in FIG. 1D is removed until the material layer 102 is exposed to form a second mask layer 128a and a second mask layer 128a. A line 130 formed by a mask layer 104a. In one embodiment, the ratio of the height h of the line 130 to the distance s between the two lines 130 (that is, the aspect ratio of the pattern between the lines 130) is about less than 4 (for example, 2~3), so the subsequent etching material layer 102 is not easy to cause the line to sway. In addition, the first mask layer 104a under the second mask layer 128a can be used as an etching stop layer in the subsequent step of etching the same material (such as silicon nitride) as the second mask layer 128a.

Next, referring to FIG. 1F, after the lines 130 are formed, the lines 130 can be used as an etching mask to remove the exposed material layer 102 until the active region 106 of the substrate 100 is exposed to form a bit line contact window in the DRAM Opening 132. However, the present invention is not limited to this. In other embodiments, after the lines 130 are formed, a deposition process or an etching process in other regions may also be performed, and then the step of FIG. 1F may be performed.

In summary, the process of the present invention first forms a pattern on the first mask layer that has a pattern opposite to the predetermined lines, and then uses the second mask layer filled with the pattern as the actual etching mask, so it is different from the existing process Compared with the etching mask composed of multiple layers of materials (such as SiO ₂ layer/aC layer/SiN layer/SiO ₂ layer), the aspect ratio of the pattern in the etching mask can be reduced to avoid line swinging.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: substrate 102: material layer 104, 104a: first mask layer 106: active area 108: isolation structure 110: character line group 112a, 112b: buried character line 114: gate 116: gate dielectric layer 118: silicon oxide layer 120: silicon nitride layer 122: patterned mask layer 124: part 126: trench 128: hard mask material 128a: second mask layer 130: line 132: bit line contact window d: depth h: height s: distance t1, t2: thickness

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

100: base

102: Material layer

104: The first mask layer

106: active area

108: Isolation structure

110: Character line group

112a, 112b: buried character line

114: Gate

116: gate dielectric layer

118: silicon oxide layer

120: silicon nitride layer

126: Ditch

128a: The second mask layer

d: depth

t1: thickness

Claims (8)

A method for manufacturing a semiconductor element includes: forming a first mask layer on a substrate on which a material layer has been formed; forming a patterned mask layer on the first mask layer, wherein the patterned mask The screen layer has a pattern opposite to the predetermined number of lines; the patterned mask layer is used as an etching mask, and the exposed part of the first mask layer is removed to transfer the pattern to the The first mask layer forms a plurality of trenches, and the plurality of trenches do not expose the material layer; a second mask layer is formed in the plurality of trenches; and the second mask layer is used as an etching A mask, removing the exposed first mask layer until the material layer is exposed to form the plurality of lines, wherein the method of forming the second mask layer includes: depositing a mask layer on the substrate Hard mask material to fill the plurality of trenches; and flattening the hard mask material until the first mask layer is exposed. According to the method for manufacturing a semiconductor device described in the first item of the patent application, the hard mask material includes silicon nitride. According to the method of manufacturing a semiconductor device as described in claim 1, wherein the hard mask material includes silicon. According to the method for manufacturing a semiconductor device according to the first item of the scope of patent application, the ratio of the depth of the trench to the thickness of the first mask layer is 40% to 80%. According to the method for manufacturing a semiconductor device described in the first item of the scope of the patent application, the ratio of the height of the line to the distance between the two lines is less than 4. According to the method for manufacturing a semiconductor device as described in item 5 of the scope of the patent application, the ratio of the height of the line to the distance between the two lines is 2 to 3. According to the method of manufacturing a semiconductor device described in the first item of the scope of patent application, the method of removing the exposed part of the first mask layer includes dry etching. According to the method for manufacturing a semiconductor device described in the first item of the patent application, after the formation of the plurality of lines, the method further includes using the plurality of lines as an etching mask to remove the exposed material layer.

Images