CN107516410B - Be applied to host computer MBUS receiving circuit of multinode - Google Patents
Be applied to host computer MBUS receiving circuit of multinode Download PDFInfo
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- CN107516410B CN107516410B CN201710838049.8A CN201710838049A CN107516410B CN 107516410 B CN107516410 B CN 107516410B CN 201710838049 A CN201710838049 A CN 201710838049A CN 107516410 B CN107516410 B CN 107516410B
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- G—PHYSICS
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Abstract
The invention provides a master MBUS receiving circuit applied to multiple nodes, which comprises a pre-stage filtering differential amplifying circuit and a signal output circuit, wherein the pre-stage filtering differential amplifying circuit comprises a pre-stage filtering circuit and a differential amplifying circuit, the pre-stage filtering circuit comprises a first filtering circuit for receiving high-level signals, a second filtering circuit for receiving low-level signals and a capacitor C14 connected with the first filtering circuit and the second filtering circuit, the differential amplifying circuit comprises an operational amplifier, and the first filtering circuit outputs signals to a third pin end of the operational amplifier and the second filtering circuit outputs signals to a fourth pin end of the operational amplifier. The circuit provided by the invention can enable the received signals to be output to a host end through the signal output circuit after being subjected to multistage filtering and amplification, effectively improves the strength of the received signals, enhances the stability of signal output, and increases the number of load carried by slave nodes, thereby improving the load capacity of the circuit and the anti-interference capacity of the received signals.
Description
Technical Field
The invention belongs to the technical field of control circuits, and particularly relates to a multi-node master MBUS receiving circuit.
Background
The current MBUS is a bus protocol specially designed for remote data transmission of a heat meter, is an important technology for data transmission digitization of a measuring instrument, has been widely applied to data acquisition occasions of passive joints such as water, electricity, gas, heat meters and the like, and has the characteristics of poor anti-interference capability, poor transmission distance, low communication rate, few bus nodes and the like in industry.
Disclosure of Invention
The invention aims to provide a multi-node master MBUS receiving circuit which can solve the defects in the prior art.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
The utility model provides a host computer MBUS receiving circuit for multinode, includes preceding filtering differential amplification circuit and the signal output circuit of received signal, preceding filtering differential amplification circuit includes preceding filtering circuit and differential amplification circuit, preceding filtering circuit includes the first filter circuit of receiving high level signal and the second filter circuit of receiving low level signal and connects first filter circuit and second filter circuit's electric capacity C14, first filter circuit includes resistance R12, electric capacity C12, resistance R9, resistance R12 receives high level signal and exports through parallelly connected electric capacity C12 and resistance R9; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives an output signal of the first filter circuit and outputs the output signal to a third pin end of the resistor R10 and the operational amplifier, the resistor R20 receives a signal output by the second filter circuit and outputs the signal to a fourth pin end of the operational amplifier, the two ends of the resistor R42 and the capacitor C17 are respectively connected with the first pin end and the fourth pin end of the operational amplifier after being connected in parallel, the third pin end and the fourth pin end of the operational amplifier output signals to the first pin end, differential amplification is realized through the action between the resistor R10 and the resistor R11 and the action between the resistor R20 and the resistor R42, and voltage output differential amplifying signals are provided to the signal output circuit.
Further, the host MBUS receiving circuit further comprises a filtering amplifying circuit, the filtering amplifying circuit comprises a first filtering amplifier and a second filtering amplifier which are connected in series through a capacitor C5, one end of the capacitor C5 is connected with the output end of the first filtering amplifier, the other end of the capacitor C5 is connected with the same-direction input end of the second filtering amplifier, the same-direction input end of the first filtering amplifier receives signals output by the front-stage filtering differential amplifying circuit through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the reverse input end of the first filtering amplifier is connected to a node between the output end of the first filtering amplifier and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, and the reverse input end of the first filtering amplifier is grounded through a resistor R46; the output signal of the capacitor C5 is received by the same-direction input end of the second filter amplifier through the resistor R16, the resistor R24 and the capacitor C18, the output end of the second filter amplifier feeds back a signal to the reverse input end of the second filter amplifier through the resistor R27 and the capacitor C6 which are connected in parallel, and the reverse input end of the second filter amplifier is grounded through the resistor R31.
Further, the signal output circuit comprises a voltage comparator and a comparison circuit, wherein the reverse input end of the voltage comparator receives an output signal of the pre-stage filtering differential amplifying circuit through a resistor R40 and a capacitor C15, the comparison circuit comprises a resistor R26, a resistor R30 and a capacitor C8, the resistor R26 receives a voltage provided by a power supply VCC30A and outputs the voltage to the same-direction input end of the resistor R30 and the voltage comparator respectively, the same-direction input end of the voltage comparator is grounded through the capacitor C8, the other end of the resistor R30 is grounded, and the output end of the voltage comparator outputs a signal to a host receiving end.
Still further, the signal output circuit further includes a signal undervoltage circuit, the signal undervoltage circuit includes a resistor R45 and a resistor R47 connected in series, a diode D2, a diode D4, and a capacitor C19, the resistor R45 and the resistor 47 receive a voltage provided by the power VCC30A and are connected to a cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, an anode of the diode D4 is connected to a node between the capacitor C15 and an inverting input terminal of the voltage comparator, the cathode of the diode D2 is connected to an inverting input terminal of the voltage comparator, and an anode of the diode D2 is grounded.
The host MBUS receiving circuit provided by the invention enables the received signals to be output to a host end through the signal output circuit after the multistage filtering differential amplifying circuit and the filtering amplifying circuit are used for filtering and amplifying, the received signal strength can be improved, the signal robustness is enhanced, the signal output stability is enhanced, the number of load from nodes is increased, and the maximum number of nodes is more than 2000, so that the circuit load capacity and the anti-interference capacity of the received signals are improved, the application in industrial environment is satisfied, and the communication rate is improved.
Drawings
FIG. 1 is a circuit flow diagram of the overall invention;
FIG. 2 is a schematic circuit diagram of the whole of the present invention;
In the figure: 1. a pre-stage filtering differential amplifying circuit; 2. a filter amplifying circuit; 3. and a signal output circuit.
Detailed Description
The following describes the present invention in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the host MBUS receiving circuit includes a front-stage filtering differential amplifying circuit 1, a filtering amplifying circuit 2 and a signal output circuit 3 that receive signals. As shown in fig. 2, the pre-stage filtering differential amplifying circuit 1 includes a pre-stage filtering circuit and a differential amplifying circuit, wherein the pre-stage filtering circuit includes a first filtering circuit that receives a high-level signal and a second filtering circuit that receives a low-level signal, and a capacitor C14 that connects the first filtering circuit and the second filtering circuit; the first filter circuit comprises a resistor R12, a capacitor C12 and a resistor R9, wherein the resistor R12 receives a high-level signal and outputs the high-level signal through the capacitor C12 and the resistor R9 which are connected in parallel, and the other ends of the resistor R9 and the capacitor C12 are grounded; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel, and the other ends of the outputs of the capacitor C16 and the resistor R23 are grounded; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives an output signal of the first filtering circuit and outputs the output signal to a resistor R10 and a third pin terminal VIN+ of the operational amplifier, the other end of the resistor R10 is grounded, the resistor R20 receives a signal output by the second filtering circuit and outputs the signal to a fourth pin terminal VIN-of the operational amplifier, the two ends of the resistor R42 and the capacitor C17 are respectively connected with a first pin terminal OUT and a fourth pin terminal VIN-of the operational amplifier after being connected in parallel, the third pin terminal VIN+ and the fourth pin terminal VIN-of the operational amplifier output to the first pin terminal OUT, differential amplification of the signal is realized through the functions between the resistor R11 and the resistor R20 and the resistor R10 and the resistor R42, and the differential amplifying signal is output from the first pin terminal OUT to the filtering amplifying circuit in the embodiment; the second pin GND of the operational amplifier is grounded, and the fifth pin VCC receives the voltage provided by the VCC30A power supply. The circuit uses a high-precision filtering differential amplifying circuit to effectively inhibit the interference of common-mode signals, improve the stability of received signals and increase the load quantity of slave nodes.
As shown in fig. 2, the filter amplifying circuit 2 includes a first filter amplifier U2A and a second filter amplifier U2B connected in series through a capacitor C5, one end of the capacitor C5 is connected to the output end of the first filter amplifier U2A, the other end is connected to the co-directional input end of the second filter amplifier U2B, and the first filter amplifier U2A receives the signal output by the front-stage filter differential amplifying circuit and amplifies the signal by the second filter amplifier U2B to output the signal to the signal output circuit; the signal output by the differential amplifying circuit is received by the same-direction input end of the first filter amplifier U2A through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the reverse input end of the first filter amplifier U2A is connected to a node between the output end of the first filter amplifier U2A and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, the reverse input end of the first filter amplifier U2A is grounded through a resistor R46, and the signals of the same-direction input end and the reverse input end are received by the output end of the first filter amplifier U2A and output to the second filter amplifier U2B through a capacitor C5; the output signal of a capacitor C5 is received by the same-direction input end of the second filter amplifier U2B through a resistor R16, a resistor R24 and a capacitor C18, the other ends of the resistor R24 and the capacitor C18 are grounded, the output end of the second filter amplifier U2B feeds back a signal to the reverse input end of the second filter amplifier U2B through a resistor R27 and a capacitor C6 which are connected in parallel, the reverse input end of the second filter amplifier U2B is grounded through a resistor R31, and the output end of the second filter amplifier U2B receives signals of the same-direction input end and the reverse input end and outputs the signals to a resistor R40 and a capacitor C15 of a signal output circuit. The circuit is amplified by multistage filtering, so that signal assignment is effectively improved, signal robustness is enhanced, and the load quantity of bus slave nodes is further increased.
As shown in fig. 2, the signal output circuit 3 includes a voltage comparator U1B, a comparison circuit and a signal undervoltage circuit, where an inverting input end of the voltage comparator U1B receives a signal output by an output end of the second filter amplifier U2B through a resistor R40 and a capacitor C15, the capacitor C15 is grounded through a resistor R44, the comparison circuit includes a resistor R26, a resistor R30 and a capacitor C8, the resistor R26 receives a voltage provided by a power VCC30A and outputs the voltage to the same directional input ends of the resistor R30 and the voltage comparator U1B, the same directional input end of the voltage comparator U1B is grounded through the capacitor C8, the other end of the resistor R30 is grounded, and the output end of the voltage comparator U1B outputs the signal to a host receiving end; the signal undervoltage circuit can provide bias voltage for signals and comprises a resistor R45, a resistor R47, a diode D2, a diode D4 and a capacitor C19 which are connected in series, wherein the resistor R45 and the resistor 47 receive voltage provided by a power supply VCC30A and are connected to the cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, the anode of the diode D4 is connected to a node between the capacitor C15 and the reverse input end of the voltage comparator, the cathode of the diode D2 is connected to the reverse input end of the voltage comparator, and the anode of the diode D2 is grounded.
The working principle of the invention is as follows: as shown in figure 1, the signal sent by the sending end of the receiving host is filtered by the pre-stage filter circuit and sent to the differential amplifier circuit to be amplified by the operational amplifier, so that the stability of the received signal is improved, the interference of common-mode signals and noise is restrained, the signal sent by the differential amplifier circuit is amplified by the multi-stage filter of the first filter amplifier and the second filter amplifier in the filter amplifier circuit, the strength of the received signal can be effectively improved, the robustness of the signal is enhanced, the stability of signal output is enhanced, the loading quantity of buses from nodes is further increased, the final signal is sent to the signal output circuit, the bias voltage is provided by the signal undervoltage circuit, and the host received signal is output after the bias voltage is compared with the reference level of the fifth pin end of the voltage comparator.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the scope of protection defined by the claims of the present invention without departing from the spirit of the present invention.
Claims (1)
1. The utility model provides a host computer MBUS receiving circuit for multinode, characterized by including preceding filtering differential amplification circuit (1) and the signal output circuit (3) of received signal, preceding filtering differential amplification circuit (1) include preceding filtering circuit and differential amplification circuit, preceding filtering circuit include receive high level signal's first filter circuit and receive low level signal's second filter circuit and connect first filter circuit and second filter circuit's electric capacity C14, first filter circuit includes resistance R12, electric capacity C12, resistance R9, resistance R12 receives high level signal and exports through parallel connection's electric capacity C12 and resistance R9; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives output signals of the first filter circuit and outputs the output signals to the resistor R10 and a third pin terminal (VIN+), the resistor R20 receives output signals of the second filter circuit and outputs the output signals to a fourth pin terminal (VIN-), the resistor R42 and the capacitor C17 are connected in parallel, and the two ends of the resistor R42 and the capacitor C17 are respectively connected with a first pin terminal (OUT) and a fourth pin terminal (VIN-), and the first pin terminal (OUT) of the operational amplifier outputs signals;
The host MBUS receiving circuit further comprises a filter amplifying circuit (2), the filter amplifying circuit comprises a first filter amplifier (U2A) and a second filter amplifier (U2B) which are connected in series through a capacitor C5, the homodromous input end of the first filter amplifier (U2A) receives signals output by the front-stage filter differential amplifying circuit through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the reverse input end of the first filter amplifier (U2A) is connected to a node between the output end of the first filter amplifier (U2A) and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, and the reverse input end of the first filter amplifier (U2A) is grounded through a resistor R46; the output signal of a capacitor C5 is received by the homodromous input end of the second filter amplifier (U2B) through a resistor R16, a resistor R24 and a capacitor C18, the output end of the second filter amplifier (U2B) feeds back a signal to the reverse input end of the second filter amplifier (U2B) through a resistor R27 and a capacitor C6 which are connected in parallel, and the reverse input end of the second filter amplifier (U2B) is grounded through a resistor R31;
The signal output circuit comprises a voltage comparator (U1B) and a comparison circuit, wherein the reverse input end of the voltage comparator (U1B) receives an output signal of the differential amplification circuit through a resistor R40 and a capacitor C15, the comparison circuit comprises a resistor R26, a resistor R30 and a capacitor C8, the resistor R26 receives voltage provided by a power supply VCC30A and outputs the voltage to the same-direction input end of the resistor R30 and the voltage comparator (U1B), the same-direction input end of the voltage comparator (U1B) is grounded through the capacitor C8, the other end of the resistor R30 is grounded, and the output end of the voltage comparator (U1B) outputs a signal to the host receiving end;
The signal output circuit further comprises a signal undervoltage circuit, the signal undervoltage circuit comprises a resistor R45, a resistor R47, a diode D2, a diode D4 and a capacitor C19 which are connected in series, the resistor R45 and the resistor 47 receive voltage provided by a power supply VCC30A and are connected to the cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, the anode of the diode D4 is connected to a node between the capacitor C15 and the reverse input end of the voltage comparator (U1B), the cathode of the diode D2 is connected to the reverse input end of the voltage comparator (U1B), and the anode of the diode D2 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710838049.8A CN107516410B (en) | 2017-09-18 | 2017-09-18 | Be applied to host computer MBUS receiving circuit of multinode |
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| CN201710838049.8A CN107516410B (en) | 2017-09-18 | 2017-09-18 | Be applied to host computer MBUS receiving circuit of multinode |
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| CN107516410A CN107516410A (en) | 2017-12-26 |
| CN107516410B true CN107516410B (en) | 2024-05-03 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108447241B (en) * | 2018-03-30 | 2020-05-08 | 王海霞 | Medical equipment signal transmission calibrating device |
| CN108649978B (en) * | 2018-04-09 | 2021-06-11 | 深圳市源啓智能科技有限公司 | MBUS host computer receiving circuit |
| CN109302194B (en) * | 2018-11-29 | 2023-10-20 | 苏州东剑智能科技有限公司 | Mbus host receiving circuit |
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-
2017
- 2017-09-18 CN CN201710838049.8A patent/CN107516410B/en active Active
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|---|---|---|---|---|
| US5870016A (en) * | 1997-02-03 | 1999-02-09 | Eva Cogenics Inc Euaday Division | Power line carrier data transmission systems having signal conditioning for the carrier data signal |
| WO2010076028A1 (en) * | 2008-12-31 | 2010-07-08 | Elster Messtechnik Gmbh | System and method for determining and monitoring volume flows |
| CN205177146U (en) * | 2015-11-20 | 2016-04-20 | 黑龙江盛华霖科技发展股份有限公司 | High -power MBUS host computer |
| CN206497149U (en) * | 2017-01-18 | 2017-09-15 | 成都拓来微波技术有限公司 | A kind of novel microwave signal power detection module |
| CN207458323U (en) * | 2017-09-18 | 2018-06-05 | 瑞纳智能设备股份有限公司 | A kind of host MBUS receiving circuits applied to multinode |
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| 空间粒子探测器中一种微电流测量电路设计;雷升杰;魏志勇;陈国云;张紫霞;黄三玻;方美华;;宇航计测技术(06);全文 * |
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Address after: 230011 Anhui province Changfeng Shuangfeng Economic Development Zone Xia Feng East Road Hefei City No. 039 Applicant after: RUNA SMART EQUIPMENT Co.,Ltd. Address before: 230011 Anhui province Changfeng Shuangfeng Economic Development Zone Xia Feng East Road Hefei City No. 039 Applicant before: HEFEI RUNA METERING Co.,Ltd. |
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