CN108230652B - High-power MBUS master controller circuit - Google Patents
High-power MBUS master controller circuit Download PDFInfo
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- CN108230652B CN108230652B CN201710970294.4A CN201710970294A CN108230652B CN 108230652 B CN108230652 B CN 108230652B CN 201710970294 A CN201710970294 A CN 201710970294A CN 108230652 B CN108230652 B CN 108230652B
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- 238000001914 filtration Methods 0.000 claims abstract description 69
- 238000005070 sampling Methods 0.000 claims abstract description 39
- 239000003990 capacitor Substances 0.000 claims description 121
- 230000005669 field effect Effects 0.000 claims description 39
- 239000011324 bead Substances 0.000 claims description 20
- 238000001514 detection method Methods 0.000 claims description 20
- 238000011084 recovery Methods 0.000 claims description 9
- 230000000087 stabilizing effect Effects 0.000 claims description 8
- 230000003321 amplification Effects 0.000 claims description 7
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004146 energy storage Methods 0.000 description 2
- 206010053615 Thermal burn Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- -1 electricity Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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Abstract
The invention provides a high-power MBUS master controller circuit which comprises a host sending circuit and a host receiving circuit, wherein the host sending circuit comprises a direct current power supply and a sending control circuit, the host receiving circuit comprises a sampling resistor, a pre-stage filtering differential amplifying circuit and a signal output circuit, the pre-stage filtering differential amplifying circuit comprises a pre-stage filtering circuit and a differential amplifying circuit, the differential amplifying circuit comprises an operational amplifier, the pre-stage filtering circuit comprises a first filtering circuit and a second filtering circuit, and the first filtering circuit and the second filtering circuit respectively output to the operational amplifier and provide voltage output differential amplifying signals through the operational amplifier. The circuit has simple design, the power supply current is more than 3A, the sampling resistor with low resistance value and the high-precision differential amplifying circuit are adopted to inhibit the interference of common mode signals, improve the stability of received signals and increase the load number of slave nodes.
Description
Technical Field
The invention belongs to the technical field of control circuits, and particularly relates to a high-power MBUS master controller circuit.
Background
The MBUS is a bus protocol specially designed for remote data transmission of a heat meter, is an important technology for data transmission digitization of a measuring instrument, has been widely applied to the data acquisition occasions of passive joints such as water, electricity, gas, heat meters and the like, is low in host bus remote power supply carrying capacity, poor in driving load capacity and poor in field product adaptability, so that the defects of very difficult field maintenance and installation and the like are overcome, and meanwhile, the sampled resistor of a host receiving part heats and scalds when the current MBUS host circuit is provided with a plurality of loads, the resistor burns out easily in a long-time heating and scalding state, the service life of the resistor is reduced, and the communication performance and the product stability are reduced.
Disclosure of Invention
According to the high-power MBUS master controller circuit provided by the invention, the sampling resistor with a low resistance value and the high-precision filtering differential amplifying circuit are adopted to inhibit the interference of common-mode signals and improve the stability of received signals, the number of node loading is increased, and the adopted filtering amplifying circuit is subjected to multistage filtering amplification, so that signal assignment is effectively improved to enhance signal robustness, and the number of bus slave node loading is further increased.
In order to solve the technical problems and achieve the technical effects, the adopted technical proposal is that,
The high-power MBUS master controller circuit comprises a direct-current power supply and a transmission control circuit for receiving a host transmission signal, wherein the host receiving circuit comprises a sampling resistor connected with the transmission control circuit, a front-stage filtering differential amplifying circuit for receiving a signal output by the sampling resistor and a signal output circuit, the direct-current power supply comprises a high-voltage rail power supply and a filtering circuit, the filtering circuit comprises a capacitor C11, a power magnetic bead FB1, a power magnetic bead FB2, a capacitor C2 and a bypass capacitor C3, the high-voltage rail power supply is output to the power magnetic bead FB1 and the power magnetic bead FB2 which are connected in parallel through the capacitor C11, the other ends of the power magnetic bead FB1 and the power magnetic bead FB2 are connected with the capacitor C2 and the bypass capacitor C3 which are connected in parallel to output voltage, and the other ends of the capacitor C11, the capacitor C2 and the power bypass capacitor C3 are grounded; the pre-stage filtering differential amplifying circuit comprises a pre-stage filtering circuit and a differential amplifying circuit, wherein the pre-stage filtering circuit comprises a first filtering circuit for receiving a high-level signal output by a sampling resistor, a second filtering circuit for receiving a low-level signal output by the sampling resistor and a capacitor C14 for connecting the first filtering circuit and the second filtering circuit, the first filtering circuit comprises a resistor R12, a capacitor C12 and a resistor R9, and the resistor R12 receives the high-level signal and outputs the high-level signal through the capacitor C12 and the resistor R9 which are connected in parallel; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives output signals of the first filter circuit and outputs the output signals to the resistor R10 and a third pin end of the operational amplifier, the resistor R20 receives output signals of the second filter circuit and outputs the output signals to a fourth pin end of the operational amplifier, and the two ends of the resistor R42 and the capacitor C17 are respectively connected with the first pin end and the fourth pin end of the operational amplifier after being connected in parallel.
Further, the sampling resistor comprises a resistor R37, a resistor R38, a resistor R29 and a resistor R17 which are sequentially connected in parallel.
Further, the transmission control circuit includes a resistor R18, a resistor R22, a triode Q2, a resistor R8, a resistor R6, a field effect transistor Q1, a resistor R28, a resistor R32, a triode Q3, a resistor R14, a diode D3, a resistor R29, a resistor R7, a triode Q4 and a diode D5, wherein a host signal is received by the resistor R18 and is output to a base electrode of the triode Q2 through the resistor R22, an emitter electrode of the triode Q2 and the other end of the resistor R22 are grounded, a collector electrode of the triode Q2 is output to a gate electrode of the field effect transistor Q1 through the resistor R8, a drain electrode of the field effect transistor Q1 receives a power VCC33, the resistor R6 is connected to both ends of the gate electrode and the drain electrode of the field effect transistor Q1, and an original electrode of the field effect transistor Q1 is output to the self-recovery fuse F1 through a sampling resistor; the resistor R28 receives a host signal and outputs the host signal to the base electrode of the triode Q3 through the resistor R32, the emitter electrode of the triode Q3 and the other end of the resistor R32 are grounded, the collector electrode of the triode Q3 is respectively connected with the resistor R7 and the anode electrode of the diode D3 through the resistor R14, the other end of the resistor R7 is connected with the power VCC33, the cathode electrode of the diode D3 is respectively output to the base electrode of the triode Q4 and the resistor R29, the other end of the resistor R29 is respectively connected to the emitter electrode of the triode Q4 and the anode electrode of the diode D5, and the collector electrode of the triode Q4 is respectively connected with the cathode electrode of the diode D5 and the MBUSV-end of the sampling resistor to output to the self-recovery fuse F1.
Further, the host sending circuit further comprises a power supply control circuit which receives the voltage output by the direct-current power supply and is connected with the sending control circuit, the power supply control circuit comprises an integrated control chip, a ninth pin end of the integrated control chip is connected with the direct-current power supply, a first pin end of the integrated control chip is output to an anode of a diode D5 on the sending control circuit through a power inductor L1 and is output to an MBUS bus through a self-recovery fuse F1 through a cathode output end of the diode D5, the integrated control chip provides a low-level signal for the MBUS bus through a voltage output circuit, the voltage output circuit comprises a resistor R53 connected between the diode D5 and the power inductor L1 in series, a resistor R54 connected with the resistor R53 and a capacitor C35, the resistor R53 and the resistor R54 are output to a sixth pin end of the integrated control chip, the sixth pin end (FB) is grounded through the capacitor C35, and the other end of the resistor R54 is grounded.
Further, the host sending circuit further comprises a voltage modulation circuit for adjusting the power supply control circuit, the voltage modulation circuit comprises a resistor R57, a triode Q8 and a resistor R56, a collector of the triode Q8 is output to a sixth pin end of the integrated control chip through the resistor R56, an emitter of the triode Q8 is grounded, a base of the triode Q8 is connected with the resistor R57, and the other end of the resistor R57 receives a differential pressure modulation signal capable of conducting the triode Q8.
Further, the host sending circuit further comprises a receiving and sending control circuit connected with the sampling resistor, the receiving and sending control circuit comprises a field effect transistor Q5, a resistor R15, a resistor R19, a field effect transistor Q6, a resistor R41 and a resistor R43, the resistor R41 receives a host signal MCU_Con and outputs the host signal MCU_Con to gates of the resistor R43 and the field effect transistor Q6, the other end of the resistor R43 is grounded, a drain electrode of the field effect transistor Q6 is respectively connected with the gate electrode of the field effect transistor Q5 and the resistor R15 through the resistor R19, a source electrode of the field effect transistor Q6 is grounded, a drain electrode and a source electrode of the field effect transistor Q5 are respectively connected with a MBUSV + end and a MBUSV end of the sampling resistor, and the other end of the resistor R15 is connected with a drain electrode of the field effect transistor Q5.
Further, the host receiving circuit further comprises a filter amplifying circuit, the filter amplifying circuit comprises a first filter amplifier (U2A) and a second filter amplifier which are connected in series through a capacitor C5, the homodromous input end of the first filter amplifier receives signals output by the front-stage filter differential amplifying circuit through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the reverse input end of the first filter amplifier is connected to a node between the output end of the first filter amplifier and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, and the reverse input end of the first filter amplifier is grounded through a resistor R46; the unidirectional input end of the second filter amplifier receives the output signal outputted from the first filter amplifier to the capacitor C5 through the resistor R16, the resistor R24 and the capacitor C18, the output end of the second filter amplifier feeds back the signal to the reverse input end of the second filter amplifier through the resistor R27 and the capacitor C6 which are connected in parallel, the reverse input end of the second filter amplifier is grounded through the resistor R31, and the output end of the second filter amplifier receives the signals of the unidirectional input end and the reverse input end of the second filter amplifier and outputs a signal control circuit.
Further, the host receiving circuit further comprises a current detection circuit connected with the output end of the pre-stage filtering differential amplifying circuit, the current detection circuit comprises a comparator and a detection circuit, the reverse input end of the comparator receives an amplified signal of the pre-stage filtering differential amplifying circuit through a resistor R4, the detection circuit comprises a resistor R1, a resistor R2, a stabilizing tube D1 and a bypass capacitor C1, the resistors R1 and R2 receive a power VCC33 and transmit the power VCC33 to the same-direction input end of the comparator through the stabilizing tube D1 and the bypass capacitor C1, and the output end of the comparator outputs the signal to the host end through a resistor R3.
Further, the signal output circuit comprises a voltage comparator and a comparison circuit, wherein the reverse input end of the voltage comparator receives an output signal of the pre-stage filtering differential amplification circuit through a resistor R40 and a capacitor C15, the comparison circuit comprises a resistor R26, a resistor R30 and a capacitor C8, the resistor R26 receives a voltage provided by a power supply VCC30A and is transmitted to the same-direction input end of the voltage comparator through the resistor R30 and the capacitor C8, the other end of the capacitor C8 is grounded, and the output end of the voltage comparator outputs a signal to a host receiving end.
Further, the signal output circuit further comprises a signal undervoltage circuit, the signal undervoltage circuit comprises a resistor R45, a resistor R47, a diode D2, a diode D4 and a capacitor C19 which are connected in series, the resistor R45 and the resistor 47 receive voltage provided by a power supply VCC30A and are connected to the cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, the anode of the diode D4 is connected to a node between the capacitor C15 and the reverse input end of the voltage comparator, the cathode of the diode D2 is connected to the reverse input end of the voltage comparator, and the anode of the diode D2 is grounded.
The invention has the beneficial effects that the power magnetic beads and the capacitor adopted by the direct current power supply enable the direct current power supply to carry out filtering and energy storage, thereby providing a good robustness for the system; the power supply control circuit outputs a level signal for the MBUS bus and provides 4A load driving current, so that the remote power supply driving capability of the bus is effectively improved; the voltage modulation circuit is controlled by signals to have two-gear voltage output, so that two differential voltage modulations of a bus are met, the adaptability of the circuit is effectively improved, and the bus driving load capacity is up to more than 4A current; the transmission control circuit suppresses bus discharge when the output level of the bus MBUS is high, and discharges the high level stored in the bus when the output level of the bus MBUS is low, so that the switch conducts zero-impedance output and the communication effectiveness is improved; the receiving and transmitting control circuit can effectively reduce the heating rate of the sampling resistor when the load is excessive by receiving the host signal; the differential amplifying circuit uses a sampling resistor with a low resistance value and a high-precision differential amplifier to inhibit the interference of common mode signals so as to improve the stability of received signals and increase the number of node load; the filtering and amplifying circuit enables signals to be subjected to multistage filtering and amplifying, so that signal assignment is improved, signal robustness is enhanced, and the number of node loading on a bus is further increased; a voltage comparator arranged on the signal output circuit compares the received signal with a reference level, so that the output host receives the signal; the power supply detection circuit judges overload and short circuit of the current output by the pre-stage filtering and amplifying signal through the comparator, so that the detection cost is reduced, the mode is simple, and the circuit is concise.
Drawings
FIG. 1 is an overall circuit flow diagram of the present invention;
FIG. 2 is a schematic diagram of a host transmitter circuit according to the present invention;
FIG. 3 is a circuit diagram of a host receiving circuit according to the present invention;
In the figure: 1. a direct current power supply; 2. a transmission control circuit; 3. a transmission/reception control circuit; 4. a power supply control circuit; 5. a voltage modulation circuit; 6. sampling a resistor; 7. a pre-stage filtering differential amplifying circuit; 8. a current detection circuit; 9. a filter amplifying circuit; 10. and a signal output circuit.
Detailed Description
The high-power MBUS master controller circuit provided by the invention is further described in detail below with reference to the whole drawings and specific embodiments.
As shown in fig. 1, the high-power MBUS master circuit includes a host transmitting circuit and a host receiving circuit, the host transmitting circuit includes a direct-current power supply 1, a transmitting control circuit 2 for receiving a host transmitting signal, a transmitting and receiving control circuit 3, a power control circuit 4, and a voltage modulation circuit 5 for adjusting the power control circuit, and the host receiving circuit includes a sampling resistor 6, a front-stage filtering differential amplifying circuit 7 connected with the sampling resistor, a signal output circuit 10, a filtering amplifying circuit 9, and a current detecting circuit 8.
As shown in fig. 2, the dc power supply 1 includes a high-voltage rail power supply and a filter circuit, where the filter circuit includes a capacitor C11, a power bead FB1, a power bead FB2, a capacitor C2, and a bypass capacitor C3, where the high-voltage rail power supply outputs to the power bead FB1 and the power bead FB2 connected in parallel through the capacitor C11, and the other ends of the power bead FB1 and the power bead FB2 are connected to output voltages of the capacitor C2 and the bypass capacitor C3 connected in parallel, and the other ends of the capacitor C11, the capacitor C2, and the power bypass capacitor C3 are grounded, so that filtering and energy storage are performed by using the adopted power bead and capacitor, and a good robustness is provided for the circuit system.
As shown in fig. 2, the power supply control circuit 4 is a low-voltage rail power supply output control circuit, and includes an input circuit, a voltage dividing circuit, a frequency circuit, a stabilizing circuit, a starting circuit, a driving circuit and a voltage output circuit, where the input circuit is an input end of the power supply control circuit, and is connected with a ninth pin VIN of the integrated control chip U4 through a capacitor C30, a voltage dividing resistor R50, a resistor R52, a bypass capacitor C29 and a capacitor C27 by a voltage 33V of a power supply output end of the high-voltage rail; the voltage dividing circuit is used for dividing the voltage of the other ends of the voltage dividing resistor R50 and the resistor R52 to the eighth pin end EN of the integrated control chip U4 and used as an enabling pin for starting the integrated control chip U4; the frequency circuit is the working frequency of the fourth pin FSW of the integrated control chip U4, which is connected with the reference ground U4 through a resistor R51, the working frequency of the integrated control chip U4 is adjusted and set by adjusting the resistance value of the resistor R51, and the other end of the resistor R51 is connected with the reference ground; the stabilizing circuit is characterized in that a third pin end COMP end of an integrated circuit core U4 is connected with a capacitor R55 through a capacitor C34, and the other end of the resistor R55 is grounded and used for improving the working steady state of the integrated control chip U4; the starting circuit is characterized in that a seventh pin SS end of the integrated control chip U4 is grounded through a capacitor C26 and used as the soft starting time of the integrated control chip U4, and the soft starting time is controlled by setting the capacity of the capacitor C26; the driving circuit is a switch driver of the integrated control chip U4, wherein a second pin terminal BST of the integrated control chip U4 is connected to a first pin terminal LX of the integrated control chip U4 through a capacitor C28; the output of the power supply control circuit is output to the anode of a diode D5 through a power inductor L1 by taking the first pin end LX end of an integrated control chip U4 as an output end, the output is respectively connected with a capacitor C33 and a resistor R53, the other end of the capacitor C33 is respectively connected with the ground, and the cathode output of the diode D5 is output to an MBUS bus through a self-recovery fuse F1; the voltage output circuit is characterized in that the other end of the resistor R53 is connected with the resistor R54 and the bypass capacitor C53 and outputs the resistor R54 and the capacitor C35 to the sixth pin terminal FB of the integrated control chip U4, the other ends of the resistor R54 and the capacitor C35 are respectively grounded, a low-level signal is provided for the MBUS bus through the voltage output of the first pin terminal LX of the integrated control chip U4, 4A load driving current is provided, and the remote power supply driving capability of the bus is effectively improved. The voltage modulation circuit 5 receives an MCU_VM differential pressure modulation signal, the base electrode of the triode Q8 is connected with the reference ground through the resistor R57, the emitter electrode of the triode Q8 is connected with the sixth pin terminal FB of the integrated control chip U4 through the resistor R56, when the MCU_VM differential pressure modulation signal outputs a high level, the triode Q8 is conducted, the resistor R56 is conducted and grounded through the triode Q8, and the output voltage of the integrated control chip U4 is 0.8 (1+R53/(R54// R56)); when the MCU_VM signal outputs a low level, the triode Q8 is cut off, the resistor R56 is disconnected from the ground, the output voltage of the integrated control chip U4 is 0.8 (1+R53/R54), the voltage output of the integrated control chip U4 is the low level of the bus MBUS, the voltage output of two gears is controlled through the MCU_VM differential pressure modulation signal, two differential pressure modulations of the bus are met, and the load capacity of the bus is driven to be more than 4A current.
As shown in fig. 2, the transmission control circuit 2 includes a resistor R18, a resistor R22, a triode Q2, a resistor R8, a resistor R6, a resistor R7, a field effect transistor Q1, a resistor R28, a resistor R32, a triode Q3, a resistor R14, a diode D3, a resistor R29, a triode Q4 and a diode D5, wherein a host signal is received by the resistor R18 and output to a base electrode of the triode Q2 through the resistor R22, an emitter electrode of the triode Q2 and the other end of the resistor R22 are grounded, a collector electrode of the triode Q2 is output to a gate electrode of the field effect transistor Q1 through the resistor R8, a drain electrode of the field effect transistor Q1 receives a power VCC33, the resistor R6 is connected to both ends of the gate electrode and the drain electrode of the field effect transistor Q1, and an original electrode of the field effect transistor Q1 is connected with a sampling resistor and outputs a signal from a recovery fuse F1; the resistor R28 receives a host signal and outputs the host signal to the base electrode of the triode Q3 through the resistor R32, the emitter electrode of the triode Q3 and the other end of the resistor R32 are grounded, the collector electrode of the triode Q3 is respectively connected with the resistor R7 and the anode electrode of the diode D3 through the resistor R14, the other end of the resistor R7 is connected with the power VCC33, the cathode electrode of the diode D3 is respectively output to the base electrode of the triode Q4 and the resistor R29, the other end of the resistor R29 is respectively connected to the emitter electrode of the triode Q4 and the anode electrode of the diode D5, and the collector electrode of the triode Q4 is respectively connected with the cathode electrode of the diode D5 and the sampling resistor and outputs a signal from the recovery fuse F1. The transmission control circuit suppresses bus discharge when the output level of the bus MBUS is high, and discharges the high level stored in the bus when the output level of the bus MBUS is low, so that the switch conducts zero-impedance output and communication effectiveness is improved.
As shown in fig. 2, the transceiver control circuit 3 includes a field effect transistor Q5, a resistor R15, a resistor R19, a field effect transistor Q6, a resistor R41, and a resistor R43, where the resistor R41 receives a host signal mcu_con and outputs the host signal mcu_con to gates of the resistor R43 and the field effect transistor Q6, the other end of the resistor R43 is grounded, a drain electrode of the field effect transistor Q6 is connected to the gate of the field effect transistor Q5 and the resistor R15 through the resistor R19, a source electrode of the field effect transistor Q6 is grounded, a drain electrode and a source electrode of the field effect transistor Q5 are connected to MBUSV + end and MBUSV end of a sampling resistor, and the other end of the resistor R15 is connected to the drain electrode of the field effect transistor Q5, and the resistor R19 is capable of receiving a slave signal TXDN. The receiving and transmitting control circuit is connected with the sampling resistor through receiving the host signal, and when the circuit is subjected to high-power load, the total flat signal is directly transmitted to the MBUS bus through the receiving and transmitting control circuit without the sampling resistor, so that the heating and scalding phenomena of the sampling resistor caused by overlarge load are reduced, and the service life of the sampling resistor is prolonged.
As shown in fig. 3, the sampling resistor 6 includes a resistor R37, a resistor R38, a resistor R29, and a resistor R17 connected in parallel. The front-stage filtering differential amplifying circuit 7 comprises a front-stage filtering circuit and a differential amplifying circuit, wherein the front-stage filtering circuit comprises a first filtering circuit for receiving a high-level signal of a sampling resistor, a second filtering circuit for receiving a low-level signal of the sampling resistor and a capacitor C14 for connecting the first filtering circuit and the second filtering circuit; the first filter circuit comprises a resistor R12, a capacitor C12 and a resistor R9, wherein the resistor R12 receives a high-level signal and outputs the high-level signal through the capacitor C12 and the resistor R9 which are connected in parallel, and the other ends of the resistor R9 and the capacitor C12 are grounded; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel, and the other ends of the outputs of the capacitor C16 and the resistor R23 are grounded; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives an output signal of the first filtering circuit and outputs the output signal to a resistor R10 and a third pin terminal VIN+ of the operational amplifier, the other end of the resistor R10 is grounded, the resistor R20 receives a signal output by the second filtering circuit and outputs the signal to a fourth pin terminal VIN-of the operational amplifier, the two ends of the resistor R42 and the capacitor C17 are respectively connected with a first pin terminal OUT and a fourth pin terminal VIN-of the operational amplifier after being connected in parallel, the third pin terminal VIN+ and the fourth pin terminal VIN-of the operational amplifier output to the first pin terminal OUT, differential amplification of the signal is realized through the functions between the resistor R11 and the resistor R20 and the resistor R10 and the resistor R42, and the differential amplifying signal is output from the first pin terminal OUT to the filtering amplifying circuit in the embodiment; the second pin GND of the operational amplifier is grounded, and the fifth pin VCC receives the voltage provided by the VCC30A power supply. The circuit uses a sampling resistor with a low resistance value and a high-precision filtering differential amplifying circuit to effectively inhibit the interference of common mode signals, improve the stability of received signals and increase the load quantity of slave nodes.
As shown in fig. 3, the filter amplifying circuit 9 includes a first filter amplifier U2A and a second filter amplifier U2B connected in series through a capacitor C5, one end of the capacitor C5 is connected to the output end of the first filter amplifier U2A, the other end is connected to the co-directional input end of the second filter amplifier U2B, and the first filter amplifier U2A receives the signal output by the front-stage filter differential amplifying circuit and amplifies the signal by the second filter amplifier U2B to output the signal to the signal output circuit; the signal output by the differential amplifying circuit is received by the same-direction input end of the first filter amplifier U2A through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the reverse input end of the first filter amplifier U2A is connected to a node between the output end of the first filter amplifier U2A and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, the reverse input end of the first filter amplifier U2A is grounded through a resistor R46, and the signals of the same-direction input end and the reverse input end are received by the output end of the first filter amplifier U2A and output to the second filter amplifier U2B through a capacitor C5; the output signal of a capacitor C5 is received by the same-direction input end of the second filter amplifier U2B through a resistor R16, a resistor R24 and a capacitor C18, the other ends of the resistor R24 and the capacitor C18 are grounded, the output end of the second filter amplifier U2B feeds back a signal to the reverse input end of the second filter amplifier U2B through a resistor R27 and a capacitor C6 which are connected in parallel, the reverse input end of the second filter amplifier U2B is grounded through a resistor R31, and the output end of the second filter amplifier U2B receives signals of the same-direction input end and the reverse input end and outputs the signals to a resistor R40 and a capacitor C15 of a signal output circuit. The circuit is amplified by multistage filtering, so that signal assignment is effectively improved, signal robustness is enhanced, and the load quantity of bus slave nodes is further increased.
As shown in fig. 3, the signal output circuit 10 includes a voltage comparator U1B, a comparison circuit and a signal undervoltage circuit, where an inverting input end of the voltage comparator U1B receives a signal output by an output end of the second filter amplifier U2B through a resistor R40 and a capacitor C15, the capacitor C15 is grounded through a resistor R44, the comparison circuit includes a resistor R26, a resistor R30 and a capacitor C8, the resistor R26 receives a voltage provided by a power VCC30A and outputs the voltage to the same directional input ends of the resistor R30 and the voltage comparator U1B, the same directional input end of the voltage comparator U1B is grounded through the capacitor C8, the other end of the resistor R30 is grounded, and the output end of the voltage comparator U1B outputs the signal to a host receiving end; the signal undervoltage circuit can provide bias voltage for signals and comprises a resistor R45, a resistor R47, a diode D2, a diode D4 and a capacitor C19 which are connected in series, wherein the resistor R45 and the resistor 47 receive voltage provided by a power supply VCC30A and are connected to the cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, the anode of the diode D4 is connected to a node between the capacitor C15 and the reverse input end of the voltage comparator, the cathode of the diode D2 is connected to the reverse input end of the voltage comparator, and the anode of the diode D2 is grounded.
As shown in fig. 3, the current detection circuit 8 is connected to the output end of the pre-stage filtering differential amplification circuit, the current detection circuit includes a comparator U1A and a detection circuit, the reverse input end of the comparator U1A receives an amplified signal of the pre-stage filtering differential amplification circuit through a resistor R4, the detection circuit includes a resistor R1, a resistor R2, a stabilizing tube D1 and a bypass capacitor C1, the resistors R1 and R2 receive a power VCC33 and transmit the power VCC33 to the same-direction input end of the comparator through the stabilizing tube D1 and the bypass capacitor C1, and the output end of the comparator outputs a signal to the host end through a resistor R3. The power supply detection circuit judges overload and short circuit of the amplified signal output by the pre-stage filtering amplified signal through the comparator U1A and the detection circuit, and detection cost is reduced.
The working principle of the invention is as follows: the power supply control circuit and the transmitting control circuit are provided with the capacity of driving loads with more than 3A of large current by adopting a direct current power supply, the signal output of the power supply control circuit is regulated through a voltage modulation circuit, the two-stage voltage output of the power supply control circuit is controlled to meet the two differential voltage modulation requirements of a bus, the adopted low-resistance sampling resistor receives the signals output by the transmitting control circuit and outputs the signals to a front-stage filtering differential amplifying circuit, the transmitting control circuit connected to the transmitting control circuit reduces the heating of the sampling resistor through a host signal, the signals are filtered and amplified through the front-stage filtering differential amplifying circuit, the amplified signals are output to a filtering amplifying circuit to enable the signals to be amplified through multistage filtering, and therefore signal assignment is improved, the signal robustness is enhanced, the node load quantity on the bus is further increased, the power supply detection circuit judges overload and short circuit of the currents output by the front-stage filtering amplifying signals through a comparator and a comparison circuit, the detection cost is reduced, the received signals are compared with a reference level through the voltage comparator arranged on the signal output circuit, and finally the amplified signals are transmitted to the host.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the scope of protection defined by the claims of the present invention without departing from the spirit of the present invention.
Claims (4)
1. The high-power MBUS master controller circuit comprises a host sending circuit and a host receiving circuit, and is characterized in that the host sending circuit comprises a direct-current power supply (1) and a sending control circuit (2) for receiving a host sending signal, the host receiving circuit comprises a sampling resistor (6) connected with the sending control circuit, a front-stage filtering differential amplifying circuit (7) for receiving a signal output by the sampling resistor and a signal output circuit (10), the direct-current power supply comprises a high-voltage rail power supply and a filtering circuit, the filtering circuit comprises a capacitor C11, a power magnetic bead FB1, a power magnetic bead FB2, a capacitor C2 and a bypass capacitor C3, the high-voltage rail power supply outputs to the power magnetic bead FB1 and the power magnetic bead FB2 which are connected in parallel through the capacitor C11, the other ends of the power magnetic bead FB1 and the power magnetic bead 2 are connected with the capacitor C2 and the bypass capacitor C3 which output voltages in parallel, and the other ends of the capacitor C11, the capacitor C2 and the power bypass capacitor C3 are grounded; the front-stage filtering differential amplifying circuit (7) comprises a front-stage filtering circuit and a differential amplifying circuit, wherein the front-stage filtering circuit comprises a first filtering circuit for receiving a high-level signal output by a sampling resistor, a second filtering circuit for receiving a low-level signal output by the sampling resistor and a capacitor C14 for connecting the first filtering circuit and the second filtering circuit, the first filtering circuit comprises a resistor R12, a capacitor C12 and a resistor R9, and the resistor R12 receives the high-level signal and outputs the high-level signal through the capacitor C12 and the resistor R9 which are connected in parallel; the second filter circuit comprises a resistor R21, a capacitor C16 and a resistor R23, wherein the resistor R21 receives a low-level signal and outputs the low-level signal through the capacitor C16 and the resistor R23 which are connected in parallel; the differential amplifying circuit comprises a resistor R11, a resistor R10, a resistor R20, a resistor R42, a capacitor C17 and an operational amplifier, wherein the resistor R11 receives output signals of the first filtering circuit and outputs the output signals to the resistor R10 and a third pin terminal (VIN+), the resistor R20 receives output signals of the second filtering circuit and outputs the output signals to a fourth pin terminal (VIN-), and the two ends of the resistor R42 and the capacitor C17 are respectively connected with a first pin terminal (OUT) and a fourth pin terminal (VIN-) of the operational amplifier after being connected in parallel;
The transmitting control circuit (2) comprises a resistor R18, a resistor R22, a triode Q2, a resistor R8, a resistor R6, a field effect transistor Q1, a resistor R28, a resistor R32, a triode Q3, a resistor R14, a diode D3, a resistor R29, a resistor R7, a triode Q4 and a diode D5, wherein a host signal is output to a base electrode of the triode Q2 through the resistor R22 by the resistor R18, an emitter electrode of the triode Q2 and the other end of the resistor R22 are grounded, a collector electrode of the triode Q2 is output to a grid electrode of the field effect transistor Q1 through the resistor R8, a drain electrode of the field effect transistor Q1 receives a power VCC33, the resistor R6 is connected with two ends of the grid electrode and the drain electrode of the field effect transistor Q1, and an original electrode of the field effect transistor Q1 is output to the self-recovery fuse F1 through a sampling resistor; the resistor R28 receives a host signal and outputs the host signal to the base electrode of the triode Q3 through the resistor R32, the emitter electrode of the triode Q3 and the other end of the resistor R32 are grounded, the collector electrode of the triode Q3 is respectively connected with the resistor R7 and the anode electrode of the diode D3 through the resistor R14, the other end of the resistor R7 is connected with the power VCC33, the cathode electrode of the diode D3 is respectively output to the base electrode of the triode Q4 and the resistor R29, the other end of the resistor R29 is respectively connected to the emitter electrode of the triode Q4 and the anode electrode of the diode D5, and the collector electrode of the triode Q4 is respectively connected with the cathode electrode of the diode D5 and the MBUSV-end of the sampling resistor to output to the self-recovery fuse F1;
the host sending circuit further comprises a power supply control circuit (4) which receives voltage output by a direct-current power supply and is connected with the sending control circuit, the power supply control circuit comprises an integrated control chip, a ninth pin (VIN) of the integrated control chip is connected with the direct-current power supply, a first pin (LX) of the integrated control chip is output to an anode of a diode D5 on the sending control circuit through a power inductor L1 and is output to an MBUS bus through a self-recovery fuse F1 through a cathode output end of the diode D5, the integrated control chip provides a low-level signal for the MBUS bus through the voltage output circuit, the voltage output circuit comprises a resistor R53 connected at a node between the diode D5 and the power inductor L1, a resistor R54 connected in series with the resistor R53, and a capacitor C35, the resistor R53 and the resistor R54 are output to a sixth pin end (FB) of the integrated control chip (U4), the sixth pin end (FB) is grounded through the capacitor C35, and the other end of the resistor R54 is grounded;
The host sending circuit further comprises a voltage modulation circuit (5) for adjusting the power supply control circuit, the voltage modulation circuit comprises a resistor R57, a triode Q8 and a resistor R56, a collector of the triode Q8 is output to a sixth pin end (FB) of the integrated control chip (U4) through the resistor R56, an emitter of the triode Q8 is grounded, a base of the triode Q8 is connected with the resistor R57, and the other end of the resistor R57 receives a differential pressure modulation signal capable of conducting the triode Q8;
The host sending circuit further comprises a receiving and sending control circuit (3) connected with the sampling resistor, the receiving and sending control circuit comprises a field effect transistor Q5, a resistor R15, a resistor R19, a field effect transistor Q6, a resistor R41 and a resistor R43, the resistor R41 receives a host signal MCU_Con and outputs the host signal MCU_Con to the grid electrodes of the resistor R43 and the field effect transistor Q6, the other end of the resistor R43 is grounded, the drain electrode of the field effect transistor Q6 is respectively connected with the grid electrode of the field effect transistor Q5 and the resistor R15 through the resistor R19, the source electrode of the field effect transistor Q6 is grounded, the drain electrode and the source electrode of the field effect transistor Q5 are respectively connected with the MBUSV + end and the MBUSV end of the sampling resistor, and the other end of the resistor R15 is connected with the drain electrode of the field effect transistor Q5;
The host receiving circuit further comprises a filter amplifying circuit (9), the filter amplifying circuit comprises a first filter amplifier (U2A) and a second filter amplifier (U2B) which are connected in series through a capacitor C5, the homodromous input end of the first filter amplifier (U2A) receives signals output by the front-stage filter differential amplifying circuit through a resistor R36, a capacitor C13 and a resistor R35 which are connected in series, the opposite input end of the first filter amplifier (U2A) is connected to a node between the output end of the first filter amplifier (U2A) and the capacitor C5 through a resistor R25 and a capacitor C7 which are connected in parallel, and the opposite input end of the first filter amplifier (U2A) is grounded through a resistor R46; the unidirectional input end of the second filter amplifier (U2B) receives an output signal output by the first filter amplifier (U2A) to the capacitor C5 through the resistor R16, the resistor R24 and the capacitor C18, the output end of the second filter amplifier (U2B) feeds back a signal to the reverse input end of the second filter amplifier (U2B) through the resistor R27 and the capacitor C6 which are connected in parallel, the reverse input end of the second filter amplifier (U2B) is grounded through the resistor R31, and the output end of the second filter amplifier (U2B) receives signals of the unidirectional input end and the reverse input end of the second filter amplifier (U2B) and outputs a signal control circuit;
The host receiving circuit further comprises a current detection circuit (8) connected with the output end of the pre-stage filtering differential amplification circuit, the current detection circuit comprises a comparator (U1A) and a detection circuit, the reverse input end of the comparator (U1A) receives an amplified signal of the pre-stage filtering differential amplification circuit through a resistor R4, the detection circuit comprises a resistor R1, a resistor R2, a stabilizing tube D1 and a bypass capacitor C1, the resistors R1 and R2 receive a power VCC33 and transmit the power VCC33 to the same-direction input end of the comparator through the stabilizing tube D1 and the bypass capacitor C1, and the output end of the comparator outputs the signal to the host end through a resistor R3.
2. The high power MBUS master circuit according to claim 1, characterized in that the sampling resistor (6) comprises a resistor R37, a resistor R38, a resistor R29, and a resistor R17 connected in parallel in sequence.
3. The high-power MBUS master circuit according to claim 1, characterized in that the signal output circuit (10) comprises a voltage comparator (U1B) and a comparison circuit, the inverting input end of the voltage comparator (U1B) receives the output signal of the pre-filtering differential amplifying circuit through a resistor R40 and a capacitor C15, the comparison circuit comprises a resistor R26 and a resistor R30 and a capacitor C8, the resistor R26 receives the voltage provided by the power VCC30A and is transmitted to the same-direction input end of the voltage comparator through the resistor R30 and the capacitor C8, the other end of the capacitor C8 is grounded, and the output end of the voltage comparator (U1B) outputs the signal to the host receiving end.
4. The high-power MBUS master circuit according to claim 1, characterized in that the signal output circuit further comprises a signal undervoltage circuit, the signal undervoltage circuit comprises a resistor R45 and a resistor R47 which are connected in series, a diode D2, a diode D4 and a capacitor C19, the resistor R45 and the resistor 47 receive the voltage provided by the power supply VCC30A and are connected to the cathode of the diode D4, the cathode of the diode D4 is grounded through the capacitor C19, the anode of the diode D4 is connected to the node between the capacitor C15 and the inverting input terminal of the voltage comparator (U1B), the cathode of the diode D2 is connected to the inverting input terminal of the voltage comparator (U1B), and the anode of the diode D2 is grounded.
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| CN108563279A (en) * | 2018-07-11 | 2018-09-21 | 重庆线易电子科技有限责任公司 | Filter circuit of pressure-stabilizing and signal deteching circuit |
| CN109302194B (en) * | 2018-11-29 | 2023-10-20 | 苏州东剑智能科技有限公司 | Mbus host receiving circuit |
| CN110784235B (en) * | 2019-12-04 | 2024-05-14 | 青岛东软载波科技股份有限公司 | M-BUS host receiving and transmitting circuit |
| CN111489542A (en) * | 2020-03-24 | 2020-08-04 | 宁波水表(集团)股份有限公司 | Receiving circuit of M-Bus instrument Bus |
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