JP2005210222A - Operational amplifier, active filter equipped with it, and data transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier capable of relaxing limitation on a frequency band of an active filter usable depending on the band, and to provide the active filter and a data transmission system. <P>SOLUTION: The operational amplifier comprises a common emitter differential amplifier circuit 11 including a first transistor Q11 and a second transistor Q12 having base terminals as a differential input and emitters connected commonly and delivering an output signal from the collector of the second transistor Q12, and an emitter earth amplification stage 12 being driven with the collector output from the common emitter differential amplifier circuit 11 wherein the emitter earth amplification stage 12 comprises a series circuit 121 of two capacitor elements C11 and C12 connected between the collector and base of a transistor Q15, and a resistor element R11 connected between the joint of the capacitor elements in the series circuit 121 and the ground potential. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an operational amplifier applied to, for example, a filter, an active filter including the operational amplifier, and a data transmission system.

  An active filter is a means for forming a filter on an integrated circuit (IC). Inductors cannot be formed on ICs, and capacitances and resistance elements are limited in element values or element accuracy is not so good, so various active filters using active circuits have been proposed (for example, Non-Patent Document 1).

Among them, a filter technique based on an integration circuit using an operational amplifier (hereinafter also referred to as an operational amplifier) is widely known.
There are many types of this method depending on the method of realizing the details, but generally speaking, various transfer functions can be flexibly realized, and in the low frequency region where the operational amplifier gain is sufficiently high, the theoretical characteristics are good. Match.
Active filter design <Electronic Science Series> 52, Sangyo Publishing, Ken Yanagisawa, Jun Kanemitsu

In the filter technology based on the integration circuit using an operational amplifier, the gain of the operational amplifier decreases as the frequency increases, and the deviation from the theoretical characteristics increases, eventually limiting the usable frequency band due to the operational amplifier frequency characteristics. There is a disadvantage that it ends up.
Hereinafter, this problem will be described using a specific circuit.

FIG. 1 is a diagram showing a second-order low-pass filter called a biquad type.
Any second-order transfer function can be realized by slightly changing this circuit or adding an addition / subtraction circuit. Any transfer function can be decomposed into a product of second order transfer functions.
If the denominator is an odd order, one is a first order transfer function. Therefore, if an arbitrary second-order transfer function can be realized, an arbitrary transfer function can be realized.

In FIG. 1, ωo / s indicates an integration circuit. k is a coefficient for determining Q. The integration circuit is realized as shown in FIG. 2 when an operational amplifier is used.
In FIG. 2, 1 is an operational amplifier. In the operational amplifier 1, the non-inverting phase input terminal (+) is grounded, the inverting phase input terminal (−) is connected to the input terminal Tin of the input signal Vin via the resistance element R1, and the output terminal and the inverting phase input terminal (− ) Is connected to the capacitor C1.
The transfer function T (s) of this integration circuit is as follows.

An actual operational amplifier itself has the characteristics of an integrator.
FIG. 3 shows an equivalent circuit when the characteristic of the operational amplifier is the integration characteristic of the band ωu. The transfer function of this circuit is obtained as follows.

Comparing this equation with the equation (1), it can be seen that setting the characteristic of the operational amplifier to the integral characteristic of the band ωu means that the integral coefficient is shifted by ωo / ωu and that a new pole is formed in ωu.
When such an integrator is used as an active filter, the phase is rotated excessively due to the influence of the newly generated pole, and generally, the Q of the second-order transfer function becomes higher than the original design value, and the frequency characteristic has a peak. Produce.
Therefore, the band of the operational amplifier determines the usable frequency range of the active filter.

As a specific example, the general band of the operational amplifier is 100 MHz. The higher the order of the filter, the higher the Q appears in the second order element when it is decomposed into a second order transfer function. Assuming that Q is 5, the gain of that stage is 5 at the cutoff frequency.
If the tolerance of deviation from the theoretical value of the transfer function at that stage is 5%, the approximate value of the cutoff frequency of the filter that can be realized is 100 MHz / 5 × 0.05 = 1 MHz.
If a higher cutoff frequency is to be realized, the calculation Q should be set low in advance in order to increase the allowable deviation from the theoretical value, widen the operational amplifier bandwidth, or allow for the influence of the operational amplifier bandwidth. It is necessary to do.
Designing a low Q in advance means that the characteristic variation increases when the band of the operational amplifier is different from the expected value.

  As a matter of fact, the order, filter configuration, low pass, high pass, or band pass will differ, but as a rough rule, an active filter using an operational amplifier up to 1 MHz band should be designed easily. Can do. However, when it exceeds 1 MHz, it becomes difficult gradually, and when it exceeds 10 MHz, it becomes very difficult.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an operational amplifier capable of relaxing the restriction on the frequency band of an active filter that can be used depending on the band, an active filter including the operational amplifier, and data. It is to provide a transmission system.

  In order to achieve the above object, an operational amplifier according to a first aspect of the present invention includes a first transistor and a second transistor each having a base (gate) terminal as a differential input and an emitter (source) connected in common. An emitter (source) common differential amplifier circuit having a transistor and supplying an output signal from the collector (drain) of the first transistor or the second transistor, and a collector of the emitter (source) common differential amplifier circuit An emitter (source) ground amplification stage driven by a (drain) output, and the emitter (source) ground amplification stage is connected between the collector (drain) and the base (gate). And at least one resistance element connected between a connection point between the capacitive elements of the series circuit and a ground potential.

  An operational amplifier according to a second aspect of the present invention includes a first transistor and a second transistor each having a base (gate) terminal as a differential input and an emitter (source) connected in common. An emitter (source) common differential that supplies a first output signal from a first collector (drain) of one transistor and supplies a second output signal from a second collector (drain) of the second transistor An amplifier circuit, a first emitter (source) grounded amplification stage driven by a first collector (drain) output of the emitter (source) common differential amplifier circuit, and an emitter (source) common differential amplifier circuit. A second emitter (source) ground amplification stage driven by a second collector (drain) output, the first emitter (source) ground amplification stage being a collector (drain) A first series circuit of at least two capacitive elements connected between the base and the base (gate), and at least one resistor connected between the connection point between the capacitive elements of the first series circuit and the ground potential And the second emitter (source) ground amplification stage includes a second series circuit of at least two capacitive elements connected between the collector (drain) and the base (gate), and the second And at least one resistance element connected between the connection point between the capacitive elements of the series circuit and the ground potential.

  An active filter according to a third aspect of the present invention includes an operational amplifier, a capacitive element connected between the output terminal of the operational amplifier and the inverted phase input of the operational amplifier, and an input supplied to the inverted phase input. The operational amplifier includes a first transistor and a second transistor, each having a base (gate) terminal as a differential input and an emitter (source) connected in common. An emitter (source) common differential amplifier for supplying an output signal from the collector (drain) of the first transistor or the second transistor, and a collector (drain) output of the emitter (source) common differential amplifier An emitter (source) grounded amplification stage driven by the emitter (source) grounded amplification stage, the collector (drain) and the base ( It has at least two series circuits of capacitive elements connected in over g) between at least the one resistive element connected between the connection point and the ground potential between the capacitance element of the series circuit.

  An active filter according to a fourth aspect of the present invention includes an operational amplifier, a capacitive element connected between an output terminal of the operational amplifier and an inverted phase input of the operational amplifier, and an input supplied to the inverted phase input. The operational amplifier includes a first transistor and a second transistor, each having a base (gate) terminal as a differential input and an emitter (source) connected in common. The first output signal is supplied from the first collector (drain) of the first transistor, and the second output signal is supplied from the second collector (drain) of the second transistor. A common differential amplifier circuit; a first emitter (source) ground amplifier stage driven by a first collector (drain) output of the emitter (source) common differential amplifier circuit; A first emitter (source) ground amplification stage driven by a second collector (drain) output of an emitter (source) common differential amplifier circuit, the first emitter (source) ground amplification stage Is connected between the first series circuit of at least two capacitive elements connected between the collector (drain) and the base (gate), and the connection point between the capacitive elements of the first series circuit and the ground potential. A second series circuit of at least two capacitive elements connected between a collector (drain) and a base (gate), and wherein the second emitter (source) ground amplification stage has at least one resistance element; And at least one resistance element connected between a connection point between the capacitive elements of the second series circuit and a ground potential.

  A data transmission system according to a fourth aspect of the present invention is a data transmission system for receiving modulated digital data by transmitting it through a predetermined medium, an active filter for extracting desired signal data from the received digital data, A demodulation circuit for demodulating the digital data extracted by the active filter, and the active filter includes an operational amplifier and a capacitor connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier The operational amplifier has a differential input at each base (gate) terminal and an emitter (source) connected in common. A first transistor and a second transistor, and a collection of the first transistor or the second transistor. An emitter (source) common differential amplifier circuit for supplying an output signal from the (drain), and an emitter (source) ground amplifier stage driven by a collector (drain) output of the emitter (source) common differential amplifier circuit; The emitter (source) ground amplification stage includes a series circuit of at least two capacitive elements connected between a collector (drain) and a base (gate), a connection point between the capacitive elements of the series circuit, and a ground potential. And at least one resistance element connected therebetween.

  A data transmission system according to a sixth aspect of the present invention is a data transmission system for receiving modulated digital data by transmitting a predetermined medium, and an active filter for extracting desired signal data from the received digital data; A demodulation circuit for demodulating the digital data extracted by the active filter, and the active filter includes an operational amplifier and a capacitor connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier The operational amplifier has a differential input at each base (gate) terminal and an emitter (source) connected in common. A first transistor and a second transistor, and a first collector (drain) of the first transistor An emitter (source) common differential amplifier circuit that supplies an output signal and supplies a second output signal from a second collector (drain) of the second transistor, and an emitter (source) common differential amplifier circuit. A first emitter (source) grounded amplification stage driven by a first collector (drain) output and a second collector (drain) output driven by a second collector (drain) output of the emitter (source) common differential amplifier circuit. And a first series of at least two capacitive elements connected between the collector (drain) and the base (gate). A second emitter (source) grounded amplifier having a circuit and at least one resistive element connected between a connection point between the capacitive elements of the first series circuit and a ground potential Is connected between the second series circuit of at least two capacitive elements connected between the collector (drain) and the base (gate), and the connection point between the capacitive elements of the second series circuit and the ground potential. And at least one resistance element.

According to the present invention, for example, in an active filter using an integrating circuit by an operational amplifier typified by a biquad type, the operating frequency is limited to a low frequency because it is limited to the band of the operational amplifier. 2 or higher order integral characteristics are added by a very simple method.
This increases the effective gain in the signal band of the filter without expanding the band of the operational amplifier.
As a result, since it is not necessary to realize an active filter at a higher frequency or to extend the band of the operational amplifier, an active filter with lower power can be realized.

  According to the present invention, there is an advantage that it is possible to relax the restriction on the frequency band of the active filter that can be used depending on the band of the operational amplifier.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 4 is a circuit diagram showing a first embodiment of an operational amplifier (operational amplifier) according to the present invention.

  The operational amplifier 10 shown in FIG. 4 has a differential amplifier circuit 11, a grounded emitter amplifier circuit (stage) 12, an emitter follower circuit 13 as an output stage, differential input terminals TVi + and TVi−, and an output terminal TVo as main components. doing.

  The differential amplifier circuit 11 includes a pnp transistor Q11 as a first transistor, a pnp transistor Q12 as a second transistor, npn transistors Q13 and Q14, and a current source I11.

In the differential amplifier circuit 11, the base of the transistor Q11 is connected to the differential input terminal TVi−, the base of the transistor Q12 is connected to the differential input terminal TVi +, and the emitters of the transistors Q11 and Q12 are connected in common. A connection point between the emitters is connected to a current source I11 connected to a supply line of the power supply voltage Vcc.
The collector of transistor Q11 is connected to the collector and base of transistor Q13 and the base of transistor Q14, and the collector of transistor Q12 is connected to the collector of transistor Q14. The emitters of the transistors Q13 and Q14 are connected to a reference potential (ground potential) Vee.

  In the differential amplifier circuit 11 thus configured, the emitter common differential amplifier 111 is configured by the transistors Q11 and Q12, the current mirror circuit 112 is configured by the transistors Q13 and Q14, and the collector of the transistor Q12 (the collector of the transistor Q14). The output signal is supplied to the grounded-emitter amplifier circuit 12 at the next stage.

  The grounded-emitter amplifier circuit 12 has an npn transistor Q15 driven by the collector output of the differential amplifier circuit 11, a current source I12, a series circuit 121 of two capacitors C11 and C12 as mirror compensation capacitors, and a resistor element R11. ing.

In the grounded emitter amplifier circuit 12, the base of the transistor Q15 is connected to the collector of the transistor Q12 of the differential amplifier circuit 11, the emitter is connected to the reference potential (ground potential) Vee, and the collector is connected to the supply line of the power supply voltage Vcc. Connected to the current source I12.
Series circuit 121 is connected between the collector and base of transistor Q15. Specifically, the first electrode of the capacitor C11 is connected to the collector of the transistor Q15, the second electrode of the capacitor C11 is connected to the first electrode of the capacitor C12, and the second electrode of the capacitor C12 is connected to the base of the transistor Q15. Has been.
One end of the resistance element R11 is connected to a connection point between the capacitors C11 and C12 of the series circuit 121, that is, a connection point between the second electrode of the capacitor C11 and the first electrode of the capacitor C12, and the other end is connected to a reference potential (grounding). Potential) Vee.

  The emitter follower circuit 13 as an output buffer has an npn transistor Q16 and a current source I13.

  The current source I13 and the output terminal are connected to the collector of the transistor Q15 of the grounded-emitter amplifier circuit 12, the collector is connected to the supply line of the power supply voltage Vcc, and the emitter is connected to the reference potential (ground potential) Vee. Connected to TVo.

  In the operational amplifier 10 having such a configuration, the output of the common emitter differential amplifier 111 composed of the transistors Q11 and Q12 is received by the current mirror circuit 112 composed of the transistors Q13 and Q14, and the transistor Q15 of the next-stage emitter grounded circuit 12 is received. Further, the output Vo is taken out by the emitter follower circuit 13 at the final stage.

In the operational amplifier 10 according to this embodiment, a mirror compensation capacitor including two series capacitors C11 and C12 is connected from the collector output of the transistor Q15 of the grounded emitter amplifier circuit 12 to the base input. Further, the connection point between the capacitors C11 and C12 is grounded via the resistance element R11.
The Miller compensation capacitor maintains an integral characteristic (transfer function is 1 / s and phase is −π / 2) over a wide frequency range in the grounded emitter stage, and keeps the negative feedback path stable.

FIG. 5 is a diagram showing a general mirror compensation circuit stage.
The transfer function of the circuit of FIG. 5 when the transfer conductance Gm is sufficiently large is given by the following equation.

FIG. 6 is a diagram showing an amplitude response characteristic with respect to the frequency of the circuit of FIG.
As is well known, the amplitude response of the circuit of FIG. 5 is inversely proportional to frequency, as shown in FIG.

FIG. 7 is a diagram showing a phase response characteristic with respect to the frequency of the circuit of FIG.
In FIG. 7, (a) shows the phase response characteristic in the ideal case where the DC gain is infinite, and the curve shown in (b) shows the phase response characteristic when the DC gain is finite.
As shown in FIG. 7, the phase is always −π / 2 above a certain frequency. Since the output of the operational amplifier is inverted with respect to the input, the phase of the output with respect to the input is exactly −2 / 3π, but the phase is based on DC with a finite gain.
A general operational amplifier ensures a phase margin / gain margin by such characteristics and keeps the negative feedback circuit stable.

Next, the transfer function and the amplitude / phase response in the operational amplifier according to the present embodiment will be described.
FIG. 8 is a diagram showing an equivalent circuit of the mirror compensation circuit stage in the operational amplifier according to the present embodiment.
When the transfer function of the equivalent circuit of FIG. 8 is obtained assuming that the transfer conductance Gm is sufficiently large, it is expressed by the following equation.

  As is apparent from this equation, a term giving zero surrounded by {} is generated instead of a simple integral characteristic.

FIG. 9 is a diagram showing an amplitude response characteristic with respect to the frequency of the circuit of FIG.
In FIG. 9, ωz indicating zero is determined from the sum of the capacitance values C1 and C2 of the capacitors C11 and C12 and the resistance value R of the resistance element R11, as is apparent from the equation (4).
As shown in FIG. 9, at a frequency higher than ωz, the circuit of FIG. 8 shows a first order response, and at a frequency lower than ωz, a second order response.

FIG. 10 is a diagram showing a phase response characteristic with respect to the frequency of the circuit of FIG.
In FIG. 9, (a) shows the phase response characteristic in the ideal case where the gain of DC is infinite, and the curve shown in (b) shows the phase response characteristic when the DC gain is finite.
As shown in FIG. 9, the phase is in the vicinity of −π in the signal band, and returns to −π / 2 at high frequencies. This is to ensure a phase margin for negative feedback.
It has been clarified that if there is a phase margin at a frequency where the gain is a unit gain, the loop is stable even if the gain is asymptotic to or exceeds -π at a frequency greater than 1, so the phase of the signal band There is no problem with the behavior.

  FIG. 11 is a circuit diagram showing a second embodiment of an operational amplifier (operational amplifier) according to the present invention.

  The operational amplifier 20 of FIG. 11 has a differential amplifier circuit 21, a source grounded amplifier circuit (stage) 22, differential input terminals TVi +, TVi−, and an output terminal TVo as main components.

  The differential amplifier circuit 21 includes a p-channel MOS (PMOS) transistor Q21 as a first transistor, a PMOS transistor Q22 as a second transistor, n-channel MOS (NMOS) transistors Q23 and Q24, and a current source I21. ing.

  In the differential amplifier circuit 21, a common source differential amplifier 211 is configured by the transistors Q21 and Q22, a current mirror circuit 212 is configured by the transistors Q23 and Q24, and the drain of the transistor Q22 (a connection point with the drain of the transistor Q24). The output signal is supplied to the common source amplifier circuit 22 in the next stage.

  The common source amplifier circuit 22 includes an NMOS transistor Q25 driven by the drain output of the differential amplifier circuit 21, a current source I22, a series circuit 221 of two capacitors C21 and C22 as mirror compensation capacitors, and resistance elements R21 and R22. Have.

The operational amplifier 20 according to the second embodiment is basically different from the operational amplifier 10 of FIG. 4 in that an output buffer is not provided, and PMOS transistors Q21 and Q22 are applied instead of the pnp transistors Q11 and Q12, and npn NMOS transistors Q23 to Q25 are applied instead of the transistors Q13 to Q15.
Accordingly, the base of the description related to FIG. 4 is replaced with the gate, the emitter is replaced with the source, the collector is replaced with the drain, and the basic functions and connection relationships are the same as in FIG. Is omitted.

  Note that the output buffer is omitted in the second embodiment. Therefore, it is disadvantageous in terms of gain and load driving capability, or has a small loss of output amplitude, and is suitable for low voltage operation. Although there is no fundamental difference between MOS and bipolar, MOS has a considerably low transfer conductance Gm for the same operating current.

  In the equivalent circuit of the mirror compensation circuit of FIG. 5, when the transfer conductance Gm is solved as a finite value, a positive zero is generated. Bipolar with a large transfer conductance Gm is not a problem because the zero frequency is reasonably high, but it is a problem with a MOS having a small Gm. The resistor element R22 placed in series with the mirror capacitor, that is, the resistor element R22 inserted between the first electrode of the capacitor C21 of the series circuit 211 and the drain of the NMOS transistor Q25 is a resistor element for canceling the zero. When the resistance value R2 of the resistance element R22 is 1 / Gm, zero is canceled out.

  FIG. 12 is a circuit diagram showing a third embodiment of an operational amplifier (operational amplifier) according to the present invention.

  The operational amplifier 30 of FIG. 12 includes a differential amplifier circuit 31, a first grounded emitter amplifier circuit (stage) 32, a first emitter follower circuit 33 as a differential output stage, and a second grounded emitter amplifier circuit (stage) 34. A second emitter follower circuit 35 as a differential output stage, an in-phase feedback circuit 36, differential input terminals TVi + and TVi−, and differential output terminals TVo + and TVo− are included as main components.

  The differential amplifier circuit 31 includes a pnp transistor Q31 as a second transistor, a pnp transistor Q32 as a first transistor, npn transistors Q33 and Q34, and a current source I31.

In the differential amplifier circuit 31, the base of the transistor Q31 is connected to the differential input terminal TVi−, the base of the transistor Q32 is connected to the differential input terminal TVi +, and the emitters of the transistors Q31 and Q32 are connected in common. The connection point between the emitters is connected to a current source I31 connected to the supply line of the power supply voltage Vcc.
The collector of transistor Q31 is connected to the collector of transistor Q33, and the collector of transistor Q32 is connected to the collector of transistor Q34. The bases of the transistors Q33 and Q34 are connected in common to the output of the common-mode feedback circuit 35, and the emitters of both are connected to a reference potential (ground potential) Vee.

  In the differential amplifier circuit 31 configured as described above, the emitter common differential amplifier 311 is configured by the transistors Q31 and Q12, the current source 312 is configured by the transistors Q13 and Q14, the collector of the transistor Q32 (the collector of the transistor Q34 and the collector of the transistor Q34) The output signal is supplied to the first-grounded-emitter amplifier circuit 32 in the next stage.

  The first grounded-emitter amplifier circuit 32 is driven by the first collector output of the first transistor Q32 of the differential amplifier circuit 31. The npn transistor Q35, the npn transistor Q36, the current source I32, and two mirror compensation capacitors A first series circuit 321 of capacitors C31 and C32 and resistance elements R31 and R32 are provided.

In the first grounded-emitter amplifier circuit 32, the base of the transistor Q35 is connected to the collector of the transistor Q32 of the differential amplifier circuit 31, the emitter is connected to one end of the resistor element R32 and the base of the transistor Q36, and the collector is the power supply voltage Vcc. Connected to a current source I32 connected to the supply line. The emitter of the transistor Q36 and the other end of the resistor element R32 are connected to the reference potential (ground potential) Vee, and the collector of the transistor Q36 is connected to the connection point between the collector of the transistor Q35 and the current source I32.
Series circuit 321 is connected between the collector and base of transistor Q35. Specifically, the first electrode of the capacitor C31 is connected to the collector of the transistor Q35, the second electrode of the capacitor C31 is connected to the first electrode of the capacitor C32, and the second electrode of the capacitor C32 is connected to the base of the transistor Q35. Has been.
One end of the resistor element R31 is connected to a connection point between the capacitors C31 and C32 of the series circuit 321, that is, a connection point between the second electrode of the capacitor C31 and the first electrode of the capacitor C32, and the other end is connected to a reference potential (grounding). Potential) Vee.

  The emitter follower circuit 33 as an output buffer includes an npn transistor Q37 and a current source I33.

  A current in which the base of the transistor Q36 is connected to the collectors of the transistors Q35 and Q36 of the first grounded-emitter amplifier circuit 32, the collector is connected to the supply line of the power supply voltage Vcc, and the emitter is connected to the reference potential (ground potential) Vee. Connected to source I33, output terminal TVo +, and common-mode feedback circuit 36.

  The second grounded emitter amplifier circuit 34 is driven by the second collector output of the second transistor Q32 of the differential amplifier circuit 31. The npn transistor Q38, the npn transistor Q39, the current source I34, and two mirror compensation capacitors A second series circuit 341 of capacitors C33 and C34 and resistance elements R33 and R34 are provided.

In the second grounded-emitter amplifier circuit 34, the base of the transistor Q38 is connected to the collector of the transistor Q31 of the differential amplifier circuit 31, the emitter is connected to one end of the resistor element R34 and the base of the transistor Q39, and the collector is the power supply voltage Vcc. Connected to a current source I34 connected to the supply line. The emitter of the transistor Q39 and the other end of the resistor element R34 are connected to the reference potential (ground potential) Vee, and the collector of the transistor Q39 is connected to the connection point between the collector of the transistor Q38 and the current source I34.
Series circuit 341 is connected between the collector and base of transistor Q38. Specifically, the first electrode of the capacitor C33 is connected to the collector of the transistor Q38, the second electrode of the capacitor C33 is connected to the first electrode of the capacitor C34, and the second electrode of the capacitor C34 is connected to the base of the transistor Q38. Has been.
One end of the resistor element R33 is connected to a connection point between the capacitors C33 and C34 of the series circuit 341, that is, a connection point between the second electrode of the capacitor C33 and the first electrode of the capacitor C34, and the other end is connected to a reference potential (grounding). Potential) Vee.

  The emitter follower circuit 35 as an output buffer includes an npn transistor Q40 and a current source I35.

  A current having the base of the transistor Q40 connected to the collectors of the transistors Q38 and Q39 of the second grounded emitter amplifier circuit 34, the collector connected to the supply line of the power supply voltage Vcc, and the emitter connected to the reference potential (ground potential) Vee Connected to source I35, output terminal TVo-, and common-mode feedback circuit 36.

The operational amplifier 30 having the above configuration has a differential input differential output configuration, whereas the operational amplifier 10 of FIG. 4 has a differential input single output configuration.
It is often required to implement an active filter as a fully differential circuit in order to reduce the dynamic range due to a lower power supply voltage, or to increase the resistance to digital noise when integrated with a digital circuit. . This embodiment is suitable for such applications.
The operational amplifier 30 in FIG. 12 has Darlington connection of the emitter follower stages in the first and second common-emitter amplifier circuits 32 and 34 (Q35 and Q36, and Q38 and Q39). As a result, the DC gain is significantly increased, and the characteristics are closer to ideal.

  FIG. 13 is a circuit diagram showing a fourth embodiment of an operational amplifier (operational amplifier) according to the present invention.

  The operational amplifier 40 of FIG. 13 includes a differential amplifier circuit 41, a first grounded emitter amplifier circuit (stage) 42, a second grounded emitter amplifier circuit (stage) 43, an in-phase feedback circuit 44, and differential input terminals TVi + and TVi−. , And differential output terminals TVo + and TVo- as main components.

  The differential amplifier circuit 41 includes a PMOS transistor Q41 as a second transistor, a PMOS transistor Q42 as a first transistor, NMOS transistors Q43 and Q44, and a current source I41.

  In the differential amplifier circuit 41, the transistors Q41 and Q42 form a common source differential amplifier 411, the transistors Q43 and Q44 form a current source 412, and an output signal is output from the first drain of the transistor Q42 to the first stage of the next stage. And the output signal is supplied from the second drain of the transistor Q41 to the second-source-grounded amplifier circuit 43 in the next stage.

  The first common-source amplifier circuit 42 is a first series circuit of an NMOS transistor Q45 driven by the first drain output of the differential amplifier circuit 41, a current source I42, and two capacitors C41 and C42 serving as mirror compensation capacitors. 421 and resistance elements R41 and R42.

  The second common-source amplifier circuit 43 is a second series circuit of an NMOS transistor Q45 driven by the second drain output of the differential amplifier circuit 41, a current source I43, and two capacitors C43 and C44 as mirror compensation capacitors. 431 and resistance elements R43 and R44.

The operational amplifier 40 according to the fourth embodiment is basically different from the operational amplifier 30 of FIG. 12 in that an output buffer is not provided, and PMOS transistors Q41 and Q42 are applied instead of the pnp transistors Q31 and Q32, and npn NMOS transistors Q43 to Q46 are applied instead of the transistors Q33 to Q35 and Q38.
Accordingly, the base of the description related to FIG. 12 is replaced with the gate, the emitter is replaced with the source, the collector is replaced with the drain, and the basic functions and connection relationships are the same as those in FIG. Is omitted.

  Note that the output buffer is omitted in the fourth embodiment. Therefore, it is disadvantageous in terms of gain and load driving capability, or has a small loss of output amplitude, and is suitable for low voltage operation. Although there is no fundamental difference between MOS and bipolar, MOS has a considerably low transfer conductance Gm for the same operating current.

  In the equivalent circuit of the mirror compensation circuit of FIG. 5, when the transfer conductance Gm is solved as a finite value, a positive zero is generated. Bipolar with a large transfer conductance Gm is not a problem because the zero frequency is reasonably high, but it is a problem with a MOS having a small Gm. A resistor element R42 placed in series with the mirror capacitor, that is, R42 inserted between the first electrode of the capacitor C41 of the series circuit 421 and the drain of the NMOS transistor Q45, and the first electrode of the capacitor C43 of the series circuit 431 R44 inserted between the drain of the NMOS transistor Q46 is a resistance element for canceling the zero. Zero is canceled when the resistance values R2 and R4 of the resistance elements R42 and R44 are 1 / Gm.

The operational amplifiers 10 to 40 according to the first to fourth embodiments have been described above.
Hereinafter, these operational amplifiers 10 to 40 will be considered.

FIG. 14 is a diagram for explaining the effect of the operational amplifier according to the present embodiment, and shows the gain characteristics of the operational amplifier as a whole.
In FIG. 14, ωu is a unit gain angular frequency (band), ωz is a zero angular frequency generated by the mirror compensation circuit of this embodiment, and ωo is a characteristic angular frequency of an active filter realized using this operational amplifier.
The zero angular frequency ωz is set lower than ωu in order to ensure a phase margin at the unity gain angular frequency ωu. Theoretically, a phase margin of π / 4 remains when ωz = ωu, but the phase margin is actually small due to the influence of other non-ideal poles, so choosing ωz = ωu is realistic. Not.

In an operational amplifier having a normal first-order mirror compensation circuit to which the present invention is not applied, the gain A1 at the cutoff frequency of the active filter is ωu / ωo.
Therefore, the required gain A1 is determined from the allowable error and the Q of the filter, and it must be used at a low filter cut-off frequency ωo that satisfies it or an operational amplifier with a high ωu must be used.
On the other hand, according to the present invention, the gain A2 at ωo takes a large value by multiplying the ratio of ωu / ωo by the ratio of ωz / ωo. In other words, an active filter can be realized up to a higher frequency using the same ωu operational amplifier, and a lower ωu operational amplifier can be used for the same ωo.
The bandwidth ωu that can be realized with an operational amplifier is determined by the device used, mainly the cutoff frequency of the transistor and parasitic capacitance. If you try to achieve a critically high value, the current consumption will increase dramatically, or the DC characteristics (gain, offset) Causes inconvenience such as deterioration.

Another advantage of the present invention will be described.
FIG. 15 shows a state where an operational amplifier in the band ωu is used as an integrator. FIG. 16 is a vector diagram of FIG.

Since the gain of the operational amplifier is finite, the input error voltage Ve cannot be ignored. The error voltage Ve is a signal delayed by π / 2 with respect to the output Vo. On the other hand, the voltage Vc at the capacitor C end is a vector sum of Ve and Vo, and advances by θ from Vo due to the finite Ve. Since the input current Iin flows through the capacitor C, it advances by π / 2 with respect to Vc.
As a result, the relationship between Iin and Vo that should be in the relationship of π / 2 is shifted by θ. This extra phase generally produces an effect similar to increasing the Q of the secondary transfer function.
According to the present invention, the transfer characteristic of the operational amplifier is second order and close to 1 / s2. Its phase is asymptotic to π, not π / 2.

How the phase characteristic affects the characteristic as an integrator will be described.
FIG. 17 shows a state assuming that the filter band approximately used by the operational amplifier has a second-order integral characteristic 1 / s2. FIG. 18 is a vector diagram of FIG.

In this case, the error voltage Ve is in phase with the output Vo. Therefore, Vc, which is the vector sum of Vo and Ve, is in phase with Vo.
As a result, the input voltages Iin and Vo maintain the correct phase relationship, and the error due to the finite gain is only the error of the gain factor of the integrator.

  Thus, it can be said that the characteristics of the operational amplifier of the present invention are more preferable for the active filter in terms of phase.

FIG. 19 is a circuit diagram showing a fifth embodiment of the operational amplifier according to this embodiment.
The operational amplifier 10A in FIG. 19 is different from the operational amplifier 10 in FIG. 4 in that the mirror compensation is performed in the third order instead of the second order in the grounded emitter amplifier circuit 12A.

Therefore, in the grounded emitter amplifier circuit 12A, the series circuit 121A is a series circuit of three capacitors C11, C12, and C13.
Series circuit 121A is connected between the collector and base of transistor Q15. Specifically, the first electrode of the capacitor C11 is connected to the collector of the transistor Q15, the second electrode of the capacitor C11 is connected to the first electrode of the capacitor C12, and the second electrode of the capacitor C12 is connected to the first electrode of the capacitor C13. The second electrode of the capacitor C13 is connected to the base of the transistor Q15.
One end of the resistance element R11 is connected to a connection point between the capacitors C11 and C12 of the series circuit 121A, that is, a connection point between the second electrode of the capacitor C11 and the first electrode of the capacitor C12, and the other end is connected to a reference potential (grounding). Potential) Vee. Furthermore, one end of the resistance element R12 is connected to the connection point between the capacitors C12 and C13 of the series circuit 121A, that is, the connection point between the second electrode of the capacitor C12 and the first electrode of the capacitor C13, and the other end is connected to the reference potential (grounding). Potential) Vee.

  The second-order mirror compensation is only asymptotic to π and not π. From the viewpoint of this phase, for example, as shown in FIG. 19, it is possible to perform a third order mirror compensation and design so as to pass π in the vicinity of the characteristic frequency of the filter.

This phase effect is obtained only when current is input through the transfer conductance circuit Gm as shown in FIG.
As shown in FIG. 2, Iin and Vo are correctly maintained in the relationship of π / 2 when a resistance is input. However, since the in-phase property of the input voltage Vin and the current Iin is lost due to the influence of the error voltage Ve, the effect of the phase characteristic is obtained. I can't.

That is, FIG. 20 shows a basic configuration of an active filter suitable for application of the operational amplifier according to this embodiment.
As shown in FIG. 20, the active filter 100 according to the present invention includes an operational amplifier 101, a capacitor 102 (C) connected between the output terminal of the operational amplifier 101 and its inverted phase input (−), and an inverted phase input. The integration circuit 103 based on the input current supplied to is used as a basic component.
The operational amplifiers 10, 10 </ b> A, and 20 to 40 according to the present embodiment described above are applied to the operational amplifier 101.

As described above, according to the present invention, in an active filter using an integrating circuit using an operational amplifier typified by a biquad type, the operating frequency is limited to a low frequency because it is limited to the band of the operational amplifier. By adding a second-order or higher-order integral characteristic by a very simple method, the effective gain in the signal band of the filter can be increased without expanding the band of the operational amplifier, and at higher frequencies. Since it is not necessary to realize an active filter or extend the band of the operational amplifier, it is possible to provide a suitable means for realizing an active filter with lower power.
In addition, it is limited to the case where the input is only the current input via the transfer conductance circuit, but it becomes a phase delay of π instead of the conventional phase delay of π / 2, which can also be used effectively for high accuracy. .

  The active filter according to the present embodiment can be applied to a digital data transmission system such as audio.

  FIG. 21 is a block diagram illustrating a configuration example of a digital optical space transmission system to which the active filter according to the present embodiment is applied.

The digital optical space transmission system 200 receives digital audio data from a transmission unit 210 included in a digital audio device 201 such as a CD player using infrared IR, for example, included in a cordless (wireless) speaker 202 or a cordless (wireless) headphone 203. Delivered by unit 220.
Then, the active filter 100 according to the present embodiment is applied as the band pass filter (BPF) 221 of the receiving unit 220.

Specifically, the transmission unit 210 includes an audio analog-digital converter (ADC) 211 so as to correspond to a digital / analog signal, and is digitally modulated by the digital modulation processing circuit 212 and transmitted by the LED driver 213. .
In the receiving unit 220, the desired signal and the interference signal are separated through the AGC 223 and the BPF 221, received by the photodiode 222, digitally demodulated by the digital demodulation processing circuit 224, and output as audio through the audio digital-analog converter (DAC) 225.

  As described above, the digital optical space transmission system 200 in FIG. 21 is a system that transfers audio signals wirelessly and does not require rear speaker wiring. Moreover, since the transmission signal amplitude is inversely proportional to the square of the distance, a wide dynamic range and high S / N are realized, and an active filter using an operational amplifier having an effect as described above is employed. Good reception and filtering processing is realized.

It is a figure which shows the 2nd order low-pass filter called a biquad type | mold. It is a figure which shows the implementation example of the integration circuit using an operational amplifier. It is a figure which shows the equivalent circuit when the characteristic of an operational amplifier is made into the integral characteristic of zone | band (omega) u. 1 is a circuit diagram showing a first embodiment of an operational amplifier (operational amplifier) according to the present invention. It is a figure which shows a general mirror compensation circuit stage. It is a figure which shows the amplitude response characteristic with respect to the frequency of the circuit of FIG. It is a figure which shows the phase response characteristic with respect to the frequency of the circuit of FIG. It is a figure which shows the equivalent circuit of the mirror compensation circuit stage in the operational amplifier which concerns on this embodiment. It is a figure which shows the amplitude response characteristic with respect to the frequency of the circuit of FIG. It is a figure which shows the phase response characteristic with respect to the frequency of the circuit of FIG. It is a circuit diagram which shows 2nd Embodiment of the operational amplifier (operational amplifier) which concerns on this invention. It is a circuit diagram which shows 3rd Embodiment of the operational amplifier (operational amplifier) which concerns on this invention. It is a circuit diagram which shows 4th Embodiment of the operational amplifier (operational amplifier) which concerns on this invention. It is a figure for demonstrating the effect of the operational amplifier which concerns on this embodiment, and has shown the gain characteristic as the whole operational amplifier. It is a figure which shows the state which used the operational amplifier of the band (omega) u as an integrator. FIG. 16 is a vector diagram of FIG. 15. It is a figure which shows the state assumed that it has the characteristic of the 2nd-order integral characteristic 1 / s2 in the filter zone | band which an operational amplifier uses approximately. FIG. 18 is a vector diagram of FIG. 17. It is a circuit diagram which shows 5th Embodiment of the operational amplifier (operational amplifier) which concerns on this embodiment. It is a figure which shows the basic composition of an active filter suitable by applying the operational amplifier which concerns on this embodiment. It is a block diagram which shows the structural example of the digital optical space transmission system to which the active filter which concerns on this embodiment is applied.

Explanation of symbols

10, 10A, 20 ... operational amplifier, 11, 21 ... differential amplifier circuit, 12, 12A, 22 ... grounded emitter amplifier circuit (stage), Q11, Q21 ... first transistor, Q12, Q22 ... second transistor, Q15 , Q25 ... Common emitter / source amplification transistor, C11 to C13, C21, C22 ... Capacitor, R11, R12, R21, R22 ... Resistance element, 121, 121A, 221 ... Series circuit, 30, 40 ... Op-amp, 31, 41 ... Differential amplifier circuit, 32, 42... First emitter / source grounded amplifier circuit (stage), 34, 43... Second emitter / source grounded amplifier circuit (stage), Q31, Q41. Q42 ... first transistor, Q35, Q38, Q45, Q46 ... grounded emitter amplifier transistor, C31 to C34, C4 C44: capacitor, R31 to R34, R41 to R44 ... resistance element, 321, 341, 421, 431 ... series circuit, 100 ... active filter, 101 ... operational amplifier, 102 (C) capacitor, 103 ... integration circuit, 200 ... digital Optical space transmission system, 201 ... audio equipment, 202 ... cordless (wireless) speaker, 203 ... cordless (wireless) headphones, 210 ... transmission unit, 211 ... analog-to-digital converter (ADC) for audio, 212 ... digital modulation processing circuit, 213 DESCRIPTION OF SYMBOLS ... LED driver, 220 ... Reception part, 221 ... BPF, 222 ... Photodiode, 223 ... AGC, 224 ... Digital demodulation processing circuit, 225 ... Digital-to-analog converter (DAC) for audio.

Claims (15)

Each emitter having a base terminal as a differential input and having a first transistor and a second transistor whose emitters are commonly connected, and supplying an output signal from the collector of the first transistor or the second transistor A common differential amplifier circuit;
A common-emitter amplifier stage driven by the collector output of the common emitter differential amplifier circuit,
The grounded-emitter amplifier stage is
A series circuit of at least two capacitive elements connected between the collector and the base;
An operational amplifier comprising: a connection point between the capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. A source having a first transistor and a second transistor each having a differential input as a gate terminal and a source connected in common, and supplying an output signal from the drain of the first transistor or the second transistor A common differential amplifier circuit;
A common-source amplifier stage driven by the drain output of the common source differential amplifier circuit;
The grounded source amplification stage is
A series circuit of at least two capacitive elements connected between the drain and the gate;
An operational amplifier comprising: a connection point between the capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. The source-grounded amplification stage includes a resistance element connected between the series circuit and the drain.
The operational amplifier according to claim 2, further comprising: Each of the base terminals has a differential input and a first transistor and a second transistor whose emitters are commonly connected, and a first output signal is supplied from a first collector of the first transistor, An emitter-common differential amplifier circuit for supplying a second output signal from a second collector of the second transistor;
A first grounded-emitter amplifier stage driven by a first collector output of the common emitter differential amplifier circuit;
A second grounded-emitter amplifier stage driven by a second collector output of the common emitter differential amplifier circuit;
The first grounded-emitter amplification stage includes:
A first series circuit of at least two capacitive elements connected between the collector and the base;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second grounded-emitter amplification stage is:
A second series circuit of at least two capacitive elements connected between the collector and the base;
An operational amplifier comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential. The operational amplifier according to claim 4, wherein each of the first and second grounded-emitter amplifier stages includes a Darlington-connected emitter follower stage. Each gate terminal has a first transistor and a second transistor, each having a differential input and a source connected in common, and a first output signal is supplied from a first drain of the first transistor, A common source differential amplifier circuit for supplying a second output signal from a second drain of the second transistor;
A first source grounded amplification stage driven by a first drain output of the common source differential amplifier circuit;
A second common-source amplifier stage driven by a second drain output of the common source differential amplifier circuit;
The first grounded source amplification stage includes:
A first series circuit of at least two capacitive elements connected between the drain and the gate;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second source grounded amplification stage is:
A second series circuit of at least two capacitive elements connected between the drain and the gate;
An operational amplifier comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential. Each of the first and second common-source amplification stages includes a resistance element connected between the series circuit and the drain.
The operational amplifier according to claim 6, further comprising: An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each emitter having a base terminal as a differential input and having a first transistor and a second transistor whose emitters are commonly connected, and supplying an output signal from the collector of the first transistor or the second transistor A common differential amplifier circuit;
A common-emitter amplifier stage driven by the collector output of the common emitter differential amplifier circuit,
The grounded-emitter amplifier stage is
A series circuit of at least two capacitive elements connected between the collector and the base;
An active filter comprising: a connection point between capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
A source having a first transistor and a second transistor each having a differential input as a gate terminal and a source connected in common, and supplying an output signal from the drain of the first transistor or the second transistor A common differential amplifier circuit;
A common-source amplifier stage driven by the drain output of the common source differential amplifier circuit;
The grounded source amplification stage is
A series circuit of at least two capacitive elements connected between the drain and the gate;
An active filter comprising: a connection point between capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each of the base terminals has a differential input and a first transistor and a second transistor whose emitters are commonly connected, and a first output signal is supplied from a first collector of the first transistor, An emitter-common differential amplifier circuit for supplying a second output signal from a second collector of the second transistor;
A first grounded-emitter amplifier stage driven by a first collector output of the common emitter differential amplifier circuit;
A second grounded-emitter amplifier stage driven by a second collector output of the common emitter differential amplifier circuit;
The first grounded-emitter amplification stage includes:
A first series circuit of at least two capacitive elements connected between the collector and the base;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second grounded-emitter amplification stage is:
A second series circuit of at least two capacitive elements connected between the collector and the base;
An active filter comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential. An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each gate terminal has a first transistor and a second transistor, each having a differential input and a source connected in common, and a first output signal is supplied from a first drain of the first transistor, A common source differential amplifier circuit for supplying a second output signal from a second drain of the second transistor;
A first source grounded amplification stage driven by a first drain output of the common source differential amplifier circuit;
A second common-source amplifier stage driven by a second drain output of the common source differential amplifier circuit;
The first grounded source amplification stage includes:
A first series circuit of at least two capacitive elements connected between the drain and the gate;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second source grounded amplification stage is:
A second series circuit of at least two capacitive elements connected between the drain and the gate;
An active filter comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential. A data transmission system for receiving modulated digital data by transmitting a predetermined medium,
An active filter for extracting desired signal data from the received digital data;
A demodulation circuit for demodulating the digital data extracted by the active filter,
The active filter is
An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each emitter having a base terminal as a differential input and having a first transistor and a second transistor whose emitters are commonly connected, and supplying an output signal from the collector of the first transistor or the second transistor A common differential amplifier circuit;
A common-emitter amplifier stage driven by the collector output of the common emitter differential amplifier circuit,
The grounded-emitter amplifier stage is
A series circuit of at least two capacitive elements connected between the collector and the base;
A data transmission system comprising: a connection point between capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. A data transmission system for receiving modulated digital data by transmitting a predetermined medium,
An active filter for extracting desired signal data from the received digital data;
A demodulation circuit for demodulating the digital data extracted by the active filter,
The active filter is
An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
A source having a first transistor and a second transistor each having a differential input as a gate terminal and a source connected in common, and supplying an output signal from the drain of the first transistor or the second transistor A common differential amplifier circuit;
A common-source amplifier stage driven by the drain output of the common source differential amplifier circuit;
The grounded source amplification stage is
A series circuit of at least two capacitive elements connected between the drain and the gate;
A data transmission system comprising: a connection point between capacitive elements of the series circuit; and at least one resistance element connected between a ground potential. A data transmission system for receiving modulated digital data by transmitting a predetermined medium,
An active filter for extracting desired signal data from the received digital data;
A demodulation circuit for demodulating the digital data extracted by the active filter,
The active filter is
An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each of the base terminals has a differential input and a first transistor and a second transistor whose emitters are commonly connected, and a first output signal is supplied from a first collector of the first transistor, An emitter-common differential amplifier circuit for supplying a second output signal from a second collector of the second transistor;
A first grounded-emitter amplifier stage driven by a first collector output of the common emitter differential amplifier circuit;
A second grounded-emitter amplifier stage driven by a second collector output of the common emitter differential amplifier circuit;
The first grounded-emitter amplification stage includes:
A first series circuit of at least two capacitive elements connected between the collector and the base;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second grounded-emitter amplification stage is:
A second series circuit of at least two capacitive elements connected between the collector and the base;
A data transmission system comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential. A data transmission system for receiving modulated digital data by transmitting a predetermined medium,
An active filter for extracting desired signal data from the received digital data;
A demodulation circuit for demodulating the digital data extracted by the active filter,
The active filter is
An operational amplifier;
A capacitive element connected between the output terminal of the operational amplifier and the input of the inverted phase of the operational amplifier;
An integration circuit with an input current supplied to the input of the inversion phase,
The operational amplifier is
Each gate terminal has a first transistor and a second transistor, each having a differential input and a source connected in common, and a first output signal is supplied from a first drain of the first transistor, A common source differential amplifier circuit for supplying a second output signal from a second drain of the second transistor;
A first source grounded amplification stage driven by a first drain output of the common source differential amplifier circuit;
A second common-source amplifier stage driven by a second drain output of the common source differential amplifier circuit;
The first grounded source amplification stage includes:
A first series circuit of at least two capacitive elements connected between the drain and the gate;
Having at least one resistance element connected between a connection point between the capacitive elements of the first series circuit and a ground potential;
The second source grounded amplification stage is:
A second series circuit of at least two capacitive elements connected between the drain and the gate;
A data transmission system comprising: a connection point between capacitive elements of the second series circuit; and at least one resistance element connected between a ground potential.

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