CN105403262B - Flow monitor - Google Patents
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- CN105403262B CN105403262B CN201510749766.4A CN201510749766A CN105403262B CN 105403262 B CN105403262 B CN 105403262B CN 201510749766 A CN201510749766 A CN 201510749766A CN 105403262 B CN105403262 B CN 105403262B
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Abstract
The invention provides a flow monitor, and belongs to the technical field of flow electronic monitoring. It has solved the current low problem of flow monitor work efficiency, shell protection level. The invention comprises a control module, a voltage signal acquisition module, a voltage signal output module and a data processing module, wherein the control module is used for collecting the voltage signal, outputting the voltage signal and processing data; the signal processing module is connected with the control module and used for connecting a sensor externally connected with the flow monitor and converting a current signal obtained by the sensor into a voltage signal and transmitting the voltage signal to the control module; the communication module is connected with the control module and is used for connecting input equipment externally connected with the flow monitor; and the display module is connected with the control module and used for outputting display signals. The invention has the advantages of a plurality of signal processing modules, expandable communication interfaces and high protection level.
Description
Technical Field
The invention belongs to the field of flow electronic monitoring, relates to a flow monitor, and particularly relates to a flow monitor for monitoring a fracturing truck hydrochloric acid solution.
Background
Flow monitors are commonly used to monitor the amount of flow through a chemical supply in a pipeline and to use the data obtained by the flow monitor to control the flow of the chemical supply in the pipeline. Usually, a flow sensor is installed inside the pipeline, and then a flow monitor is connected to the flow sensor, and the flow monitor processes data obtained by the flow sensor to obtain data of the actual flow in the pipeline, and uses the data as a standard for whether to adjust the flow in the pipeline. The input signals of the flow monitor used in the general daily production nowadays are usually one or two, which cannot meet the requirement of improving the efficiency in the production. Meanwhile, in the current production approaching automation control, a computer is also used for controlling the equipment and acquiring data from the equipment, and a mode of establishing connection and communication between the computer and the equipment is also used.
Meanwhile, the existing flow monitor lacks a component such as a display screen to transmit man-machine information; existing housings for flow detectors for chemical applications do not have a high level of protection.
In summary, in order to solve the functional deficiency of the existing flow monitor, a flow monitor with multiple signal processing modules, an expandable communication interface, and a high protection level needs to be designed.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a high-protection-level flow monitor which is provided with a plurality of signal processing modules and comprises an expandable communication interface.
The purpose of the invention can be realized by the following technical scheme: a flow monitor, comprising:
the signal processing module is used for connecting a sensor externally connected with the flow monitor and converting a current signal obtained by the sensor into a voltage signal to be transmitted to the control module;
the communication module is used for connecting input equipment externally connected with the flow monitor;
the display module is used for displaying the data of the voltage signal;
and the control module is used for collecting the voltage signal, outputting the voltage signal and processing data.
According to the flow monitor, the flow monitor comprises a first power supply module, wherein the first power supply module is connected with the signal processing module and used for supplying power to the signal processing module, and the first power supply module is further used for providing positive input voltage.
According to the flow monitor, the signal processing module comprises a first input end to a ninth input end, a first analog signal processing circuit, a second analog signal processing circuit, a first pulse signal processing circuit, a second pulse signal processing circuit, a first fuse to an eighth fuse, wherein the first input end to the fourth input end are respectively connected with positive input voltage through the first fuse, the third fuse, the fifth fuse and a seventh fuse; the fifth input end and the sixth input end are respectively connected with the first analog signal processing circuit and the second analog signal processing circuit through the second fuse and the fourth fuse, the eighth input end and the ninth input end are respectively connected with the first pulse signal processing circuit and the second pulse signal processing circuit through the eighth fuse and the sixth fuse, and the seventh input end is grounded; the signal processing module also comprises a pulse signal processing chip.
According to the above-mentioned one flow monitor, the first analog signal processing circuit and the second analog signal processing circuit have the same circuit configuration; the first analog signal processing circuit comprises first to sixth resistors, a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first diode, a first signal output end and a first analog signal processing chip; the first analog signal processing chip comprises a first interface to an eighth interface; the fifth input end of the signal processing module is connected with a second resistor through a second fuse and then is grounded through the second resistor, the fifth input end of the signal processing module is also connected with the inverting input end of a first operational amplifier through the second fuse and the first resistor, the output end of the first operational amplifier is connected with a first interface of a first analog signal processing chip through a fourth resistor, and the non-inverting input end of the first operational amplifier is grounded through a third resistor; a first parallel circuit consisting of the first diode and the first capacitor is connected in parallel with the inverting input end and the output end of the first operational amplifier, and one end of the first parallel circuit connected with the cathode of the first diode is connected with the inverting input end of the first operational amplifier; the third interface of the first analog signal processing chip is connected with the inverting input end of the first operational amplifier, the sixth interface of the first analog signal processing chip is connected with the inverting input end of the second operational amplifier, the second capacitor and the fifth resistor form a second parallel circuit, one end of the second parallel circuit is connected with the directional input end of the second operational amplifier, the other end of the second parallel circuit is connected with the output end of the second operational amplifier after passing through the sixth resistor, the output end of the second operational amplifier is connected with the first signal output end after passing through the sixth resistor, the positive phase input end of the second operational amplifier is connected with the fifth input end of the first analog signal processing chip, and the positive phase input end is grounded; the second interface of the first analog signal processing chip is connected with the anode input voltage, and the fourth interface is grounded.
According to the above flow monitor, the first pulse signal processing circuit includes a seventh resistor to an eleventh resistor, a third operational amplifier, and a first pulse signal processing chip, the first pulse signal processing chip includes a first interface to an eighth interface, an eighth input terminal of the signal processing module is connected to an inverting input terminal of the third operational amplifier through a sixth fuse and the seventh resistor, the inverting input terminal of the third operational amplifier is grounded through the eighth resistor, a positive input terminal of the third operational amplifier is connected to a positive input voltage through a ninth resistor, and the positive input terminal is grounded through a tenth resistor; the output end of the third operational amplifier is connected with the third interface of the first pulse signal processing chip, and the fourth interface of the first pulse signal processing chip is connected with the positive input voltage after passing through the eleventh resistor; the first pulse signal processing circuit and the second pulse signal processing circuit have the same circuit structure; the signal processing module further comprises a third capacitor, a twelfth resistor, a thirteenth resistor, a second signal output end and a third signal output end, wherein a sixth interface of the first pulse signal processing chip is connected with the second signal output end, a fifth interface of the first pulse signal processing chip is connected with the sixth interface of the first pulse signal processing chip through the third capacitor and the twelfth resistor, the fifth interface of the first pulse signal processing chip is grounded and is also connected with a positive input voltage through the third capacitor, an eighth interface of the first pulse signal processing chip is connected with the positive input voltage and is connected with a seventh interface of the first pulse signal processing chip through the thirteenth resistor, and the seventh interface of the first pulse signal processing chip is connected with the third signal output end.
According to the above flow monitor, the first power module includes a first voltage input terminal, a second voltage input terminal, a fourth capacitor to a seventh capacitor, a fourteenth resistor to a fifteenth resistor, a second diode, a first voltage regulation chip and a second voltage regulation chip, the first voltage regulation chip includes a first interface to a sixth interface, the second voltage regulation chip includes a first interface to a fourth interface; the first voltage input end is connected with the anode of the second diode, the cathode of the second diode is connected with the first interface of the first voltage stabilization chip, the second voltage input end of the first power supply module is connected with the first interface of the first voltage stabilization chip, and the fourth capacitor is connected in parallel with the first interface of the first voltage stabilization chip and two ends of the second interface of the first voltage stabilization chip; the fifth interface of the first voltage stabilizing chip is connected with the second interface of the second voltage stabilizing chip, the sixth interface of the first voltage stabilizing chip is connected with the first interface of the second voltage stabilizing chip, the fifth capacitor, the sixth capacitor and the fourteenth resistor form a third parallel circuit, the third parallel circuit is connected in parallel with the fifth interface of the first voltage stabilizing chip and two ends of the sixth interface of the first voltage stabilizing chip, one end of the fifth capacitor connected with the fifth interface of the first voltage stabilizing chip is grounded, the other end of the fifth capacitor connected with the positive input voltage, the fifteenth resistor and the seventh capacitor form a fourth parallel circuit, and the fourth parallel circuit is connected in parallel with the fifth interface of the second voltage stabilizing chip and two ends of the third interface of the second voltage stabilizing chip.
According to the above-mentioned flow monitor, the communication module comprises a first interface to a fourth interface, a second analog signal processing chip, a third analog signal processing chip, a MAX485 chip U7, a first 485 communication interface, a second 485 communication interface, a third 485 communication interface, an eighth capacitor, a ninth capacitor, a sixteenth resistor to an eighteenth resistor, a third diode, and a fourth diode, the MAX485 chip U7 comprises a first interface to an eighth interface, the second interface of the communication module is connected with the sixth interface of the MAX485 chip U7, the third interface of the communication module is connected with the seventh interface of the MAX485 chip U7, the sixteenth resistor and the seventeenth resistor are connected in parallel with the second interface of the communication module and the two ends of the third interface of the communication module, the second interface of the communication module is connected with the sixth interface of the MAX485 chip U7 through an eighth capacitor, the anode of a third diode and the cathode of the third diode in sequence; the third interface of the communication module is connected with the seventh interface of the MAX485 chip U7 through a ninth capacitor, the anode of a fourth diode and the cathode of a third diode in sequence; the fourth interface of MAX485 chip U7 connects the sixth interface of second analog signal processing chip, and MAX485 chip U7's second interface and third interface all connect the seventh interface of second analog signal processing chip, the third interface of second analog signal processing chip connects first 485 communication interface, and the second interface of second analog signal processing chip connects second 485 communication interface, MAX485 chip U7's first interface connects the third interface of third analog signal processing chip, the sixth interface of third analog signal processing chip connects third 485 communication interface.
According to the flow monitor, the flow monitor further comprises a display screen, and the display screen is connected with the display module.
According to the flow monitor, the control module comprises a PIC18F4685 chip, and the control module further comprises a key module, and a plurality of keys are arranged on the key module.
Compared with the prior art, the invention has the following advantages:
1. the flow monitor is equipped with 2 pulse signal processing module and 2 analog signal processing modules, and it is higher to handle signal efficiency.
2. The flow monitor is provided with a display screen which can display the data measured by the monitor in real time.
3. The flow monitor is provided with an extensible 485 communication interface, so that the flow monitor has the function of information input and output.
4. The shell protection level grade of the flow monitor reaches IP67, so that the flow monitor is more stable and safer when measuring the flow of chemicals.
Drawings
Fig. 1 is a circuit diagram of a signal processing module.
Fig. 2 is a circuit diagram of a first power supply module.
Fig. 3 is a circuit diagram of a communication module.
Fig. 4 is a circuit diagram of the control module.
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.
As shown in fig. 1 to 4, the present flow monitor includes a flow monitor, characterized by comprising: the signal processing module is used for connecting a sensor externally connected with the flow monitor and converting a current signal obtained by the sensor into a voltage signal to be transmitted to the control module; the communication module is used for connecting input equipment externally connected with the flow monitor; the display module is used for displaying the data of the voltage signal; and the control module is used for collecting the voltage signal, outputting the voltage signal and processing data.
According to the flow monitor, the flow monitor comprises a first power supply module, wherein the first power supply module is connected with the signal processing module and used for supplying power to the signal processing module, and the first power supply module is further used for providing positive input voltage.
According to the above flow monitor, the signal processing module includes a first input terminal to a ninth input terminal, a first analog signal processing circuit, a second analog signal processing circuit, a first pulse signal processing circuit, a second pulse signal processing circuit, a first fuse F1 to an eighth fuse F8, the first input terminal to the fourth input terminal are respectively connected with a positive input voltage through the first fuse F1, the third fuse F3, the fifth fuse F5 and the seventh fuse F7; the fifth input end and the sixth input end are respectively connected with the first analog signal processing circuit and the second analog signal processing circuit through a second fuse F2 and a fourth fuse F4, the eighth input end and the ninth input end are respectively connected with the first pulse signal processing circuit and the second pulse signal processing circuit through an eighth fuse F8 and a sixth fuse F6, and the seventh input end is grounded; the signal processing module also comprises a pulse signal processing chip.
According to the above-mentioned one flow monitor, the first analog signal processing circuit and the second analog signal processing circuit have the same circuit configuration; the first analog signal processing circuit comprises a first resistor R1-a sixth resistor R6, a first operational amplifier Q1, a second operational amplifier Q2, a first capacitor C1, a second capacitor C2, a first diode D1, a first signal output end T1 and a first analog signal processing chip U1; the first analog signal processing chip U1 comprises a first interface to an eighth interface; the fifth input end of the signal processing module is connected with a second resistor R2 through a second fuse F2 and then grounded through a second resistor R2, the fifth input end of the signal processing module is also connected with the inverting input end of a first operational amplifier Q1 through a second fuse F2 and a first resistor R1, the output end of the first operational amplifier Q1 is connected with a first interface of a first analog signal processing chip U1 through a fourth resistor R4 and the non-inverting input end of the first operational amplifier Q1 is grounded through a third resistor R3; a first parallel circuit consisting of the first diode D1 and the first capacitor C1 is connected in parallel with the inverting input end and the output end of the first operational amplifier Q1, and one end of the first parallel circuit connected with the cathode of the first diode D1 is connected with the inverting input end of the first operational amplifier Q1; the third interface of the first analog signal processing chip U1 is connected to the inverting input terminal of the first operational amplifier Q1, the sixth interface of the first analog signal processing chip U1 is connected to the inverting input terminal of the second operational amplifier Q2, the second capacitor C2 and the fifth resistor R5 form a second parallel circuit, one end of the second parallel circuit is connected to the directional input terminal of the second operational amplifier Q2, the other end of the second parallel circuit is connected to the output terminal of the second operational amplifier Q2 through the sixth resistor R6, the output terminal of the second operational amplifier Q2 is connected to the first signal output terminal T1 through the sixth resistor R6, the non-inverting input terminal of the second operational amplifier Q2 is connected to the fifth input terminal of the first analog signal processing chip U1, and the non-inverting input terminal is grounded; the second interface of the first analog signal processing chip U1 is connected with the anode input voltage, and the fourth interface is grounded.
The analog signal is input to the first analog signal processing circuit through the fifth input end of the signal processing module, the analog signal is output to the first analog signal processing chip U1 after passing through the first operational amplifier Q1 in the first analog signal processing circuit, and the first operational amplifier Q1, the first resistor R1 and the third resistor R3 form a negative feedback amplifying circuit which has an amplifying effect on the analog signal. The first analog signal processing chip U1 uses a linear optocoupler HCNR201 chip. The analog signal is output to the second operational amplifier Q2 through the fifth interface of the first analog signal processing chip U1, the second operational amplifier Q2 plays a role in buffering and front-back stage isolation on the analog signal, namely the second operational amplifier Q2 is used as a voltage follower and plays a role in buffering and isolating the analog signal. The analog signal passes through the second operational amplifier Q2 and the sixth resistor R6 and is outputted from the first signal output terminal T1.
First analog signal processing chip U1 adopts linear opto-coupler chip to be used for preventing external interference, uses the opto-coupler device to keep apart analog signal and has fine effect, and the transmission accuracy of general opto-coupler device receives the temperature influence great, so adopts linear opto-coupler to keep apart to satisfy the requirement of high accuracy.
According to the above flow monitor, the first pulse signal circuit includes seventh to eleventh resistors R7 to R11, a third operational amplifier Q3, and a first pulse signal processing chip U2, the first pulse signal processing chip U2 includes first to eighth interfaces, an eighth input terminal of the signal processing module is connected to an inverting input terminal of the third operational amplifier Q3 through a sixth fuse F6 and a seventh resistor R7, an inverting input terminal of the third operational amplifier Q3 is grounded through an eighth resistor R8, a non-inverting input terminal of the third operational amplifier Q3 is connected to a positive input voltage through a ninth resistor R9, and the non-inverting input terminal is grounded through a tenth resistor R10; the output end of the third operational amplifier Q3 is connected with the third interface of the first pulse signal processing chip U2, and the fourth interface of the first pulse signal processing chip U2 is connected with the positive input voltage after passing through an eleventh resistor R11; the first pulse signal processing circuit and the second pulse signal processing circuit have the same circuit structure; the signal processing module further includes a third capacitor C3, a twelfth resistor R12, a thirteenth resistor R13, a second signal output terminal T2, and a third signal output terminal T3, wherein a sixth interface of the first pulse signal processing chip U2 is connected to the second signal output terminal T2, a fifth interface of the first pulse signal processing chip U2 is connected to the sixth interface of the first pulse signal processing chip U2 through the third capacitor C3 and the twelfth resistor R12, the fifth interface of the first pulse signal processing chip U2 is grounded, the fifth interface of the first pulse signal processing chip U2 is also connected to a positive input voltage through the third capacitor C3, an eighth interface of the first pulse signal processing chip U2 is connected to the positive input voltage and is connected to a seventh interface of the first pulse signal processing chip U2 through the thirteenth resistor R13, and the seventh interface of the first pulse signal processing chip U2 is connected to the third signal output terminal T3.
The pulse signal is input to the first pulse signal processing circuit after passing through the eighth input end of the signal processing module, the pulse signal is amplified by the third operational amplifier Q3 and then output to the first pulse signal processing chip U2, and the pulse signal is transmitted by the first pulse signal processing chip U2 and then output to the second signal output end T2 of the signal processing module.
The first pulse signal processing chip U2 adopts an EL0630 chip, which outputs the received pulse signal from the output terminal of the chip through a high-speed optical coupler as a medium, and the chip also has the isolation function of two stages of input and output.
According to the above flow monitor, the first power module includes a first voltage input terminal T4, a second voltage input terminal T5, a fourth capacitor C4 to a seventh capacitor C7, a fourteenth resistor R14 to a fifteenth resistor R15, a second diode D2, a first voltage regulation chip U3 and a second voltage regulation chip U4, the first voltage regulation chip U3 includes a first interface to a sixth interface, and the second voltage regulation chip U4 includes a first interface to a fourth interface; the first voltage input end T4 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the first interface of the first voltage regulation chip U3, the second voltage input end T5 of the first power supply module is connected to the first interface of the first voltage regulation chip U3, and the fourth capacitor C4 is connected in parallel to the first interface of the first voltage regulation chip U3 and two ends of the second interface of the first voltage regulation chip U3; the fifth interface of the first voltage stabilization chip U3 is connected to the second interface of the second voltage stabilization chip U4, the sixth interface of the first voltage stabilization chip U3 is connected to the first interface of the second voltage stabilization chip U4, the fifth capacitor C5, the sixth capacitor C6 and the fourteenth resistor R14 form a third parallel circuit, the third parallel circuit is connected in parallel to the fifth interface of the first voltage stabilization chip U3 and two ends of the sixth interface of the first voltage stabilization chip U3, one end of the fifth capacitor C5, which is connected to the fifth interface of the first voltage stabilization chip U3, is grounded, the other end of the fifth interface is connected to the positive input voltage, the fifteenth resistor R15 and the seventh capacitor C7 form a fourth parallel circuit, and the fourth parallel circuit is connected in parallel to the fifth interface of the second voltage stabilization chip U4 and two ends of the third interface of the second voltage stabilization chip U4.
The voltage in the first power module is input from a first voltage input end T4, is output to the first voltage stabilization chip U3 after passing through the second diode D2, and is output after being stabilized by the second voltage stabilization chip U4 after passing through a third parallel circuit composed of a fifth capacitor C5, a sixth capacitor C6, and a fourteenth resistor R14. The first power supply module is used for stabilizing voltage and providing stable voltage for the signal processing module.
According to the above flow monitor, the communication module includes a first communication interface T6 to a fourth communication interface T9, a second analog signal processing chip U5, a third analog signal processing chip U6, a MAX485 chip U7, a first 485 communication interface T10, a second 485 communication interface T11, a third 485 communication interface T12, an eighth capacitor C8, a ninth capacitor C9, a sixteenth resistor R16 to an eighteenth resistor R18, a third diode D3, and a fourth diode D4, the MAX485 chip U7 includes a first interface to an eighth interface, the second communication interface T7 of the communication module is connected to a sixth interface of the MAX485 chip U7, the third communication interface T8 of the communication module is connected to a seventh interface of the MAX485 chip U7, the sixteenth resistor R16 and the seventeenth resistor R17 are connected in parallel to the second communication interface T7 of the communication module and the second communication interface T8 of the communication module, and the eighth communication interface T7 and the eighth communication interface T8 of the communication module is connected in sequence through the second communication interface T7, the eighth communication interface C7, and the eighth communication interface of the third communication module, The anode of the third diode D3 and the cathode of the third diode D3 are connected with a sixth interface of the MAX485 chip U7; a third communication interface T8 of the communication module is sequentially connected with a seventh interface of the MAX485 chip U7 through a ninth capacitor C9, an anode of a fourth diode D4 and a cathode of a third diode D3; the fourth interface of MAX485 chip U7 connects the sixth interface of second analog signal processing chip U5, and MAX485 chip U7's second interface and third interface all connect the seventh interface of second analog signal processing chip U5, the third interface of second analog signal processing chip U5 connects first 485 communication interface T10, and the second interface of second analog signal processing chip U5 connects second 485 communication interface T11, MAX485 chip U7's first interface connects the third interface of third analog signal processing chip U6, the sixth interface of third analog signal processing chip U6 connects third 485 communication interface T12.
The communication module comprises an input and output function, input signals are input through a first 485 communication interface T10 and a second 485 communication interface T11, when a low level is input through a first 485 communication interface T10, a seventh interface of an MAX485 chip U7 outputs a high level, and a sixth interface outputs a low level; on the contrary, the seventh interface outputs a low level, and the sixth interface outputs a high level, on the premise that the second 485 communication interface T11 inputs a high level. When the second 485 communication interface T11 inputs a low level, the communication module starts an output function, and input signals are input by the second communication interface T7 and the third communication interface T8 of the communication module, when the level input by the second communication interface T7 of the communication module is higher than the level of the third communication interface T8 of the communication module, the first interface of the MAX485 chip U7 outputs a high level, otherwise, a low level is output, which is assumed that the second 485 communication interface T11 inputs a low level. When the first interface of the MAX485 chip U7 outputs a high level, the high level signal passes through the third analog signal processing chip U6 and is output by the third 485 communication interface T12.
According to the flow monitor, the flow monitor further comprises a display screen, and the display screen is connected with the display module.
According to the flow monitor, the control module comprises a PIC18F4685 chip, and the control module further comprises a key module, and a plurality of keys are arranged on the key module.
According to the flow monitor, the flow monitor further comprises a shell, the protection grade of the shell can reach IP67 and IP67, the flow monitor is suitable for the environment of exploiting shale gas, and the flow monitor is protected from being damaged.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (3)
1. A flow monitor, comprising:
the signal processing module is used for connecting a sensor externally connected with the flow monitor and converting a current signal obtained by the sensor into a voltage signal to be transmitted to the control module;
the communication module is used for connecting input equipment externally connected with the flow monitor;
the display module is used for displaying the data of the voltage signal;
the control module is used for collecting voltage signals, outputting the voltage signals and processing data;
the first power supply module is connected with the signal processing module and used for supplying power to the signal processing module, and the first power supply module is also used for providing positive input voltage;
the signal processing module comprises a first input end to a ninth input end, a first analog signal processing circuit, a second analog signal processing circuit, a first pulse signal processing circuit, a second pulse signal processing circuit, a first fuse to an eighth fuse, a first input end to a fourth input end which are respectively connected with positive input voltage through the first fuse, the third fuse, the fifth fuse and the seventh fuse; the fifth input end and the sixth input end are respectively connected with the first analog signal processing circuit and the second analog signal processing circuit through the second fuse and the fourth fuse, the eighth input end and the ninth input end are respectively connected with the first pulse signal processing circuit and the second pulse signal processing circuit through the eighth fuse and the sixth fuse, and the seventh input end is grounded; the signal processing module also comprises a pulse signal processing chip;
the first analog signal processing circuit and the second analog signal processing circuit have the same circuit structure; the first analog signal processing circuit comprises first to sixth resistors, a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first diode, a first signal output end and a first analog signal processing chip; the first analog signal processing chip comprises a first interface to an eighth interface; the fifth input end of the signal processing module is connected with a second resistor through a second fuse and then is grounded through the second resistor, the fifth input end of the signal processing module is also connected with the inverting input end of a first operational amplifier through the second fuse and the first resistor, the output end of the first operational amplifier is connected with a first interface of a first analog signal processing chip through a fourth resistor, and the non-inverting input end of the first operational amplifier is grounded through a third resistor; a first parallel circuit consisting of a first diode and a first capacitor is connected in parallel with the inverting input end and the output end of the first operational amplifier, and one end of the first parallel circuit connected with the cathode of the first diode is connected with the inverting input end of the first operational amplifier; the third interface of the first analog signal processing chip is connected with the inverting input end of the first operational amplifier, the sixth interface of the first analog signal processing chip is connected with the inverting input end of the second operational amplifier, the second capacitor and the fifth resistor form a second parallel circuit, one end of the second parallel circuit is connected with the input end of the second operational amplifier, the other end of the second parallel circuit is connected with the output end of the second operational amplifier after passing through the sixth resistor, the output end of the second operational amplifier is connected with the first signal output end after passing through the sixth resistor, the normal phase input end of the second operational amplifier is connected with the fifth input end of the first analog signal processing chip, and the normal phase input end is grounded; the second interface of the first analog signal processing chip is connected with the positive input voltage, and the fourth interface is grounded;
the first pulse signal processing circuit comprises a seventh resistor, an eleventh resistor, a third operational amplifier and a first pulse signal processing chip, the first pulse signal processing chip comprises a first interface, an eighth input end of the signal processing module is connected with an inverting input end of the third operational amplifier through a sixth fuse and the seventh resistor, the inverting input end of the third operational amplifier is grounded through the eighth resistor, a positive phase input end of the third operational amplifier is connected with a positive input voltage through a ninth resistor, and the positive phase input end is grounded through a tenth resistor; the output end of the third operational amplifier is connected with the third interface of the first pulse signal processing chip, and the fourth interface of the first pulse signal processing chip is connected with the positive input voltage after passing through the eleventh resistor; the first pulse signal processing circuit and the second pulse signal processing circuit have the same circuit structure; the signal processing module further comprises a third capacitor, a twelfth resistor, a thirteenth resistor, a second signal output end and a third signal output end, a sixth interface of the first pulse signal processing chip is connected with the second signal output end, a fifth interface of the first pulse signal processing chip is connected with the sixth interface of the first pulse signal processing chip through the third capacitor and the twelfth resistor, the fifth interface of the first pulse signal processing chip is grounded and also connected with a positive input voltage through the third capacitor, an eighth interface of the first pulse signal processing chip is connected with the positive input voltage and is connected with a seventh interface of the first pulse signal processing chip through the thirteenth resistor, and the seventh interface of the first pulse signal processing chip is connected with the third signal output end;
the first power supply module comprises a first voltage input end, a second voltage input end, fourth to seventh capacitors, fourteenth to fifteenth resistors, a second diode, a first voltage stabilizing chip and a second voltage stabilizing chip, wherein the first voltage stabilizing chip comprises a first interface to a sixth interface, and the second voltage stabilizing chip comprises a first interface to a fourth interface; the first voltage input end is connected with the anode of the second diode, the cathode of the second diode is connected with the first interface of the first voltage stabilization chip, the second voltage input end of the first power supply module is connected with the first interface of the first voltage stabilization chip, and the fourth capacitor is connected in parallel with the first interface of the first voltage stabilization chip and the two ends of the second interface of the first voltage stabilization chip; a fifth interface of the first voltage stabilizing chip is connected with a second interface of the second voltage stabilizing chip, a sixth interface of the first voltage stabilizing chip is connected with a first interface of the second voltage stabilizing chip, a fifth capacitor, a sixth capacitor and a fourteenth resistor form a third parallel circuit, the third parallel circuit is connected in parallel with the fifth interface of the first voltage stabilizing chip and two ends of the sixth interface of the first voltage stabilizing chip, one end of the fifth capacitor connected with the fifth interface of the first voltage stabilizing chip is grounded, the other end of the fifth capacitor connected with the anode input voltage, the fifteenth resistor and the seventh capacitor form a fourth parallel circuit, and the fourth parallel circuit is connected in parallel with the fifth interface of the second voltage stabilizing chip and two ends of the third interface of the second voltage stabilizing chip;
the communication module comprises a first interface, a second interface, an analog signal processing chip, a third analog signal processing chip, an MAX485 chip, a first 485 communication interface, a second 485 communication interface, a third 485 communication interface, an eighth capacitor, a ninth capacitor, a sixteenth resistor, a eighteenth resistor, a third diode, a fourth diode and an MAX485 chip, wherein the first interface, the second interface, the sixth interface, the seventh interface, the sixteenth resistor, the seventeenth resistor and the seventeenth resistor are connected in parallel at two ends of the second interface and the third interface of the communication module, the second interface of the communication module sequentially passes through the eighth capacitor, the anode of the third diode and the cathode of the third diode and then is connected with the sixth interface of the MAX485 chip; a third interface of the communication module is connected with a seventh interface of the MAX485 chip after sequentially passing through a ninth capacitor, an anode of a fourth diode and a cathode of a third diode; the fourth interface of the MAX485 chip is connected with the sixth interface of the second analog signal processing chip, the second interface and the third interface of the MAX485 chip are both connected with the seventh interface of the second analog signal processing chip, the third interface of the second analog signal processing chip is connected with the first 485 communication interface, the second interface of the second analog signal processing chip is connected with the second 485 communication interface, the first interface of the MAX485 chip is connected with the third interface of the third analog signal processing chip, and the sixth interface of the third analog signal processing chip is connected with the third 485 communication interface.
2. The flow monitor of claim 1, further comprising a display screen coupled to the display module.
3. The flow monitor according to claim 2, wherein the control module comprises a PIC18F4685 chip, and the control module further comprises a key module, and the key module is provided with a plurality of keys.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510749766.4A CN105403262B (en) | 2015-11-06 | 2015-11-06 | Flow monitor |
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| CN201510749766.4A CN105403262B (en) | 2015-11-06 | 2015-11-06 | Flow monitor |
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| CN105403262A CN105403262A (en) | 2016-03-16 |
| CN105403262B true CN105403262B (en) | 2021-03-19 |
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| CN1062207A (en) * | 1991-12-26 | 1992-06-24 | 四川久大盐业(集团)公司 | Anti-corrosion electric transmitted-high pressure flow meter |
| CN2238420Y (en) * | 1996-03-15 | 1996-10-23 | 山西省煤炭工业综合经营总公司 | Automatic recording device for measuring lot water flow |
| US6843110B2 (en) * | 2002-06-25 | 2005-01-18 | Fluid Components International Llc | Method and apparatus for validating the accuracy of a flowmeter |
| CN103933641A (en) * | 2014-05-14 | 2014-07-23 | 胡达广 | Capacitor micro-flow detection device |
| CN204269165U (en) * | 2014-11-25 | 2015-04-15 | 苏州市职业大学 | A kind of flow measuring instrument |
| CN205192546U (en) * | 2015-11-06 | 2016-04-27 | 宁波长壁流体动力科技有限公司 | Flow monitor |
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