CN105699957A - Multi-array element sonar signal acquisition circuit - Google Patents
Multi-array element sonar signal acquisition circuit Download PDFInfo
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- CN105699957A CN105699957A CN201610152574.XA CN201610152574A CN105699957A CN 105699957 A CN105699957 A CN 105699957A CN 201610152574 A CN201610152574 A CN 201610152574A CN 105699957 A CN105699957 A CN 105699957A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/534—Details of non-pulse systems
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- Radar, Positioning & Navigation (AREA)
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- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Abstract
The invention relates to a multi-array element sonar signal acquisition circuit, which comprises a signal conditioning circuit, an A/D conversion circuit, a signal latch circuit, an FPGA circuit, a DSP detection circuit and a data uploading circuit, wherein the input end of the signal conditioning circuit is connected with a transducer, and the output end is connected with the A/D conversion circuit; the input end of the A/D conversion circuit is connected with the signal conditioning circuit and the output end is connected with the signal latch circuit; the input end of the signal latch circuit is connected with the A/D conversion circuit, and the output end is connected with the FPGA circuit and the DSP detection circuit; the input end of the FPGA circuit is connected with a data transmission bus, and the output end is connected with the DSP detection circuit, the A/D conversion circuit and the data uploading circuit; the input end of the DSP detection circuit is connected with the data transmission bus and the FPGA circuit; and the input end of the data uploading circuit is connected with the FPGA circuit and the output end is connected with a parallel data processing part in an instrument cabin. The multi-array element sonar signal acquisition circuit has the advantages that generation of even harmonics is reduced; system common mode noise is eliminated; high-frequency noise can be filtered; the acquisition precision is high; the dynamic range is large; the circuit structure is reasonable; the cost is low; and the multi-array element sonar signal acquisition circuit is applicable to point-to-point long-distance communication, and the transmission rate is quick.
Description
Technical field
The present invention relates to development technique field under water, be specifically related to a kind of many array element sonar signal Acquisition Circuit。
Background technology
Along with the increase day by day of ocean development and undersea detection demand, the research of high resolution section sonar increasingly comes into one's own。
But, section sonar of the prior art disadvantageously, lack of resolution, system common-mode noise, high frequency noise effect are big, precision is low, transmission range is short, high cost。
Summary of the invention
It is an object of the invention to for deficiency of the prior art, it is provided that a kind of high accuracy, effect of noise, transmission range length many array element sonar signal Acquisition Circuit。
For achieving the above object, the invention discloses following technical scheme:
A kind of many array element sonar signal Acquisition Circuit, uploads circuit including signal conditioning circuit, A/D change-over circuit, signal latch circuit, FPGA circuitry, DSP testing circuit and data:
Signal conditioning circuit, input connects transducer, and outfan connects A/D change-over circuit, and the analogue signal that transducer is received is amplified and filters, and answers A/D converter requirement to complete 1 times of gain differential conversion to input simulation single-ended signal；
A/D change-over circuit, input connects signal conditioning circuit, and outfan connects signal latch circuit, and through A/D converter, filtered analogue signal is quantified as 12 position digital signals；
Signal latch circuit, input connects A/D change-over circuit, outfan connects FPGA circuitry and DSP testing circuit, the 18 road signals collected are latched in respective trigger simultaneously, the a set of data transmission bus of delivery outlet multiplexing of trigger, by the sequencing contro to each road trigger, the data latched in trigger are sequentially read according to certain sequential；
FPGA circuitry, input connects data transmission bus, outfan connects DSP testing circuit, A/D change-over circuit and data and uploads circuit, complete the time series stereodata to front-end A/D C, latch, and the data collected are carried out data buffering, sign extended and data packing function, and upload the sequencing contro of circuit by data output by data；
DSP testing circuit, input connects data transmission bus and FPGA circuitry, utilizes the on-line debugging function of CCS to the realization of the data converting function of checking ADC and the data collected to be verified；
Data upload circuit, and input connects FPGA circuitry, and outfan connects the parallel data in instrument room and processes part, complete the data communication function of DSP co-processing board with underwater signal processing unit。
Further, the data transfer mode that the data after the conversion of described A/D change-over circuit are uploaded by same set of data transmission bus, namely complete 18 passage ADC synchronous acquisitions, after latched device buffering, Staggered transmitting is to FPGA circuitry or DSP testing circuit。
Further, described signal processing circuit includes signal amplification circuit and single-ended signal turns differential signal circuit:
Signal amplification circuit, including two-stage amplifying circuit, first order amplifying circuit adopts homophase to amplify, and the second season, amplifying circuit adopted anti-phase amplification；First order amplifying circuit and second level amplifying circuit are 10 times of amplifications；
Single-ended signal turns differential signal circuit, selects double operational OPA2822 as the amplifier of circuit, and what outfan adopted in the same direction is voltage follower circuit, and what inverse output terminal adopted is gain is the reverse amplification circuit of 1。
Further, two outfans at differential signal all have employed the Butterworth second-order low-pass filter circuit that lower-cut-off frequency is 100kHz, and gain is 1, and its integrated transporting discharging adopts OPA2822 chip。
Further, described A/D change-over circuit adopts ADS804 analog-digital converter。
Further, the latch of described signal latch circuit is 16, edge tri-state d type flip flop SN74LVTH16374 chip, comprise two independent outputs and enable control signal OE1, OE2 and input signal latch signal CP1, CP2 all the time, if OE is low level, then the data of outfan output latch；If OE is high level, then outfan is high-impedance state；If CP and OE is low level, the data of outfan remain unchanged。
Further, described DSP testing circuit is completed by DSP-TMS320VC33；Data transmission between DSP testing circuit and FPGA circuitry is to be realized by the external data bus of DSP, address bus and control bus, and communication therebetween adopts the mode of command word。
Further, described data upload the chip that circuit adopts is can the CY7B923 of point-to-point distance serial high-speed communication。
One many array element sonar signal Acquisition Circuit disclosed by the invention, has the advantages that
1. adopt the A/D converter of differential signal input, decrease the generation of even-order harmonic, substantially eliminate system common-mode noise；
2. can filter away high frequency noise；
3. acquisition precision is high, dynamic range is big；
4. circuit structure is reasonable, and cost is low；
5. it is suitable for point-to-point long haul communication and transfer rate is fast。
Accompanying drawing explanation
Fig. 1 is data acquisition circuit theory diagram；
Fig. 2 is signal amplification circuit schematic diagram；
Fig. 3 is single-ended signal slip sub-signal circuit theory diagrams；
Fig. 4 is second-order low-pass filter circuit theory diagrams；
Fig. 5 is A/D change-over circuit figure；
Fig. 6 is signal latch circuit schematic diagram；
Fig. 7 is FPGA and dsp interface circuit diagram；
Fig. 8 is that data upload interface circuit figure。
Detailed description of the invention
Below in conjunction with embodiment and with reference to accompanying drawing, the invention will be further described。
Refer to Fig. 1。A kind of many array element sonar signal Acquisition Circuit, uploads circuit including signal conditioning circuit, A/D change-over circuit, signal latch circuit, FPGA circuitry, DSP testing circuit and data:
Signal conditioning circuit, input connects transducer, and outfan connects A/D change-over circuit, and the analogue signal that transducer is received is amplified and filters, and answers A/D converter requirement to complete 1 times of gain differential conversion to input simulation single-ended signal；
A/D change-over circuit, input connects signal conditioning circuit, and outfan connects signal latch circuit, and through A/D converter, filtered analogue signal is quantified as 12 position digital signals；
Signal latch circuit, input connects A/D change-over circuit, outfan connects FPGA circuitry and DSP testing circuit, the 18 road signals collected are latched in respective trigger simultaneously, the a set of data transmission bus of delivery outlet multiplexing of trigger, by the sequencing contro to each road trigger, the data latched in trigger are sequentially read according to certain sequential；
FPGA circuitry, it it is the core of data collecting system, input connects data transmission bus, outfan connects DSP testing circuit, A/D change-over circuit and data and uploads circuit, that FPGA selects is ALTERA company EP1K30TC144-3, complete the time series stereodata to front-end A/D C, latch, and the data collected are carried out data buffering, sign extended and data packing function, and upload the sequencing contro of circuit by data output by data；
DSP testing circuit, input connects data transmission bus and FPGA circuitry, utilizes the on-line debugging function of CCS to the realization of the data converting function of checking ADC and the data collected to be verified；
Data upload circuit, and input connects FPGA circuitry, and outfan connects the parallel data in instrument room and processes part, complete the data communication function of DSP co-processing board with underwater signal processing unit。
In the present embodiment, the data transfer mode that the data after the conversion of described A/D change-over circuit are uploaded by same set of data transmission bus, namely complete 18 passage ADC synchronous acquisitions, after latched device buffering, Staggered transmitting is to FPGA circuitry or DSP testing circuit。
In the present embodiment, described signal processing circuit includes signal amplification circuit and single-ended signal turns differential signal circuit:
Signal amplification circuit, as in figure 2 it is shown, adopt two-stage to amplify, in order to be effectively prevented the self-excitation of amplifying circuit, adopts the mode of mixing, and namely first order amplifying circuit adopts homophase to amplify, and the second season, amplifying circuit adopted anti-phase amplification；And in amplification, the first order, the second level are 10 times of amplifications, i.e. 20dB, the forward and backward two-stage of such signal regulating panel amplifies the gain of a total 40dB。R5, R6, R7 and U2A constitute the first order and amplify, and R5 adopts 1K Ω, R6 to adopt the part that 10K Ω, R7 adopt 910 Ω, U2A to be OPA2822U。R5 and R6 determines the amplification of first order amplifier, and R7 is balancing resistance。R5, R6, R7 and U2A constitute the first order and amplify, and R5 adopts 1K Ω, R6 to adopt the part that 10K Ω, R7 adopt 910 Ω, U2A to be OPA2822U。R5 and R6 determines the amplification of first order amplifier, and R7 is balancing resistance。R9, R10, R11 and U2B constitute the second level and amplify, and R9 adopts 1K Ω, R10 to adopt the part that 10K Ω, R11 adopt 910 Ω, U2B to be OPA2822。R9 and R10 determines the amplification of first order amplifier, and R11 is balancing resistance。C2 is the DC component in coupling electric capacity filtered signal so that forward and backward level can be good at being coupled, and takes 0.1uF。R8 is that build-out resistor takes 100 Ω, adjustment and the impedance matching between rear class。
Single-ended signal turns differential signal circuit as shown in Figure 3, the present invention is in order to reduce the generation of even-order harmonic, eliminating system common-mode noise fully, have employed the A/D converter that signal input part is differential signal input, this is accomplished by converting single-ended input signal to differential signal and is supplied to ADC。Require that the noise of amplifier itself is only small simultaneously, so just the precision of ADC will not be produced excessive impact。In the design, selecting double operational OPA2822 as the amplifier of circuit, what outfan adopted in the same direction is voltage follower circuit, and what inverse output terminal adopted is gain is the reverse amplification circuit of 1。In Fig. 3, C5 and C10 is high-frequency filter capacitor, and capacitance takes 22puF。The gain of R2, R3, R5, R8, R12 initialization circuit, resistance takes 392 Ω。U1A and U1B adopts OPA2822U and resistance R2, R3, R5, R8, R12 to constitute feedback and converts single-ended signal to double-end signal。
In the present embodiment, it is 35～65kHz for input signal frequency range, mid frequency is 50kHz, for filter away high frequency noise, two outfans at differential signal all have employed the Butterworth second-order low-pass filter circuit that lower-cut-off frequency is 100kHz, gain is 1, and its integrated transporting discharging adopts OPA2822 chip。Resistance R6 and electric capacity C6 constitutes high pass filter, and R6 takes 365 Ω, C6 and takes 0.05uF。Resistance R5 and electric capacity C7 constitutes low pass filter, and R5 takes 365 Ω, C7 and takes 0.05uF。U2B amplifier adopts OPA2822U。C8 filters direct current signal for coupling electric capacity, takes 0.1uf。R7 is build-out resistor, value 1K Ω。
In the present embodiment, Fig. 5 is shown in by A/D change-over circuit。Filtered analogue signal is quantified as 12 position digital signals through A/D changer。Owing to port number is more, require that the precision gathered is high, dynamic range big (12 A/D samplings), simultaneously take account of the requirements such as acquisition system mechanical mechanism and cost, thus the data transfer mode that the data after A/D conversion are uploaded by the present invention by same set of data/address bus, namely completing 18 passage ADC synchronous acquisitions, after latched device latch buffering, Staggered transmitting is to the function of FPGA or testing circuit。Described A/D change-over circuit adopts ADS804 analog-digital converter。In figure, R27, R28, c12 configure the reference voltage of ADS804, select power supply as reference voltage, and R27 takes 10K Ω, R28 and takes 5K Ω, C12 and select 104 electric capacity。Resistance R25, R26 and electric capacity C8, C11, C9, C10 form electric source filter circuit, and resistance R25 and resistance R26 selects 100 Ω, and electric capacity C8, C11 select 104, and electric capacity C9 and C10 selects 10uf。
In order to save pcb board space, the present invention devises latch cicuit, adopt 16, the edge tri-state d type flip flop SN74LVTH16374 chip of TI company, the thought of design is to be latched in respective trigger by the 18 road signals collected simultaneously, the a set of transfer bus of delivery outlet multiplexing of trigger, by the sequencing contro to each road trigger, the data latched in trigger are sequentially read according to certain sequential。SN74LVTH16374 is a kind of 16, d type flip flop type, have the latch of 3 state outfans, comprise two independent outputs and enable control signal OE1, OE2 and input signal latch signal CP1, CP2 all the time, the rising edge of CP (clock signal) latches the data of input, if OE is low level, then the data of outfan output latch；If OE is high level, then outfan is high-impedance state；If CP and OE is low level, the data of outfan remain unchanged。C19, C20 filter out power noise in Fig. 5, selects 0.1uF。
In the present embodiment, described DSP testing circuit is completed by DSP-TMS320VC33；The introducing of DSP also enhances versatility and the propagation energy flexibly of this data collecting system。In the present system, by the logic control of the complete paired data acquisition system of FPGA, DSP complete the verifying work collecting data。Data transmission between DSP testing circuit and FPGA circuitry is to be realized by the external data bus of DSP, address bus and control bus, therebetween communication adopts the mode of command word, namely different modes of operation is distinguished with different address signals, therefore DSP and FPGA have employed the address bus of DSP outside least-significant byte when connecting, and now always has 28Command word=256 kinds different, FPGA have selected a part of command word therein and carries out decoding process, goes to perform various function after decoding。
In the present embodiment, it is can the CY7B923 (the HOTLNIK transmitter CY7B923 of Cypress company) of point-to-point distance serial high-speed communication that described data upload the chip that circuit adopts。This chip is applicable to point-to-point distance serial high-speed communication, adopts base band transmission communication mode, and supports charged hot plug。Its advantage is that cost is low, easy for installation。Suitable in optical fiber, coaxial cable and twisted-pair feeder as transmission medium。Maximum transmission distance (reference value of 330Mbps) is。A few km of optical fiber, coaxial cable 150 meters, Shielded Twisted Pair 80 meters, unshielded twisted pair 40 meters。8B/10B coding transmission or do not encode direct transfers, transmission speed is 160,330,400Mbps third gear。Data upload circuit diagram as shown in Figure 8, and in figure, C27, C28, C29 are power filtering capacitor, and capacitance selects 0.1uF, C31 to be exterior arrangement electric capacity, and capacitance selects 0.1F。R16, R17, R18, R19 are the mode of operation configuration resistance of CY7B923, and resistance selects 1K。R20, R21, C30 are build-out resistor electric capacity, and resistance R20, R21 select 270 Ω, electric capacity C30 to select 0.uF。
The above is only the preferred embodiment of the present invention, is not intended to limit；Should be understood that, although the present invention being described in detail with reference to the various embodiments described above, it will be understood by those within the art that, the technical scheme described in the various embodiments described above still can be modified by it, or wherein some or all of technical characteristic carries out equivalent replacement；And these amendments and replacement, do not make the essence of corresponding technical scheme depart from the scope of various embodiments of the present invention technical scheme。
Claims (8)
1. array element sonar signal Acquisition Circuit more than a kind, it is characterised in that include signal conditioning circuit, A/D change-over circuit, signal latch circuit, FPGA circuitry, DSP testing circuit and data and upload circuit:
Signal conditioning circuit, input connects transducer, and outfan connects A/D change-over circuit, and the analogue signal that transducer is received is amplified and filters, and answers A/D converter requirement to complete 1 times of gain differential conversion to input simulation single-ended signal；
A/D change-over circuit, input connects signal conditioning circuit, and outfan connects signal latch circuit, and through A/D converter, filtered analogue signal is quantified as 12 position digital signals；
Signal latch circuit, input connects A/D change-over circuit, outfan connects FPGA circuitry and DSP testing circuit, the 18 road signals collected are latched in respective trigger simultaneously, the a set of data transmission bus of delivery outlet multiplexing of trigger, by the sequencing contro to each road trigger, the data latched in trigger are sequentially read according to certain sequential；
FPGA circuitry, input connects data transmission bus, outfan connects DSP testing circuit, A/D change-over circuit and data and uploads circuit, complete the time series stereodata to front-end A/D C, latch, and the data collected are carried out data buffering, sign extended and data packing function, and upload the sequencing contro of circuit by data output by data；
DSP testing circuit, input connects data transmission bus and FPGA circuitry, utilizes the on-line debugging function of CCS to the realization of the data converting function of checking ADC and the data collected to be verified；
Data upload circuit, and input connects FPGA circuitry, and outfan connects the parallel data in instrument room and processes part, complete the data communication function of DSP co-processing board with underwater signal processing unit。
2. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterized in that, the data transfer mode that data after the conversion of described A/D change-over circuit are uploaded by same set of data transmission bus, namely completing 18 passage ADC synchronous acquisitions, after latched device buffering, Staggered transmitting is to FPGA circuitry or DSP testing circuit。
3. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterised in that described signal processing circuit includes signal amplification circuit and single-ended signal turns differential signal circuit:
Signal amplification circuit, including two-stage amplifying circuit, first order amplifying circuit adopts homophase to amplify, and the second season, amplifying circuit adopted anti-phase amplification；First order amplifying circuit and second level amplifying circuit are 10 times of amplifications；
Single-ended signal turns differential signal circuit, selects double operational OPA2822 as the amplifier of circuit, and what outfan adopted in the same direction is voltage follower circuit, and what inverse output terminal adopted is gain is the reverse amplification circuit of 1。
4. one many array element sonar signal Acquisition Circuit according to claim 3, it is characterized in that, two outfans at differential signal all have employed the Butterworth second-order low-pass filter circuit that lower-cut-off frequency is 100kHz, and gain is 1, and its integrated transporting discharging adopts OPA2822 chip。
5. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterised in that described A/D change-over circuit adopts ADS804 analog-digital converter。
6. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterized in that, the latch of described signal latch circuit is 16, edge tri-state d type flip flop SN74LVTH16374 chip, comprise two independent outputs and enable control signal OE1, OE2 and input signal latch signal CP1, CP2 all the time, if OE is low level, then the data of outfan output latch；If OE is high level, then outfan is high-impedance state；If CP and OE is low level, the data of outfan remain unchanged。
7. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterised in that described DSP testing circuit is completed by DSP-TMS320VC33；Data transmission between DSP testing circuit and FPGA circuitry is to be realized by the external data bus of DSP, address bus and control bus, and communication therebetween adopts the mode of command word。
8. one many array element sonar signal Acquisition Circuit according to claim 1, it is characterised in that it is can the CY7B923 of point-to-point distance serial high-speed communication that described data upload the chip that circuit adopts。
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| CN110739957A (en) * | 2019-11-29 | 2020-01-31 | 深圳市新威尔电子有限公司 | Single-end to differential signal driving circuit |
| CN111752310A (en) * | 2020-05-20 | 2020-10-09 | 哈船光电(武汉)有限公司 | High-precision shaft angle signal conversion module |
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Application publication date: 20160622 |