CN207458323U - A kind of host MBUS receiving circuits applied to multinode - Google Patents
A kind of host MBUS receiving circuits applied to multinode Download PDFInfo
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- CN207458323U CN207458323U CN201721197008.7U CN201721197008U CN207458323U CN 207458323 U CN207458323 U CN 207458323U CN 201721197008 U CN201721197008 U CN 201721197008U CN 207458323 U CN207458323 U CN 207458323U
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Abstract
The utility model provides a kind of host MBUS receiving circuits applied to multinode, prime filter difference amplifying circuit and signal output apparatus including receiving signal, the prime filter difference amplifying circuit includes prime filter circuit and differential amplifier circuit, the prime filter circuit includes the first filter circuit for receiving high level signal and receives the second filter circuit of low level signal and the capacitance C14 of the first filter circuit of connection and the second filter circuit, the differential amplifier circuit includes operational amplifier, the 3rd the second filter circuit of leads ends that first filter circuit outputs signal to operational amplifier outputs signal to the 4th leads ends of operational amplifier.Circuit provided by the utility model can be such that received signal is exported after multiple-stage filtering and amplification by signal output apparatus to host side, effectively improve received signal strength, enhance stable output signal, increase from node band and carry number, so as to improve circuit load and receive the antijamming capability of signal.
Description
Technical field
The utility model belongs to control circuit technical field, and in particular to a kind of host MBUS applied to multinode is received
Circuit.
Background technology
MBUS is a kind of bus protocol exclusively for the design of calorimeter remote data transmission at present, it is measuring instrumentss data
A kind of transmitting digitized important technology has been widely used for the data acquisition of no source contact such as water, electricity, gas, heat energy meter etc.
Occasion, existing MBus hosts receiving portion circuit, industrially using poor anti jamming capability, transmission distance deviation, communication rate be low,
The features such as bus node is few.
Utility model content
This practicality purpose of utility model is to provide a kind of host MBUS receiving circuits applied to multinode, reception electricity
Road can solve deficiency of the prior art.
To achieve the above object, the utility model uses following technical scheme：
A kind of host MBUS receiving circuits applied to multinode, the prime filter difference amplifying circuit including receiving signal
And signal output apparatus, the prime filter difference amplifying circuit includes prime filter circuit and differential amplifier circuit, described
Prime filter circuit include receive high level signal the first filter circuit and receive low level signal the second filter circuit with
And the capacitance C14 of the first filter circuit of connection and the second filter circuit, first filter circuit include resistance R12, capacitance
C12, resistance R9, the resistance R12 receive high level signal and pass through the capacitance C12 being connected in parallel and resistance R9 outputs；It is described
Second filter circuit includes resistance R21, capacitance C16 and resistance R23, the resistance R21 receive low level signal and pass through parallel connection
Capacitance C16 and resistance R23 output；The differential amplifier circuit includes resistance R11, resistance R10, resistance R20, resistance R42, electricity
Hold C17 and operational amplifier, the resistance R11 receives the first filter circuit output signal and exports to resistance R10 and computing and puts
3rd leads ends of big device, the resistance R20 receive the signal of the second filter circuit output and export to the of operational amplifier
Both ends connect the first leads ends and the 4th pin of operational amplifier respectively after four leads ends, the resistance R42 and capacitance C17 parallel connections
End, the 3rd leads ends of operational amplifier and the 4th leads ends are exported to the first leads ends, pass through the first of operational amplifier
Leads ends export signal, real by the effect between the effect between resistance R10 and resistance R11 and resistance R20 and resistance R42
Existing differential amplification provides voltage output differential amplification signal to signal output apparatus.
Further, the host MBUS receiving circuits further include filter amplification circuit, and the filter amplification circuit includes
By capacitance C5 the first filter amplifiers connected and the second filter amplifier, described C5 capacitances one end connects the first filter and amplification
The output terminal of device, the other end connect the noninverting input of the second filter amplifier, the input in the same direction of first filter amplifier
End receives the signal of prime filter difference amplifying circuit output, the first filter by resistance R36, the capacitance C13 and resistance R35 that connect
The reverse input end of twt amplifier is connected to the output terminal and electricity of the first filter amplifier by resistance R25 and capacitance C7 in parallel
Hold on the node between C5, the reverse input end of the first filter amplifier is grounded by resistance R46；Second filter and amplification
The noninverting input of device receives the output signal of capacitance C5 by resistance R16, resistance R24, capacitance C18, and second filtering is put
The output terminal of big device passes through resistance R27 and capacitance C6 feedback signals in parallel to the reverse input end of the second filter amplifier, institute
The reverse input end for stating the second filter amplifier is grounded by resistance R31.
Further, the signal output apparatus include voltage comparator and comparison circuit, the voltage comparator it is anti-
The output signal of prime filter difference amplifying circuit, the comparison circuit bag are received by resistance R40 and capacitance C15 to input terminal
It includes resistance R26 and resistance R30 and capacitance C8, the voltage that the resistance R26 receives power supply VCC30A offers is exported respectively to electricity
The noninverting input of R30 and voltage comparator is hindered, the noninverting input of voltage comparator is grounded by capacitance C8, the resistance
The other end ground connection of R30, the output terminal of the voltage comparator export signal to host receiving terminal.
Further, the signal output apparatus further includes the under-voltage circuit of signal, and the under-voltage circuit of signal includes string
The resistance R45 and resistance R47 of connection, diode D2, diode D4 and capacitance C19, the resistance R45 and resistance 47 receive power supply
The voltage of VCC30A offers is simultaneously connected to the cathode of diode D4, and the cathode of the diode D4 is grounded by capacitance C19, described
The anode of diode D4 is connected on the node between capacitance C15 and the reverse input end of voltage comparator, the diode D2
Cathode connect the reverse input end of voltage comparator, the plus earth of diode D2.
Host MBUS receiving circuits provided by the utility model make received signal in prime filter difference amplifying circuit and
It is exported after the multiple-stage filtering of filter amplification circuit and amplification through signal output apparatus to host side, signal is by multistage amplification and filter
Received signal strength can be improved after ripple, enhances signal robust, enhances the stability of signal output, is increased from node band load
Number, makes maximum node number at 2000 or more, so as to improve circuit load and receive the antijamming capability of signal, meets
In industrial environment application, improve communication rate.
Description of the drawings
Fig. 1 is the circuit flow graph of the utility model entirety；
Fig. 2 is the circuit diagram of the utility model entirety；
In figure：1st, prime filter difference amplifying circuit；2nd, filter amplification circuit；3rd, signal output apparatus.
Specific embodiment
Below in conjunction with whole attached drawing and specific embodiment to the host MBUS provided by the utility model applied to multinode
Receiving circuit is described in further detail.
As shown in Figure 1, the host MBUS receiving circuits include receiving the prime filter difference amplifying circuit 1 of signal, filter
Ripple amplifying circuit 2 and signal output apparatus 3.As shown in Fig. 2, the prime filter difference amplifying circuit 1 is filtered including prime
Circuit and differential amplifier circuit, wherein the prime filter circuit includes receiving the first filter circuit and the reception of high level signal
Second filter circuit of low level signal and the capacitance C14 of the first filter circuit of connection and the second filter circuit；Described first
Filter circuit includes resistance R12, capacitance C12, resistance R9, and the resistance R12 reception high level signals simultaneously pass through what is be connected in parallel
The other end ground connection of capacitance C12 and resistance R9 outputs, the resistance R9 and capacitance C12；Second filter circuit includes resistance
R21, capacitance C16 and resistance R23, the resistance R21 receive low level signal and pass through capacitance C16 in parallel and resistance R23 is defeated
Go out, the capacitance C16 and resistance R23 output other end ground connection；The differential amplifier circuit includes resistance R11, resistance R10, electricity
R20, resistance R42, capacitance C17 and operational amplifier are hindered, the resistance R11 receives the first filter circuit output signal and exports extremely
The other end ground connection of the 3rd leads ends VIN+ of resistance R10 and operational amplifier, the resistance R10, the resistance R20 are received
The signal of second filter circuit output is simultaneously exported to the 4th leads ends VIN-, the resistance R42 and capacitance C17 of operational amplifier
Both ends connect the first leads ends OUT and the 4th leads ends VIN- of operational amplifier, the operational amplifier the 3rd respectively after parallel connection
Leads ends VIN+ and the 4th leads ends VIN- are exported to the first leads ends OUT, by resistance R11 and resistance R20 and resistance R10 with
The differential amplification of signal is realized in effect between resistance R42, provides filtering of the voltage from the first leads ends OUT into the present embodiment
Amplifying circuit output difference amplified signal；The second pin end GND ground connection of the operational amplifier, the 5th leads ends VCC are received
The voltage that VCC30A power supplys provide.This circuit use high-accuracy filter difference amplifying circuit, the interference of effective suppression common mode signal,
The stability for receiving signal is improved, increases from node band and carries quantity.
As shown in Fig. 2, the filter amplification circuit 2 is included through capacitance C5 the first filter amplifier U2A to connect and the
Two filter amplifier U2B, described C5 capacitances one end connect the output terminal of the first filter amplifier U2A, the second filter of other end connection
The noninverting input of twt amplifier U2B, the first filter amplifier U2A receive the letter of prime filter difference amplifying circuit output
Number and pass through the second filter amplifier U2B amplification backward signal output circuit output signals；The first filter amplifier U2A
Noninverting input the signal that the differential amplifier circuit exports is received by the resistance R36, capacitance C13 and resistance R35 of series connection,
The reverse input end of the first filter amplifier U2A is connected to the first filter and amplification by resistance R25 and capacitance C7 in parallel
On node between device U2A output terminals and capacitance C5, the reverse input end of the first filter amplifier U2A is grounded by resistance R46,
The output terminal of the first filter amplifier U2A receives noninverting input and the signal of reverse input end passes through capacitance C5 to second
Filter amplifier U2B is exported；The noninverting input of the second filter amplifier U2B passes through resistance R16, resistance R24, capacitance
C18 receives the other end ground connection of the output signal of capacitance C5, the resistance R24 and capacitance C18, second filter amplifier
The output terminal of U2B by the reverse input end of in parallel resistance R27 and capacitance C6 feedback signals to the second filter amplifier U2B,
The reverse input end of the second filter amplifier U2B is grounded by resistance R31, the output of the second filter amplifier U2B
Reception noninverting input and the signal output of reverse input end are held to the resistance R40 of signal output apparatus and capacitance C15.This electricity
Road is amplified through multiple-stage filtering, effectively improves signal assignment, enhances signal robustness, is further increased bus and is carried number from node band
Amount.
As shown in Fig. 2, the signal output apparatus 3 includes voltage comparator U1B, comparison circuit and the under-voltage electricity of signal
Road, the reverse input end of the voltage comparator U1B receive the second filter amplifier U2B outputs by resistance R40 and capacitance C15
Hold the signal of output, the capacitance C15 is grounded by resistance R44, the comparison circuit include resistance R26 and resistance R30 and
Capacitance C8, the voltage that the resistance R26 receives power supply VCC30A offers are exported respectively to resistance R30's and voltage comparator U1B
Noninverting input, the noninverting input of voltage comparator U1B are grounded by capacitance C8, the other end ground connection of the resistance R30, institute
The output terminal for stating voltage comparator U1B exports signal to host receiving terminal；The under-voltage circuit of signal can provide partially for signal
Put voltage, the resistance R45 and resistance R47, diode D2, diode D4 and capacitance C19, the resistance R45 including series connection and
Resistance 47 receives the voltage that power supply VCC30A is provided and is connected to the cathode of diode D4, and the cathode of the diode D4 passes through
Capacitance C19 is grounded, and the anode of the diode D4 is connected to the node between capacitance C15 and the reverse input end of voltage comparator
On, the cathode of the diode D2 connects the reverse input end of voltage comparator, the plus earth of diode D2.
The operation principle of the utility model：As shown in Figure 1, the signal that the utility model receiving host transmitting terminal is sent passes through
The filtering of prime filter circuit is sent to differential amplifier circuit and is amplified by operational amplifier, so as to improve reception signal
Stability, the interference of suppression common mode signal and noise, through differential amplifier circuit conveying the filtered amplifying circuit of signal in
The multiple-stage filtering of first filter amplifier and the second filter amplifier amplifies, and can effectively improve received signal strength and enhancing
Signal robustness enhances the stability of signal output, further increases bus and carries quantity from node band, final signal is delivered to letter
Number output circuit provides bias voltage by the under-voltage circuit of signal, and by and the 5th leads ends of voltage comparator benchmark
Level receives signal compared to output host more afterwards.
Embodiment described above is only that the preferred embodiment of the utility model is described, not to this practicality
New scope is defined, and on the premise of the spirit of the design of the utility model is not departed from, those of ordinary skill in the art are to this
The various modifications and improvement that the technical solution of utility model is made should all fall into the guarantor that claims of the utility model determine
In the range of shield.
Claims (4)
1. a kind of host MBUS receiving circuits applied to multinode, which is characterized in that the prime filtering including receiving signal is poor
Divide amplifying circuit (1) and signal output apparatus (3), the prime filter difference amplifying circuit (1) includes prime filter circuit
And differential amplifier circuit, the prime filter circuit include the first filter circuit for receiving high level signal and receive low level letter
Number the second filter circuit and connection the first filter circuit and the second filter circuit capacitance C14, first filter circuit
Including resistance R12, capacitance C12, resistance R9, the resistance R12 receive high level signal and pass through the capacitance C12 being connected in parallel and
Resistance R9 is exported；Second filter circuit includes resistance R21, capacitance C16 and resistance R23, the resistance R21 receive low level
Signal simultaneously passes through capacitance C16 in parallel and resistance R23 outputs；The differential amplifier circuit includes resistance R11, resistance R10, resistance
R20, resistance R42, capacitance C17 and operational amplifier, the resistance R11 receive the first filter circuit output signal and export to electricity
The 3rd leads ends (VIN+) of R10 and operational amplifier are hindered, the signal of the resistance R20 receptions the second filter circuit output is simultaneously defeated
Go out to the 4th leads ends (VIN-) of operational amplifier, concatenation operation is put respectively at both ends after the resistance R42 and capacitance C17 parallel connections
The first leads ends (OUT) and the 4th leads ends (VIN-) of big device, the first leads ends (OUT) output letter of the operational amplifier
Number.
2. host MBUS receiving circuits according to claim 1, which is characterized in that the host MBUS receiving circuits are also wrapped
Include filter amplification circuit (2), the filter amplification circuit is included through capacitance C5 the first filter amplifiers (U2A) connected and the
Two filter amplifiers (U2B), resistance R36, the capacitance that the noninverting input of first filter amplifier (U2A) passes through series connection
C13 and resistance R35 receives the signal of prime filter difference amplifying circuit output, the reversed input of the first filter amplifier (U2A)
End is connected to the section between the output terminal of the first filter amplifier (U2A) and capacitance C5 by resistance R25 and capacitance C7 in parallel
On point, the reverse input end of the first filter amplifier (U2A) is grounded by resistance R46；Second filter amplifier (U2B)
Noninverting input receives the output signal of capacitance C5, second filter amplifier by resistance R16, resistance R24, capacitance C18
(U2B) the reversed input that output terminal passes through resistance R27 and capacitance C6 feedback signals in parallel to the second filter amplifier (U2B)
End, the reverse input end of second filter amplifier (U2B) are grounded by resistance R31.
3. host MBUS receiving circuits according to claim 1, which is characterized in that the signal output apparatus includes voltage
Comparator (U1B) and comparison circuit, the reverse input end of the voltage comparator (U1B) are received by resistance R40 and capacitance C15
The output signal of differential amplifier circuit, the comparison circuit include resistance R26 and resistance R30 and capacitance C8, the resistance R26
The voltage that reception power supply VCC30A is provided exports the noninverting input to resistance R30 and voltage comparator (U1B), voltage ratio respectively
Noninverting input compared with device (U1B) is grounded by capacitance C8, the other end ground connection of the resistance R30, the voltage comparator
(U1B) output terminal exports signal to host receiving terminal.
4. host MBUS receiving circuits according to claim 3, which is characterized in that the signal output apparatus further includes letter
Number under-voltage circuit, the under-voltage circuit of signal include the resistance R45 of series connection and resistance R47, diode D2, diode D4 and electricity
Hold C19, the resistance R45 and resistance 47 receive the voltage that power supply VCC30A is provided and is connected to the cathode of diode D4, described
The cathode of diode D4 is grounded by capacitance C19, and the anode of the diode D4 is connected to capacitance C15 and voltage comparator
(U1B) on the node between reverse input end, the cathode of the diode D2 connects the reversed input of voltage comparator (U1B)
End, the plus earth of diode D2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721197008.7U CN207458323U (en) | 2017-09-18 | 2017-09-18 | A kind of host MBUS receiving circuits applied to multinode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721197008.7U CN207458323U (en) | 2017-09-18 | 2017-09-18 | A kind of host MBUS receiving circuits applied to multinode |
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| Publication Number | Publication Date |
|---|---|
| CN207458323U true CN207458323U (en) | 2018-06-05 |
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ID=62283293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721197008.7U Active CN207458323U (en) | 2017-09-18 | 2017-09-18 | A kind of host MBUS receiving circuits applied to multinode |
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| CN (1) | CN207458323U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516410A (en) * | 2017-09-18 | 2017-12-26 | 合肥瑞纳表计有限公司 | A kind of main frame MBUS receiving circuits applied to multinode |
-
2017
- 2017-09-18 CN CN201721197008.7U patent/CN207458323U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516410A (en) * | 2017-09-18 | 2017-12-26 | 合肥瑞纳表计有限公司 | A kind of main frame MBUS receiving circuits applied to multinode |
| CN107516410B (en) * | 2017-09-18 | 2024-05-03 | 瑞纳智能设备股份有限公司 | Be applied to host computer MBUS receiving circuit of multinode |
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