CN202948026U - Differential capacitance voltage conversion circuit and acceleration sensor detection system - Google Patents
Differential capacitance voltage conversion circuit and acceleration sensor detection system Download PDFInfo
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- CN202948026U CN202948026U CN 201220633470 CN201220633470U CN202948026U CN 202948026 U CN202948026 U CN 202948026U CN 201220633470 CN201220633470 CN 201220633470 CN 201220633470 U CN201220633470 U CN 201220633470U CN 202948026 U CN202948026 U CN 202948026U
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Abstract
The utility model discloses a differential capacitance voltage conversion circuit and an acceleration sensor detection system. The differential capacitance voltage conversion circuit is used for converting a capacitance differential value into a voltage differential value and comprises a clock signal source for generating a clock signal, a sampling circuit and a differential amplification circuit, the differential amplification circuit comprises a differential amplifier, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the sampling circuit comprises a first reference capacitor, a second reference capacitor, a first sampling output end and a second sampling output end, and two conducting loops are formed by the components. An acceleration sensor detection system using the differential capacitance voltage conversion circuit is further disclosed. The differential capacitance voltage conversion circuit and the acceleration sensor detection system overcome external interferences and noise through a differential circuit mode, utilize different conductive paths to eliminate voltage excursion and noise of the amplifier, and improve sampling precision and sensitivity.
Description
Technical field
The utility model relates to a kind of differential type convert of capacitor to voltage circuit and acceleration transducer detection system.
Background technology
At present a lot of acceleration transducers adopt the change of electric capacity to characterize the acceleration of the displacement of acceleration transducer place object.The for example capacitance Cs 1 of the both sides that consists of of the central shaft of acceleration transducer and the variation that CS2 can produce capacitance along with the variation of the speed that detects, for example, CS1+ Δ C and CS2-Δ C or CS1-Δ C and CS2+ Δ C.The size and Orientation of this variation is the size and Orientation of the acceleration of the sensor that accelerates.
In other words, acceleration transducer changes into positive and negative electric capacity difference to the size and Orientation of speed, if the positive electricity tolerance represents CS1-CS2, that negative capacitance difference is exactly CS2-CS1.And the electric capacity difference of this reflection acceleration magnitude and direction can't directly directly be processed by treatment circuit subsequently.
The electric capacity difference that is to say described reflection acceleration magnitude and direction need to be converted into could pass through back-end circuit after voltage and process and obtain an application result that represents acceleration.
A lot of existing convert of capacitor to voltage circuit design still adopt the single-ended signal design at present, thus can't overcome the impact of external disturbance and noise, thus reduced sampling precision and the sensitivity of acceleration transducer.And the variation of the device self such as voltage amplifier and sampling precision and the sensitivity that noise has limited acceleration transducer further in existing convert of capacitor to voltage circuit.
The utility model content
The technical problems to be solved in the utility model is for the low precision of the convert of capacitor to voltage circuit that overcomes prior art and the defective of muting sensitivity, a kind of differential type convert of capacitor to voltage circuit is provided, overcome the impact of external disturbance and noise by the mode of difference channel, and utilize clock signal to come variation and the noise of erase amplifier self at different conductive paths, thereby improve sampling precision and the sensitivity of acceleration transducer.
The utility model solves above-mentioned technical matters by following technical proposals:
The utility model provides a kind of differential type convert of capacitor to voltage circuit, be used for an electric capacity difference is converted into a voltage difference, be characterized in, described convert of capacitor to voltage circuit comprises a clock signal source, a sample circuit and a differential amplifier circuit that generates a clock signal;
Described differential amplifier circuit comprises a differential amplifier, one first electric capacity, one second electric capacity, one the 3rd electric capacity and one the 4th electric capacity; Described sample circuit comprises one first reference capacitance, one second reference capacitance, one first sampling output terminal and one second sampling output terminal;
When described clock signal was high level or low level, described differential amplifier circuit comprised following conductive path:
The positive input terminal of described differential amplifier and negative input end are respectively by described the first electric capacity and described the 3rd electric capacity access one reference voltage; The positive input terminal of described differential amplifier and negative output terminal are electrically connected to; The negative input end of described differential amplifier and positive output end are electrically connected to;
Described sample circuit comprises following conductive path:
Described the first reference capacitance, the first sampling output terminal and one first testing capacitance are serially connected with between a VDD-to-VSS successively, described the second reference capacitance, the second sampling output terminal and one second testing capacitance be serially connected with successively and described power supply between; Described the first sampling output terminal and the second sampling output terminal all are electrically connected to described reference voltage;
When described clock signal was anti-phase, described differential amplifier circuit comprised following conductive path:
The positive input terminal of described differential amplifier and described first is sampled and is connected in series described the first electric capacity between output terminal, is connected in series described the 3rd electric capacity between the negative input end of described differential amplifier and described the second sampling output terminal; Be connected in series described the second electric capacity between the negative output terminal of described first sampling output terminal and described differential amplifier, described second samples is connected in series described the 4th electric capacity between the positive output end of output terminal and described differential amplifier;
Described sample circuit comprises following conductive path:
Described the first reference capacitance, the first sampling output terminal and one first testing capacitance be serially connected with successively and described power supply between, described the second reference capacitance, the second sampling output terminal and one second testing capacitance also are serially connected with between described VDD-to-VSS successively.
Described differential signal is exactly the signal of two equal amplitude opposite phases.Difference between these two signals is exactly differential signal.Owing to can appearing at simultaneously on these two fully differential signal wires, so can cancel each other for external interference and noise.Can obtain at last better CMRR(common-mode rejection ratio) and the PSRR(Power Supply Rejection Ratio).So utilize the pattern of differential signal to carry out the conversion of capacitance voltage in the utility model, thereby eliminate external interference and noise.Improve the sensitivity that detects.
Wherein the utility model is when arbitrary state of clock signal and during rp state, correspond respectively to the sampling conductive path and amplify conductive path, specifically, for example when the clock signal during at high level, by coming at the first sampling output terminal and the second sampling output terminal access reference voltage capacitor charging to be measured to reference voltage, thereby realize sampling to testing capacitance.When the clock signal inversion is low level, realize differential amplification to the electric capacity difference of testing capacitance by the first sampling output terminal and the second sampling output terminal access differential amplifier.
And remove by the first electric capacity and the 3rd electric capacity zero migration and the low-frequency noise that differential amplifier self exists in the utility model in differential amplifier circuit.Specifically, for example, when the high level of clock signal, namely in the process to the electric capacity sampling, the conductive path that consists of by differential amplifier gathers zero migration and low-frequency noise, and clock signal is anti-phase when being low level, namely in the process to the sampled signal differential amplification, add differential amplifier to eliminate zero migration and the low-frequency noise of differential amplifier self zero migration and low-frequency noise.
Preferably, described differential amplifier circuit also comprises one first differential amplifier, one the 5th electric capacity, one the 6th electric capacity, one the 7th electric capacity and one the 8th electric capacity;
When described clock signal was high level or low level, described differential amplifier circuit also comprised following conductive path:
The positive input terminal of described the first differential amplifier and negative input end are respectively by described the 5th electric capacity and described the 7th described reference voltage of electric capacity access; The positive input terminal of described the first differential amplifier and negative input end also are electrically connected to described reference voltage; The positive input terminal of described the first differential amplifier and negative output terminal are electrically connected to; The negative input end of described the first differential amplifier and positive output end are electrically connected to;
When described clock signal was anti-phase, described differential amplifier circuit also comprised following conductive path:
Be connected in series described the 5th electric capacity between the positive input terminal of described the first differential amplifier and the negative output terminal of described differential amplifier, be connected in series described the 7th electric capacity between the negative input end of described the first differential amplifier and the positive output end of described differential amplifier; Be connected in series described the 6th electric capacity between the negative output terminal of the positive input terminal of described the first differential amplifier and described the first differential amplifier, be connected in series described the 8th electric capacity between the positive output end of the negative input end of described the first differential amplifier and described the first differential amplifier.
The utility model meets the demand of subsequent conditioning circuit or equipment more by the differential signal that the output of differential amplifier is amplified further make final acquisition.
Wherein the magnitude of voltage of reference voltage described in the present embodiment is half of magnitude of voltage of described power supply.
For the ease of the calculating of the differential voltage value of whole differential type convert of capacitor to voltage circuit output, the magnitude of voltage of described reference voltage preferably is set to half of magnitude of voltage of described power supply.
The utility model also provides a kind of acceleration transducer detection system, comprise an acceleration transducer, be characterized in, described acceleration transducer detection system also comprises differential type convert of capacitor to voltage circuit as above, and wherein said differential type convert of capacitor to voltage circuit is converted into voltage difference with the electric capacity difference of described acceleration transducer.
Preferably, described acceleration transducer is the MEMS(MEMS (micro electro mechanical system)) acceleration transducer.
Characterize acceleration, especially the MEMS acceleration transducer of its place object due to the change of the electric capacity of acceleration transducer employing at present.The capacitance Cs 1 of MEMS acceleration transducer both sides and CS2 can produce along with the variation of detection speed the variation of capacitance, for example CS1+ Δ C and CS2-Δ C or CS1-Δ C and CS2+ Δ C.The size and Orientation of this variation is the size and Orientation of the acceleration of sensor.In other words, acceleration transducer changes into positive and negative electric capacity difference to the size and Orientation of speed, if the positive electricity tolerance represents CS1-CS2, that negative capacitance difference is exactly CS2-CS1.The electric capacity difference of this reflection acceleration magnitude and direction need to be converted into could pass through back-end circuit after voltage and process application result that represents acceleration of acquisition.So the utility model with differential type convert of capacitor to voltage circuit application in acceleration transducer, thereby but the electric capacity difference that realizes characterizing acceleration is converted into the voltage difference of back-end circuit processing.
On the basis that meets this area general knowledge, above-mentioned each optimum condition, but combination in any namely get each preferred embodiments of the utility model.
Positive progressive effect of the present utility model is:
Differential type convert of capacitor to voltage circuit of the present utility model utilizes the mode of difference channel to reduce common mode interference, and the error that causes as switch and the noise that comes by chip substrate or power lead coupling are so can improve signal and noise proportional.In addition, sensitivity and dynamic range also can increase to some extent.
The different conductive path that the utility model consists of constantly based on clock signal is realized the two kinds of circuit of amplification to the sampling of electric capacity and signal, and in the electric capacity sampling process, to gather and eliminate variation and the noise of differential amplifier self, thereby improve further sampling precision and the sensitivity of acceleration transducer.
Description of drawings
Fig. 1 is the electrical block diagram of the preferred embodiment of acceleration transducer detection system of the present utility model.
Embodiment
Mode below by embodiment further illustrates the utility model, but therefore the utility model is not limited among described scope of embodiments.
As shown in Figure 1, by a differential type convert of capacitor to voltage circuit, the electric capacity difference of capacitor C S1 and capacitor C S2 in one MEMS acceleration transducer 3 is converted into voltage difference in the acceleration transducer detection system of the present embodiment.
Specifically, as shown in Figure 1, described differential type convert of capacitor to voltage circuit comprises a sample circuit 1, a differential amplifier circuit 2 and a clock signal source (not showing in Fig. 1).
Described signal source of clock generates a clock signal, when wherein described clock signal is high level in the present embodiment, and all switch P 1 conductings, all switch P 2 disconnect.When described clock signal is anti-phase when being low level, all switch P 1 disconnect, all switch P 2 conductings.Wherein all switch P 1 and switch P 2 can be circuit component, device or the unit that switching tube etc. can be realized switch.
Described switch P 1 also can conducting when clock signal is low level in addition, and described switch P 2 is all conductings when the inversion signal of the signal that makes switch P 1 conducting.
The present embodiment is realized two different conductive paths at described sample circuit 1 and differential amplifier circuit 2, thereby is realized in the present embodiment, the electric capacity difference being converted into the function of voltage difference by conducting and the disconnection of all switch P 1 and all switch P 2.
Use capacitor C R1 as the reference capacitance of the capacitor C S1 of MEMS acceleration transducer 3 in wherein said sample circuit 1, use capacitor C R2 as the reference capacitance of capacitor C S2.
As shown in Figure 1, thus in the present embodiment when all switch P 1 conducting switch P 2 disconnects, the conductive path of described sample circuit 1 is:
Described power vd D is capacitor C R1, sampling end CP and the capacitor C S1 ground connection by being connected in series successively both, also capacitor C R2, sampling end CM and the capacitor C S2 ground connection by being connected in series successively.And described sampling end CP and sampling end CP all be electrically connected to reference voltage VCM, and the magnitude of voltage of described reference voltage VCM is half of magnitude of voltage of power vd D.
That is to say, capacitor C R1 and capacitor C R2 are connected to power vd D, and capacitor C S1 and capacitor C S2 are connected to ground.The reference voltage VCM=VDD/2 that sampling end CP and sampling end CP are connected to.Therefore, in this stage, capacitor C S1 and capacitor C S2 are charged to VDD/2, and capacitor C R1 and capacitor C R1 are charged to-VDD/2.Being stored in the voltage difference that charge Q in any capacitor all equals capacitance and electric capacity two ends multiplies each other.Q=C*V。Wherein C is capacitance, and V is the voltage difference at electric capacity two ends.
Differential amplifier circuit described in the present embodiment 2 is two-stage amplifier, and wherein first order amplifier comprises a differential amplifier U1, capacitor C AZ1, capacitor C AZ2, capacitor C F1 and capacitor C F2.Second level amplifier comprises a differential amplifier U2, capacitor C gi1, capacitor C gi2, capacitor C gf1 and capacitor C gf2.
Equally when so all switch P 1 conducting switch P 2 disconnects, described differential amplifier circuit 2 and described sample circuit 1 disconnect fully, also disconnect fully between the first order amplifier of same described differential amplifier circuit 2 and second level amplifier, so do not have the phase mutual interference between described sample circuit 1, first order amplifier and second level amplifier.
And the conductive path of first order amplifier is at this moment:
The positive input terminal of described differential amplifier U1 is by described capacitor C AZ1 access reference voltage VCM, and the negative input end of described differential amplifier U1 is by described capacitor C AZ2 access reference voltage VCM.The positive input terminal of described differential amplifier U1 and negative output terminal Voutn1 are electrically connected to, and the negative input end of described differential amplifier U1 and positive output end Voutp1 are electrically connected to.
Can leave the zero migration of differential amplifier U1 and low-frequency noise respectively in capacitor C AZ1 and capacitor C AZ2 this moment.The zero migration of differential amplifier U1 and low frequency noise like this can be deleted in the amplification process to the sampled voltage of sample circuit 1 output.So the present embodiment is made output bias to zero migration and low frequency noise by capacitor C AZ1 and capacitor C AZ2, thereby in the amplification process to the sampled voltage of sample circuit 1 output after this, will cancel each other because this leaves zero migration and the low frequency noise that zero migration in capacitor C AZ1 and capacitor C AZ2 and low frequency noise and described differential amplifier U1 occurs in advance in the amplification process to the sampled voltage of sample circuit 1 output.Therefore, the zero migration of described differential amplifier U1 and low frequency noise have also fallen with regard to deleted the impact of output.
Equally, the conductive path in the amplifier of the described second level is:
The positive input terminal of described differential amplifier U2 is by the described reference voltage VCM of capacitor C gi1 access, and the negative input end of described differential amplifier U2 is by the described reference voltage VCM of capacitor C gi2 access.And the positive input terminal of described differential amplifier U2 and negative input end also are electrically connected to described reference voltage VCM.The positive input terminal of described differential amplifier U2 and negative output terminal Voutn2 are electrically connected to, and the negative input end of described differential amplifier U2 and positive output end Voutp2 electrical connection.
This moment, second level amplifier was identical with the principle of the first amplifier, and the variation etc. of himself is proofreaied and correct, and concrete principle please refer to first order amplifier, just repeats no more herein.
As mentioned above, in 1 conducting of all switch P, when all switch P 2 disconnected, capacitor C S1 and capacitor C S2 in 1 pair of acceleration transducer of the sample circuit of the present embodiment sampled, and first order amplifier and the second level amplifier in differential amplifier circuit 2 carries out the corrections such as variation simultaneously.And prevent crosstalking etc. between each circuit by the first order amplifier in isolation sample circuit 1 and differential amplifier circuit 2 and second level amplifier.
Working as all switch P 1 in the present embodiment disconnects, during all switch P 2 conducting, described sample circuit 1 is connected with second level amplifier electric with first order amplifier during differential amplifier circuit is connected, so the capacitor C S1 that described sample circuit 1 is gathered and the difference of capacitor C S2 transform and be enlarged into voltage difference.
Specifically, when all switch P 1 disconnect, during all switch P 2 conducting, the conductive path in described sample circuit 1 is:
Described power vd D is capacitor C S1, sampling end CP and the capacitor C R1 ground connection by being connected in series successively both, also capacitor C S2, sampling end CM and the capacitor C R2 ground connection by being connected in series successively.And described sampling end CP is electrically connected to the positive input terminal of differential amplifier U1 by capacitor C AZ1.Described sampling end CM is electrically connected to the negative input end of differential amplifier U1 by capacitor C AZ2.
Be that capacitor C R1 and capacitor C R2 are connected to ground, and capacitor C S1 and capacitor C S2 are connected to power vd D.Due in 1 conducting of all switch P, when all switch P 2 disconnected, described sampling end CP and sampling end CM be controlled in VCM=VDD/2.According to the principle of charge conservation, electric charge should remain unchanged on described sampling end CP and sampling end CM.Therefore, in capacitor C S1 and capacitor C R1, charge differences (Qcs1-Qcr1) is transferred to capacitor C F1 at this moment.The charge differences of capacitor C S2 and capacitor C R2 (Qcs2 – Qcr2) is transferred to capacitor C F2 at this moment.When if in the present embodiment, the capacitance of capacitor C R1 equals the capacitance of capacitor C R2, in fact the electric charge difference between final described capacitor C F1 and capacitor C F2 is exactly differential charge (Qcs1-Qcr1)-(Qcs2-Qcr2)=(Qcs1-Qcs2).
Equally, when all switch P 1 disconnect, during all switch P 2 conducting, also be electrically connected to fully between the first order amplifier of described differential amplifier circuit 2 and second level amplifier.
The conductive path of wherein said first order amplifier is:
Be connected in series described capacitor C AZ1 between the positive input terminal of described differential amplifier U1 and described sampling end CP, be connected in series described capacitor C AZ2 between the negative input end of described differential amplifier U1 and described sampling end CM.Be connected in series described capacitor C F1 between the negative output terminal Voutn1 of described sampling end CP and described differential amplifier U1, be connected in series described capacitor C F2 between the positive output end Voutp1 of described sampling end CM and described differential amplifier U1.
This moment, the conductive path of first order amplifier was exactly the amplifying circuit of existing differential amplifier, so according to the amplification principle of differential amplifier, the positive output end Voutp1 of described differential amplifier U1 is output as:
Voutp1＝(VDD×(CS1-CR1)+CF2×VCM)/CF2
The negative output terminal Voutn1 of described differential amplifier U1 is output as:
Voutn1＝(VDD×(CS2-CR2)+CF1×VCM)/CF1
If the capacitance of the F1 of capacitor C described in the present embodiment equals the capacitance of capacitor C F2, when being CF1=CF2=CF, the voltage difference Δ Vout1 that can obtain obtaining by described first order amplifier by above-mentioned formula is: Δ Vout1=(Voutp1-Voutn1)=(VDD * (CS1-CS2))/CF
If when Δ C is defined as the electric capacity difference of capacitor C S1 and capacitor C S2, namely during Δ C=CS1-CS2, can obtain Δ Vout1=VDD * Δ C/CF
In like manner this moment, the conductive path of described second level amplifier is:
Be connected in series described capacitor C gi1 between the negative output terminal Voutn1 of the positive input terminal of described differential amplifier U2 and described differential amplifier U1, be connected in series described capacitor C gi2 between the negative output terminal Voutp1 of the negative input end of described differential amplifier U2 and described differential amplifier U1.Be connected in series described capacitor C gf1 between the negative output terminal Voutn2 of the positive input terminal of described differential amplifier U2 and described differential amplifier U2, be connected in series described capacitor C gf2 between the positive output end Voutp2 of the negative input end of described differential amplifier U2 and described differential amplifier U2.
Equally, this moment, the conductive path of described second level amplifier was also the amplifying circuit of existing differential amplifier, if this moment, the capacitance of described capacitor C gi1 was identical with the capacitance of capacitor C gi2, be Cgi1=Cgi2=Cgi, the capacitance of described capacitor C gf1 is identical with the capacitance of capacitor C gf2, i.e. Cgf1=Cgf2=Cgf.So according to the amplification principle of differential amplifier and at the specifically described Computing Principle of described first order amplifier, the voltage difference Δ Vout2 that can obtain final output is:
ΔVout2＝(Voutp2-Voutn2)＝VDD×(ΔC/CF)×(Cgi/Cgf)
Can find out that from above-mentioned formula this differential output voltage Δ Vout2 is that electric capacity difference DELTA C with acceleration transducer is directly proportional.So Δ Vout2 can characterize the variation of the electric capacity difference DELTA C of acceleration transducer, and the form of the differential amplification in employing the present embodiment, and the mode of the isolation of amplifying circuit and sample circuit, reduce disturbance and noise effectively.
The above is only preferred implementation of the present utility model; should be pointed out that for those skilled in the art, without departing from the concept of the premise utility; can also make some improvements and modifications, these improvements and modifications also should be considered as in the utility model protection domain.
Claims (4)
1. a differential type convert of capacitor to voltage circuit, be used for an electric capacity difference is converted into a voltage difference, it is characterized in that, described convert of capacitor to voltage circuit comprises a clock signal source, a sample circuit and a differential amplifier circuit that generates a clock signal;
Described differential amplifier circuit comprises a differential amplifier, one first electric capacity, one second electric capacity, one the 3rd electric capacity and one the 4th electric capacity; Described sample circuit comprises one first reference capacitance, one second reference capacitance, one first sampling output terminal and one second sampling output terminal;
When described clock signal was high level or low level, described differential amplifier circuit comprised following conductive path: the positive input terminal of described differential amplifier and negative input end are respectively by described the first electric capacity and described the 3rd electric capacity access one reference voltage; The positive input terminal of described differential amplifier and negative output terminal are electrically connected to; The negative input end of described differential amplifier and positive output end are electrically connected to;
Described sample circuit comprises following conductive path:
Described the first reference capacitance, the first sampling output terminal and one first testing capacitance are serially connected with between a VDD-to-VSS successively, described the second reference capacitance, the second sampling output terminal and one second testing capacitance be serially connected with successively and described power supply between; Described the first sampling output terminal and the second sampling output terminal all are electrically connected to described reference voltage;
When described clock signal was anti-phase, described differential amplifier circuit comprised following conductive path:
The positive input terminal of described differential amplifier and described first is sampled and is connected in series described the first electric capacity between output terminal, is connected in series described the 3rd electric capacity between the negative input end of described differential amplifier and described the second sampling output terminal; Be connected in series described the second electric capacity between the negative output terminal of described first sampling output terminal and described differential amplifier, described second samples is connected in series described the 4th electric capacity between the positive output end of output terminal and described differential amplifier;
Described sample circuit comprises following conductive path:
Described the first reference capacitance, the first sampling output terminal and one first testing capacitance be serially connected with successively and described power supply between, described the second reference capacitance, the second sampling output terminal and one second testing capacitance also are serially connected with between described VDD-to-VSS successively.
2. differential type convert of capacitor to voltage circuit as claimed in claim 1, is characterized in that, described differential amplifier circuit also comprises one first differential amplifier, one the 5th electric capacity, one the 6th electric capacity, one the 7th electric capacity and one the 8th electric capacity;
When described clock signal was high level or low level, described differential amplifier circuit also comprised following conductive path:
The positive input terminal of described the first differential amplifier and negative input end are respectively by described the 5th electric capacity and described the 7th described reference voltage of electric capacity access; The positive input terminal of described the first differential amplifier and negative input end also are electrically connected to described reference voltage; The positive input terminal of described the first differential amplifier and negative output terminal are electrically connected to; The negative input end of described the first differential amplifier and positive output end are electrically connected to;
When described clock signal was anti-phase, described differential amplifier circuit also comprised following conductive path:
Be connected in series described the 5th electric capacity between the positive input terminal of described the first differential amplifier and the negative output terminal of described differential amplifier, be connected in series described the 7th electric capacity between the negative input end of described the first differential amplifier and the positive output end of described differential amplifier; Be connected in series described the 6th electric capacity between the negative output terminal of the positive input terminal of described the first differential amplifier and described the first differential amplifier, be connected in series described the 8th electric capacity between the positive output end of the negative input end of described the first differential amplifier and described the first differential amplifier.
3. acceleration transducer detection system, comprise an acceleration transducer, it is characterized in that, described acceleration transducer detection system also comprises differential type convert of capacitor to voltage circuit as claimed in claim 1 or 2, and wherein said differential type convert of capacitor to voltage circuit is used for the electric capacity difference of described acceleration transducer is converted into voltage difference.
4. acceleration transducer detection system as claimed in claim 3, is characterized in that, described acceleration transducer is the MEMS acceleration transducer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220633470 CN202948026U (en) | 2012-11-26 | 2012-11-26 | Differential capacitance voltage conversion circuit and acceleration sensor detection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220633470 CN202948026U (en) | 2012-11-26 | 2012-11-26 | Differential capacitance voltage conversion circuit and acceleration sensor detection system |
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| CN202948026U true CN202948026U (en) | 2013-05-22 |
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| CN 201220633470 Withdrawn - After Issue CN202948026U (en) | 2012-11-26 | 2012-11-26 | Differential capacitance voltage conversion circuit and acceleration sensor detection system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981021A (en) * | 2012-11-26 | 2013-03-20 | 微动科技（杭州）有限公司 | Differential capacitance-voltage conversion circuit and acceleration sensor detection system |
| CN103245840A (en) * | 2013-05-23 | 2013-08-14 | 成都国腾电子技术股份有限公司 | Port multiplexing interface circuit for capacitive sensor |
| CN103308721A (en) * | 2013-07-04 | 2013-09-18 | 中国科学院地质与地球物理研究所 | Capacitance reading circuit of inertia detecting element |
| CN108064344A (en) * | 2017-11-20 | 2018-05-22 | 深圳市汇顶科技股份有限公司 | Difference channel, capacitive detection circuit, touch detecting apparatus and terminal device |
-
2012
- 2012-11-26 CN CN 201220633470 patent/CN202948026U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981021A (en) * | 2012-11-26 | 2013-03-20 | 微动科技（杭州）有限公司 | Differential capacitance-voltage conversion circuit and acceleration sensor detection system |
| CN103245840A (en) * | 2013-05-23 | 2013-08-14 | 成都国腾电子技术股份有限公司 | Port multiplexing interface circuit for capacitive sensor |
| CN103245840B (en) * | 2013-05-23 | 2015-09-16 | 成都振芯科技股份有限公司 | A kind of multiplexed port interface circuit for capacitance type sensor |
| CN103308721A (en) * | 2013-07-04 | 2013-09-18 | 中国科学院地质与地球物理研究所 | Capacitance reading circuit of inertia detecting element |
| CN108064344A (en) * | 2017-11-20 | 2018-05-22 | 深圳市汇顶科技股份有限公司 | Difference channel, capacitive detection circuit, touch detecting apparatus and terminal device |
| WO2019095377A1 (en) * | 2017-11-20 | 2019-05-23 | 深圳市汇顶科技股份有限公司 | Differential circuit, capacitance detection circuit, touch detection apparatus and terminal device |
| EP3514553A4 (en) * | 2017-11-20 | 2019-10-02 | Shenzhen Goodix Technology Co., Ltd. | Differential circuit, capacitance detection circuit, touch detection apparatus and terminal device |
| US10627959B2 (en) | 2017-11-20 | 2020-04-21 | Shenzhen GOODIX Technology Co., Ltd. | Differential circuit, capacitance detection circuit, touch detection device and terminal device |
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