CN107505485B - Contact probe, semiconductor device testing apparatus, and semiconductor device testing method - Google Patents
Contact probe, semiconductor device testing apparatus, and semiconductor device testing method Download PDFInfo
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- CN107505485B CN107505485B CN201710286564.XA CN201710286564A CN107505485B CN 107505485 B CN107505485 B CN 107505485B CN 201710286564 A CN201710286564 A CN 201710286564A CN 107505485 B CN107505485 B CN 107505485B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
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Abstract
The invention realizes low resistance contact with respect to a pad of a semiconductor element. The semiconductor element testing device is provided with a contact probe (12), and the contact probe (12) is contacted with an emitter bonding pad (1b) when a semiconductor element (1) placed on a testing table (11) is tested. The contact probe (12) is held on the contact block (14) in a state of being separated from the plunger pin (18), and after the contact block (14) is lowered, the contact probe (12) is first allowed to stand by itself on the emitter pad (1b) of the semiconductor element (1). Then, when the contact block (14) is lowered, 1 of the plunger pins (18) comes into contact with the protrusion (12d) of the contact probe (12), and thereafter, the other plunger pins (18) come into contact with the 1 st contact surface (12b) around the protrusion (12 d). The contact probe (12) can realize low-resistance contact by keeping the parallelism with the semiconductor element (1) even if the contact probe is inclined to the emitter pad (1 b).
Description
Technical Field
The present invention relates to a contact probe used for a dynamic characteristic test of a semiconductor device (chip), a semiconductor device testing apparatus, and a semiconductor device testing method.
Background
A semiconductor device testing apparatus for testing dynamic characteristics of a semiconductor device is known, and generally includes a test circuit, a contact block, a contact pin, and a test stand (see, for example, patent document 1). The contact block is a component serving as a unit for electrically connecting a test circuit and a semiconductor element on a test stage, and has a placement tray and a base unit. The placing tray is located above a test stage on which semiconductor elements are placed, and holds a plurality of contact pins as contact probes to be brought into contact with the semiconductor elements. One side of the base unit is connected to a wiring connected to a test circuit, and the other side holds a plurality of plunger pins which are in contact with the other side in a state where a load is applied to the contact pins.
When the semiconductor element is a power device such as an IGBT (Insulated Gate Bipolar Transistor), the semiconductor element includes a Gate pad, an emitter pad, and a collector pad. In the test, the contact pins are brought into contact with the gate pad and the emitter pad of the semiconductor element, and the electrodes of the test circuit provided on the test stage are brought into contact with the collector pad. In the case where the Semiconductor element is a Metal-Oxide-Semiconductor Field-effect transistor (MOSFET), the contact pin is brought into contact with the gate pad and the emitter pad, and the electrode of the test table is brought into contact with the drain pad. In the case where the semiconductor is an FWD (Free Wheeling Diode), the contact pin is brought into contact with the cathode pad, and the electrode of the test stand is brought into contact with the anode pad.
Here, the contact pin is used as a contact probe because when a semiconductor element is broken, a melt of the semiconductor element (silicon or the like) adheres to the tip of the probe, and therefore the probe must be replaced. Thus, the placement tray holding the contact pins is provided to be detachable on the base unit. When the contact pin needs to be replaced, the placing disc is detached from the base unit, the damaged contact pin is replaced by a good contact pin, and the contact pin is installed on the base unit again.
In a test of the semiconductor device testing apparatus, first, a semiconductor device is placed at a predetermined position on a test table, and a contact block is lowered to an arbitrary position by an up-down operation mechanism, thereby bringing a contact pin into contact with the semiconductor device. At this time, the contact pin applies a load corresponding to the spring characteristic of the spring provided in the plunger pin to the semiconductor element. The gate and emitter (source and cathode) pads of the semiconductor device were electrically connected to the test circuit via contact pins, plunger pins and wiring, and the collector (drain and anode) pads were electrically connected to the test circuit via electrodes and wiring on the test table, and electrical characteristics were tested.
In addition, when the radius of the contact surface between the cylindrical contact pin and the semiconductor element is R, the sectional area of each contact pin is (π R ^ 2), and therefore, the contact area between the contact probe and the semiconductor element is determined as a whole by the number of (π R ^ 2) ×.
In recent years, the chip size of a semiconductor device tends to be smaller due to the accelerated progress of cell integration and performance improvement (improvement in rated current). On the other hand, even when the chip size is reduced, the semiconductor device is required to be tested for a low resistance contact and a large current to flow. Therefore, as a semiconductor device testing apparatus, it is necessary to improve the electrical conduction performance of the contact probe. There are 2 methods to improve the energization performance, one is to select a material that reduces the contact resistance of the contact pin and the semiconductor element, and the other is to enlarge the contact area of the contact pin and the semiconductor element.
Conventionally, low-resistance materials such as tungsten alloys, copper alloys, silver alloys, palladium alloys, gold alloys, and iridium alloys have been used for contact pins. Further, the contact area with the semiconductor element is increased by reducing the inter-pin pitch of the contact pins and arranging a plurality of contact pins.
As another method for increasing the contact area with the semiconductor element, it has been proposed to use, as a contact probe, a conductive resin which is in contact with and contacts the emitter (source) pad surface of the semiconductor element (see, for example, patent document 2). By forming the conductive resin into the size of the emitter (source) pad of the semiconductor element, the contact area can be greatly increased.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2012-068076
Patent document 2: japanese patent laid-open No. 2009-128189
Disclosure of Invention
Technical problem to be solved by the invention
However, in the structure in which the emitter (source) pad of the semiconductor element and the conductive resin are brought into face-to-face contact with each other, even if the contact area can be increased, it is difficult to apply a uniform load to the emitter (source) pad of the semiconductor element having a surface with unevenness of the conductive resin. Therefore, there is a problem that the contact resistance is not uniform over the entire surface of the emitter (source) pad of the semiconductor element, and the current is concentrated in a region with low contact resistance to cause local heat generation, thereby damaging the semiconductor element.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a contact probe, a semiconductor device testing apparatus, and a semiconductor device testing method for achieving low-resistance contact with a pad of a semiconductor device.
Technical scheme for solving technical problem
In order to solve the above problems, the present invention provides a contact probe. The contact probe is provided with a 1 st contact surface, and the 1 st contact surface is contacted with the plunger pins; and a 2 nd contact surface which is in surface-to-surface contact with the inspection object on the opposite side of the 1 st contact surface.
The invention provides a semiconductor element testing device, comprising: a test stand on which a semiconductor element is placed; a plurality of contact probes which are brought into contact with main electrodes of the semiconductor device mounted on the test stage when the semiconductor device is tested; a plurality of plunger pins which are brought into contact with the contact probes and press the contact probes against the main electrodes of the semiconductor device when the semiconductor device test is performed; a placement tray for lifting the contact probe to hold the contact probe at a position separated from the main electrode of the semiconductor device when the semiconductor device test is not performed, and for placing the contact probe at a predetermined position of the main electrode of the semiconductor device by its own weight when the semiconductor device test is performed; and a base unit that holds the plunger pin at a position separated from the contact probe when the semiconductor device test is not performed, and that presses the contact probe placed on the main electrode of the semiconductor device by contacting the plunger pin when the semiconductor device test is performed. The contact probe in the semiconductor device testing apparatus includes: a prismatic body having a 1 st contact surface that contacts the plurality of plunger pins, and a 2 nd contact surface that contacts the main electrode of the semiconductor element on a side opposite to the 1 st contact surface; and a protrusion protrudingly provided at the center of the 1 st contact surface and contacting one of the plunger pins.
The invention also provides a semiconductor element testing method for evaluating the electrical characteristics of the semiconductor element. The semiconductor element testing method includes the steps of placing a plurality of contact probes, each having a protrusion in the center of a contact surface of a prism-shaped body on a side of contact with a plunger pin, on a main electrode of the semiconductor element by its own weight; bringing one of the plunger pins into contact with the projecting portion of the contact probe, respectively, to maintain parallelism of the main electrodes of the contact probe and the semiconductor element; and increasing a load when the plunger pin abuts against the protrusion portion and causing the other plural plunger pins to abut against a 1 st contact surface around the protrusion portion, in each of the contact probes.
Effects of the invention
The contact probe, the semiconductor device testing apparatus, and the semiconductor device testing method having the above-described configurations have an advantage in that different loads are applied to the contact probe at the center and the periphery of the upper portion of the contact probe, and thus parallelism with respect to the inclined pad in the semiconductor device can be maintained, and low-resistance contact can be achieved.
Drawings
Fig. 1 is a diagram showing a configuration example of a semiconductor device testing apparatus according to embodiment 1.
Fig. 2 is an external perspective view showing a contact probe.
Fig. 3 is a plan view showing the arrangement relationship of the semiconductor, the contact probe, and the plunger pin.
Fig. 4 is an explanatory view of the contact area of the contact probe, fig. 4(a) shows the contact area in the case of the columnar contact probe, and fig. 4(B) shows the contact area in the case of the needle-like contact probe.
Fig. 5 is a diagram schematically illustrating a step of bringing the plunger pin into contact with the contact probe after bringing the contact probe into contact with the semiconductor element.
Fig. 6 is an explanatory view of the operation of the semiconductor device testing apparatus, fig. 6(a) shows a standby state before initial contact, fig. 6(B) shows a contact state with the semiconductor device, fig. 6(C) shows a contact state with the protrusion, and fig. 6(D) shows a complete contact state.
Fig. 7 is a diagram showing a relationship between a pressing amount of the plunger pin and a load.
Fig. 8 is a diagram illustrating the balance of the load applied to the contact probe.
FIG. 9 is a view showing another embodiment of a contact probe.
Fig. 10 is a diagram showing a configuration example of the semiconductor device testing apparatus according to embodiment 2.
Fig. 11 is a plan view showing the arrangement relationship of the semiconductor, the contact probe, and the plunger pin.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, the overall configuration of the semiconductor device testing apparatus according to the embodiment used for the dynamic characteristic test of the semiconductor device (chip) will be described.
Fig. 1 is a diagram showing a configuration example of a semiconductor element testing apparatus according to embodiment 1, and fig. 2 is a perspective view showing an external appearance of a contact probe.
The semiconductor element testing device includes: a test stage 11, the test stage 11 carrying the semiconductor element 1 in a chip state; contact probes 12, 13, the contact probes 12, 13 being in electrical contact with the semiconductor element 1; a contact block 14, the contact block 14 holding the contact probes 12, 13; and a test circuit 15. Here, an IGBT is shown as an example of the semiconductor element 1 of the test object. In the case of the IGBT, the semiconductor element 1 is placed on the test stage 11 in a state where one surface having the gate pad 1a as a control electrode and the emitter pad 1b as a main electrode faces upward and the other surface having the collector pad faces downward.
The contact block 14 is provided with a placing tray 16 and a base unit 17. The placement board 16 has probe holding holes 16a and 16b formed therethrough in accordance with the positions of the contact probes 12 and 13 disposed on the semiconductor element 1, and the contact probes 12 and 13 are inserted into the probe holding holes 16a and 16b, respectively. The base unit holds the plunger pin 18 that is in contact with and pressed by the contact probes 12, 13. The plunger pin 18 has a spring for applying a predetermined load to the contact probes 12 and 13.
The placement tray 16 is detachably provided on the base unit 17, and when the contact probes 12 and 13 need to be replaced, the placement tray 16 is detached from the base unit 17, and the damaged contact probes 12 and 13 are replaced with good contact probes 12 and 13. Further, when the semiconductor element 1 is not tested, the placing tray 16 lifts the contact probes 12, 13 from the semiconductor element 1, and maintains a state of being separated from the plunger pin 18. In testing the semiconductor device 1, the placement tray 16 is first lowered to lower the contact probes 12 and 13 and place the semiconductor device 1 with its own weight. Thereafter, the placing tray 16 is further lowered, and the contact probes 12 and 13 are lowered to come into contact with the plunger pin 18. As the placing tray 16 further descends, the plunger pin 18 applies a load to the contact probes 12, 13, pressing the contact probes 12, 13 to the semiconductor element 1.
The plunger pin 18 is connected to the test circuit 15 via wiring 19a, 19 b. The test stage 11 has a wiring 19c having one end connected to the lower surface of the semiconductor element 1, and the other end of the wiring 19c is connected to the test circuit 15.
Here, as shown in fig. 2, the contact probe 12 in contact with the emitter pad 1b of the semiconductor element 1 has a prism-shaped body 12 a. The upper end surface of the body 12a forms a 1 st contact surface 12b that contacts the plunger pin 18, and the lower end surface forms a 2 nd contact surface 12c that contacts the emitter pad 1b of the semiconductor element 1. The contact probe 12 further has a projecting portion 12d provided to project near the center of the 1 st contact surface 12b, and the plunger pin 18 is in contact with the upper surface of the projecting portion 12 d. The contact probe 12 further has a flange portion 12e at a peripheral portion on the 1 st contact surface 12b side. When the contact probes 12 are loosely fitted into the probe holding holes 16a formed through the placement tray 16, the flange portion 12e is locked to the probe holding holes 16a, and the contact probes 12 are prevented from falling off the placement tray 16. The contact probe 12 is also chamfered at the 2 nd contact surface 12c side peripheral edge, and the corner is cut at an angle of 45 degrees.
Fig. 3 is a plan view showing the arrangement relationship of the semiconductor, the contact probe, and the plunger pin, fig. 4 is an explanatory view of the contact area of the contact probe, fig. 4(a) shows the contact area in the case of a columnar contact probe, and fig. 4(B) shows the contact area in the case of a needle-like contact probe.
When semiconductor element 1 is tested, contact probes 12 of the number corresponding to the chip size are brought into contact with emitter pad 1 b. In the example shown in fig. 3, 5 contact probes 12 are in contact with the emitter pad 1 b. Each contact probe 12 is in contact with 5 plunger pins 18. Of these, 1 plunger pin 18 contacts the projection 12d of the contact probe 12, and 4 plunger pins 18 contact the 1 st contact surface 12d of the contact probe 12 so as to surround the projection 12 d.
As shown in FIG. 4A, the contact area between the contact probe 12 and the emitter pad 1B of the semiconductor element 1 is equal to the area of the 2 nd contact surface 12c of the contact probe 12, that is, the contact area of the 2 nd contact surface 12c is 64R 2 when 4 times (8R) the diameter (2R) of the contact probe 13 shown in FIG. 4B is set to the dimensions of the 2 nd contact surface 12c in the lateral direction (a) and the longitudinal direction (B), and the contact area of 5 pins is 5 π R2 (π R2 × 5 pins) when 5 pin-shaped contact probes 13 are used.
Here, the contact area differs by about 4(═ 64^2/5 π R ^ 2) times in the case of using 5 pin-shaped contact probes 13 compared with the case of using 1 block-shaped contact probe 12. That is, by changing 5 pin-shaped contact probes 13 to 1 block-shaped contact probe 12, the probe contact area with emitter pad 1b of semiconductor element 1 is increased by 4 times, and a contact with a lower resistance can be realized. Thus, the dead angle region of the inter-pin pitch formed by the point contact of the conventional pin-shaped contact probe 13 is effectively utilized to make surface contact with the emitter pad 1b of the semiconductor element 1, and the contact area may be several hundred times as large.
Next, a procedure of performing a dynamic characteristic test of the semiconductor device (chip) by using the above semiconductor device testing apparatus will be described.
Fig. 5 is a diagram schematically illustrating a step of bringing the plunger pin into contact with the contact probe after bringing the contact probe into contact with the semiconductor element. Fig. 6 is an explanatory view of the operation of the semiconductor device testing apparatus, fig. 6(a) shows a standby state before initial contact, fig. 6(B) shows a contact state with the semiconductor device, fig. 6(C) shows a contact state with the protruding portion, and fig. 6(D) shows a complete contact state. In fig. 5, the contact probe 12 is a probe in which the peripheral portion of the 2 nd contact surface 12c is chamfered at 45 degrees, and in fig. 6, the contact probe 12 is a probe in which the peripheral portion of the 2 nd contact surface 12c is chamfered at a curved shape (rounded shape).
As shown in the upper part of fig. 5, the placing tray 16 is provided with a portion holding the contact probe 12 in a recessed manner, and the block-shaped contact probe 12 held on the recessed portion is separated from the plunger pin 18 in a non-contact state. The placement tray 16 is also provided with a portion where the contact probe 13 is held in a protruding manner, and the pin-shaped contact probe 13 held in the protruding portion is almost in a contact state with the plunger pin 18. In this manner, the placement tray 16 is fixed to the base unit 17 and operates together with the base unit 17 in a state where the block-shaped contact probe 12 and the plunger pin 18 are not in contact with each other and the pin-shaped contact probe 13 and the plunger pin 18 are almost in contact with each other.
After the contact block 14 of the semiconductor device testing apparatus is lowered, the 2 nd contact surface 12c of the block-shaped contact probe 12 is placed on the emitter pad 1b of the semiconductor device 1, and the pin-shaped contact probe 13 is placed on the gate pad 1a of the semiconductor device 1.
As shown in the lower part of fig. 5, the placing tray 16 is further lowered to be in a state where: block-shaped contact probes 12 are left on the emitter pads 1b of the semiconductor element 1, and pin-shaped contact probes 13 are left on the gate pads 1a of the semiconductor element 1. At this time, a load corresponding to the lowering of the contact block 14 is applied to the pin-shaped contact probe 13 through the corresponding plunger pin 18.
When the placement tray 16 is further lowered, the protruding portion 12d of the contact probe 12 abuts on the tip of the corresponding plunger pin 18. Next, when the placement tray 16 is further lowered, the 1 st contact surface 12b of the contact probe 12 comes into contact with the tip ends of the 4 corresponding plunger pins 18. After the set tray 16 is further lowered and stopped, the plunger pin 18 in contact with the projection 12d and the 1 st contact surface 12b of the contact probe 12 applies a predetermined load to the projection 12d and the 1 st contact surface 12b of the contact probe 12.
Thus, the placement tray 16 is configured to: the block-shaped contact probe 12 is placed on the semiconductor element in a free state, and then the plunger pin 18 presses the protruding portion 12d of the contact probe 12 and the 1 st contact surface 12b in this order.
Next, the operation of the semiconductor device testing apparatus will be described in detail. The pin-shaped contact probe 13 has the same structure as the conventional one, and therefore, illustration and description thereof are omitted here.
First, as shown in fig. 6(a), in an initial state of the test start, the main body 12a of the contact probe 12 is loosely fitted into the probe holding hole 16a of the placement tray 16, and the flange portion 12e is locked around the probe holding hole 16 a. At this time, the contact probe 12 is not in contact with any plunger pin 18, and is thus lifted by the setting plate 16 in a free state.
Next, after the placing table 16 is lowered, the contact probe 12 is first placed on the emitter pad 1b which is the main electrode of the semiconductor element 1. As shown in fig. 6(B), when the placing tray 16 is further lowered, the placing tray 16 is separated from the contact probe 12, and the contact probe 12 is kept standing alone by its own weight. That is, the contact probe 12 is placed such that the 2 nd contact surface 12c of the contact probe 12 is parallel to the surface of the emitter pad 1b of the semiconductor element 1.
As shown in fig. 6(C), after the placement tray 16 is further lowered, one plunger pin 18 abuts on the projection 12d of the contact probe 12, and presses the contact probe 12 against the emitter pad 1b of the semiconductor element 1. Thus, the contact probe 12 is pressed against the emitter pad 1b of the semiconductor element 1 without being inclined in a state where the 2 nd contact surface 12c thereof is parallel to the surface of the emitter pad 1b of the semiconductor element 1. By uniformly contacting the entire 2 nd contact surface 12c of the contact probe 12 with the emitter pad 1b of the semiconductor element 1 in this manner, a large contact area can be obtained, and the contact resistance becomes uniform, so that it is possible to avoid the semiconductor element from being damaged due to local current concentration and heat generation. Further, since one-side pressing in which the contact probe 12 is pressed in a state inclined with respect to the emitter pad 1b of the semiconductor element 1 does not occur, it is possible to reduce quality deterioration such as formation of a deep probe trace on the surface of the emitter pad 1 b.
As shown in fig. 6(D), after the placement tray 16 is further lowered, the remaining plunger pin 18 abuts on the 1 st contact surface 12b of the contact probe 12. In the contact probe 12, the 1 st contact surface 12b around the projecting portion 12d is pressed against the emitter pad 1b of the semiconductor element 1 by the remaining plunger pin 18 in a state where the projecting portion 12d at the upper center is pressed against the emitter pad 1b of the semiconductor element 1 in the vertical direction. At this time, the plunger pin 18 that biases the projecting portion 12d is shorter in the amount (height portion) of the spring that projects from the 1 st contact surface 12b of the projecting portion 12d than the plunger pin 18 that biases the periphery of the projecting portion 12 d. Therefore, in the contact probe 12, a stronger load is applied to the projecting portion 12d than to the 1 st contact surface 12b around the projecting portion 12 d. Thereby, the plunger pin 18 and the contact probe 12 are brought into a complete contact state, and the semiconductor device testing apparatus is brought into a state in which the test circuit 15 can perform a test. In this way, since the 2 nd contact surface 12c of the contact probe 12 is parallel to the emitter pad 1b of the semiconductor element 1, the contact area increases, the contact resistance becomes low, and the test of a large current is applied.
After the dynamic characteristic test of the semiconductor device 1 is completed, the operation of the semiconductor device testing apparatus is reversed from the above-described process. That is, from the testable state shown in fig. 6(D), the state shown in fig. 6(C) is changed, that is: when the set tray 16 is raised, the plunger pin 18 first abutting on the 1 st contact surface 12b around the projection 12d is separated from the 1 st contact surface 12 b. After the set tray 16 is raised, the plunger pin 18 abutting the projection 12d is separated from the projection 12d, and the state shown in fig. 6(B) is achieved. Then, when the placing tray 16 is further raised, the placing tray 16 raises the contact probe 12, and returns to the standby state shown in fig. 6 (a).
Next, the spring characteristics of the spring provided in the plunger pin 18 and the load applied to the contact probe 12 when the plunger pin 18 is biased will be described.
Fig. 7 is a diagram showing a relationship between a pressing amount of the plunger pin and a load, and fig. 8 is a diagram explaining a balance of the load applied by the contact probe. In fig. 7, the horizontal axis represents the amount of depression of the plunger pin 18, and the vertical axis represents the load applied to the contact probe 12.
As shown in fig. 7, the amount of depression of the contact probe 12 by the plunger pin 18 is proportional to the load applied to the contact probe 12, and the value of the load is determined by the constant of the spring provided in the plunger pin 18.
Here, the plunger pin 18 that is pressed against the center of the projecting portion 12d of the probe 12 is loaded more heavily than the plunger pin 18 around the 1 st contact surface 12b around the pressing projecting portion 12d, because the pressing amount is larger than the projecting amount of the projecting portion 12 d. Therefore, in the test of the semiconductor device testing apparatus, the center plunger pin 18 presses the contact probe 12 with a high load, and the surrounding plunger pins 18 press the contact probe 12 with a low load. This difference in load is achieved by providing all the plunger pins 18 with the same spring characteristics and providing a protrusion 12d near the center of the contact probe 12 to vary the amount of pressing.
As described above, the center of the upper portion of the contact probe 12 is first pressed, and the periphery is pressed while increasing the load at the center, whereby the contact probe 12 is placed on the surface of the inclined emitter pad 1b of the semiconductor element 1 with a large contact area. That is, as shown in fig. 8, when the surface of the emitter pad 1b of the semiconductor element 1 is inclined, the contact probe 12 is placed on the surface of the emitter pad 1b of the semiconductor element 1 by its own weight, and therefore inevitably stands up in the vertical direction with respect to the surface of the emitter pad 1 b.
Next, since the contact probe 12 is pressed by the central 1 plunger pins 18 in a state of being placed on the surface of the emitter pad 1b, the 2 nd contact surface 12c uniformly presses the surface of the emitter pad 1b while keeping parallel to the surface of the emitter pad 1 b. Thereafter, the load on the center plunger pin 18 is controlled to be high, and the load on the surrounding plunger pins 18 is controlled to be slightly lower than the load on the center plunger pin 18, thereby maintaining the contact probe 12 in a posture of being in contact with the surface of the emitter pad 1 b. By changing the load characteristic of plunger pin 18, imbalance in the pressing force of contact probe 12 against the surface of emitter pad 1b of semiconductor element 1 is prevented, and a deep probe mark is not formed on the surface of emitter pad 1 b. Further, by forming the peripheral portion of the 2 nd contact surface 12c of the contact probe 12 in an R-shape, the formation of probe traces can be suppressed.
As described above, since the contact probe 12 does not press down the surface of the emitter pad 1b on one side, the contact area increases, and the contact resistance becomes low, and the following description will be given of the contact probe 12 in which the contact area with the electrode further increases, and the contact resistance becomes low.
FIG. 9 is a view showing another embodiment of a contact probe.
The contact probe 12 has a comb-like shape in which a plurality of grooves 12f are formed in the 2 nd contact surface 12 c. The grooves 12f may be, for example, lattice-shaped V grooves. Thus, when emitter pad 1b of semiconductor element 1 is made of a soft metal such as aluminum, for example, when contact probe 12 is pressed, the pressed metal can enter the space of groove 12 f. As a result, the contact area between the contact probe 12 and the emitter pad 1b increases, and the contact resistance becomes lower, and the contact probe 12 suitable for a larger current test can be realized.
The contact probes 12 can appropriately increase or decrease the contact area between the contact probes 12 and the emitter pad 1b by changing the pitch and depth of the grooves 12f according to the hardness of the metal forming the emitter pad 1b of the semiconductor element 1.
Fig. 10 is a diagram showing a configuration example of the semiconductor element testing apparatus according to embodiment 2, and fig. 11 is a plan view showing a positional relationship among a semiconductor, a contact probe, and a plunger pin. In fig. 10 and 11, the same or equivalent components as those shown in fig. 1 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the semiconductor device testing apparatus according to embodiment 2, the contact probe 20 is used in which the 1 st contact surface 12b that contacts the plunger pin 18 is formed flat. In this contact probe 20, the area of surface contact between the 2 nd contact surface 12b and the emitter pad 1b is the same as that of the contact probe 12 used in the semiconductor device testing apparatus according to embodiment 1. Therefore, the semiconductor device testing apparatus according to embodiment 2 can increase the contact area between the contact probe 20 and the emitter pad 1b, and reduce the current density. In addition, in embodiment 2, when the placement tray 16 is mounted on the base unit 17, the contact probe 20 held on the placement tray 16 may be brought into contact with the plunger pin held on the base unit 17.
When the semiconductor element 1 is tested, 5 contact probes 20 are in contact with the emitter pad 1b as illustrated in fig. 11. Further, each contact probe 20 is in contact with the 1 st contact surface 12b through 5 plunger pins 18. The number of the contact probes 20 placed on the emitter pad 1b of the semiconductor element 1 is determined according to the contact probes 20 and the chip size. The number of plunger pins 18 that contact the contact probe 20 is determined by the size of the 1 st contact surface 12b and the installation interval of the plunger pins 18 held by the base unit 17.
Description of the reference symbols
1 semiconductor element
1a gate pad
1b emitter pad
11 test bench
12 contact probe
12a main body
12c 2 nd contact surface
12d projection
12e flange part
12f groove
13 contact probe
14 contact block
15 test circuit
16 placing plate
16a, 16b probe-holding hole
17 base unit
18 plunger pin
19a, 19b, 19c wiring
20 contact probe
Claims (6)
1. A semiconductor device testing apparatus, comprising:
a test stand on which a semiconductor element is placed;
a plurality of contact probes which are brought into contact with main electrodes of the semiconductor device mounted on the test stage when the semiconductor device is tested;
a plurality of plunger pins which are brought into contact with the contact probes and press the contact probes against the main electrodes of the semiconductor device when the semiconductor device test is performed;
a placement tray for lifting the contact probe to hold the contact probe at a position separated from the main electrode of the semiconductor device when the semiconductor device test is not performed, and for placing the contact probe at a predetermined position of the main electrode of the semiconductor device by its own weight when the semiconductor device test is performed; and
a base unit for holding the plunger pin at a position separated from the contact probe when the semiconductor device test is not performed, and for pressing the contact probe placed on the main electrode of the semiconductor device by contacting the plunger pin when the semiconductor device test is performed,
the contact probe has: a prismatic body having a 1 st contact surface that contacts the plurality of plunger pins, and a 2 nd contact surface that contacts the main electrode of the semiconductor element on a side opposite to the 1 st contact surface; and a protrusion portion that is protrudingly provided at a center of the 1 st contact surface and is pressed with a high load by a center plug pin arranged at a center among the plug pins, an upper surface of the 1 st contact surface located around the protrusion portion being a low-load pressing surface that is pressed by a plurality of peripheral plug pins arranged around the center plug pin.
2. The semiconductor device testing apparatus according to claim 1,
the placing tray has a through hole into which the contact probe is loosely fitted;
the contact probe has a flange portion on a peripheral portion on the 1 st contact surface side, and the flange portion prevents the contact probe from falling off from the through hole.
3. The semiconductor device testing apparatus according to claim 1,
the contact probe forms a groove on the 2 nd contact surface.
4. The semiconductor device testing apparatus according to claim 1,
the placement tray is detachably attached to the base unit that can be raised and lowered with respect to the test bed.
5. A semiconductor element testing method for evaluating electrical characteristics of a semiconductor element, the semiconductor element testing method comprising the steps of:
placing a plurality of contact probes, each having a protruding portion at the center of a contact surface of the prism-shaped body on the side of contact with the plurality of plunger pins, on the main electrode of the semiconductor element by using the weight of the contact probe;
a central plunger pin arranged at the center of the plunger pins is abutted against the protruding part of the contact probe, so that the parallelism between the contact probe and the main electrode of the semiconductor element is maintained; and
in each of the contact probes, a load when the center plunger pin abuts against the protruding portion is increased, and a contact surface between a plurality of peripheral plunger pins arranged around the center plunger pin and the protruding portion is made to abut against a lower load than the center plunger pin.
6. The semiconductor device testing method according to claim 5, wherein the test result is obtained by testing the semiconductor device,
the plunger pin has a spring with the same load, and the difference between the load applied to the protruding portion and the load applied to the contact surface around the protruding portion is set according to the amount of protrusion of the protruding portion from the contact surface.
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| JP2016-117565 | 2016-06-14 | ||
| JP2016117565A JP6790477B2 (en) | 2016-06-14 | 2016-06-14 | Semiconductor device test equipment and semiconductor device test method |
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| CN107505485B true CN107505485B (en) | 2020-07-31 |
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| WO2018092457A1 (en) * | 2016-11-16 | 2018-05-24 | 富士電機株式会社 | Semiconductor testing circuit, semiconductor testing device, and semiconductor testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS60142526A (en) * | 1983-12-29 | 1985-07-27 | Toshiba Corp | Measurement of electrical characteristics of semiconductor element |
| JPH05302938A (en) * | 1992-04-24 | 1993-11-16 | Ibiden Co Ltd | Inspection jig for printed wiring board |
| DE19748823B4 (en) * | 1997-11-05 | 2005-09-08 | Feinmetall Gmbh | Service-friendly contacting device |
| JP2003133025A (en) * | 2001-10-25 | 2003-05-09 | Yazaki Corp | Inspection pin of wire harness inspection jig |
| US20050174136A1 (en) * | 2004-02-09 | 2005-08-11 | Jiachun Zhou | Test pin back surface in probe apparatus for low wear multiple contacting with conductive elastomer |
| JP2006005368A (en) * | 2005-07-01 | 2006-01-05 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| US8344747B2 (en) * | 2008-02-01 | 2013-01-01 | Nhk Spring Co., Ltd. | Probe unit |
| JP2012520461A (en) * | 2009-03-10 | 2012-09-06 | ジョンステック インターナショナル コーポレーション | Conductive pins for microcircuit testers |
| JP5370323B2 (en) * | 2010-09-22 | 2013-12-18 | 富士電機株式会社 | Probe unit |
| US9373900B2 (en) * | 2011-07-19 | 2016-06-21 | Nhk Spring Co., Ltd. | Contact structure unit |
| US9069035B2 (en) * | 2011-08-21 | 2015-06-30 | Dong Chen | Predicting LED parameters from electroluminescent semiconductor wafer testing |
| JP5702416B2 (en) * | 2012-07-11 | 2015-04-15 | 本田技研工業株式会社 | Current application device |
| JP2014081231A (en) * | 2012-10-15 | 2014-05-08 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| JP5819880B2 (en) * | 2013-05-08 | 2015-11-24 | 本田技研工業株式会社 | Parallelism adjusting device and parallelism adjusting method |
| JP5936579B2 (en) * | 2013-05-08 | 2016-06-22 | 本田技研工業株式会社 | Current application device |
| JP6029535B2 (en) * | 2013-05-27 | 2016-11-24 | 三菱電機株式会社 | Contact probe |
| JP5781128B2 (en) * | 2013-08-19 | 2015-09-16 | 本田技研工業株式会社 | Current supply apparatus and semiconductor element manufacturing method |
| JP6491409B2 (en) * | 2013-12-27 | 2019-03-27 | 富士電機株式会社 | Contact and semiconductor test equipment |
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| JP6790477B2 (en) | 2020-11-25 |
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