JP2014081231A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a reproducible and stable measurement of the electrical characteristics of a semiconductor device in a semiconductor device inspection process.SOLUTION: On a surface of a vertex PAe that is a tip end of a contact part PAb of a probe pin PA and contacts an external terminal which is provided on a semiconductor device, unevenness processing is performed periodically at a first interval and a striped pattern or dotted pattern is formed. The first interval which is one value within the range from 50 nm to 5 μm allows multi-point contact between the external terminal and the vertex PAe, thereby reducing a contact resistance.

Description

  The present invention relates to a semiconductor device manufacturing technique, and includes a step of inspecting electrical characteristics of a semiconductor integrated circuit using, for example, an IC (Integrated Circuit) test socket having a plurality of probe pins or a probe card having a plurality of probe pins. It can be suitably used for manufacturing a semiconductor device.

  Various proposals have been made regarding the shape of the probe pins and contact members used when inspecting the electrical characteristics of the semiconductor integrated circuit.

  For example, in JP2009-53124A (Patent Document 1), 0.1 to 2.0% by weight of ultradispersed nanodiamond particles having a particle size of 2 to 200 nm in a crystal grain boundary is formed on the surface of a substrate. A probe pin is disclosed in which a contact material composed of a precious metal thin film layer dispersed in a proportion is formed.

  JP 2012-68269 A (Patent Document 2) discloses a contact probe in which a carbon film containing a metal element is formed on the surface of a metal substrate, and the concentration of the metal element on the surface of the carbon film. Is lower than the average concentration of the entire coating, and the concentration of the metal element on the surface of the carbon coating is 20% or less.

  Japanese Laid-Open Patent Publication No. 63-182501 (Patent Document 3) discloses a diamond probe in which diamond particles are laminated on the tip of a metal rod and a conductive material is coated thereon by vapor deposition or sputtering. ing.

  Japanese Patent Laid-Open No. 2010-54264 (Patent Document 4) includes a probe main body provided with a beam portion and a base that is a contact portion that contacts the wafer and is connected to the wafer-side end of the probe main body. A probe having a contact portion is disclosed.

JP 2009-53124 A JP 2012-68269 A JP-A 63-182501 JP 2010-54264 A

  When inspecting the electrical characteristics of a semiconductor device in a semiconductor device selection process, a probe pin with a high hardness plating that is difficult to oxidize and is highly conductive is generally used as a means for improving contact performance. It has been. However, when the contact with the external terminal provided in the semiconductor device is repeated, the contact resistance varies due to the deformation of the tip of the contact portion or the attachment of the metal scrap constituting the external terminal to the tip of the contact portion. Further, as the thickness of the semiconductor device is reduced, the problem of destruction of the semiconductor device due to the contact load has become serious.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the surface of a portion of the contact portion of the probe pin that is in contact with the external terminal of the semiconductor device is periodically subjected to uneven processing at a first interval to form a striped pattern. Alternatively, a dot-like pattern is formed. The first interval is one value in the range of 50 nm to 5 μm.

  According to one embodiment, the electrical characteristics of a semiconductor device can be measured with good reproducibility in the semiconductor device inspection process.

1 is a main part sectional view of a semiconductor device according to a first embodiment; 1 is a schematic perspective view of an IC test socket according to Embodiment 1. FIG. FIG. 4 is an essential part cross-sectional view showing an enlarged part of an IC test socket in which the semiconductor device according to the first embodiment is inserted; FIG. 3 is a cross-sectional view of a main part showing an example of a structure of a probe pin provided in the IC test socket according to the first embodiment, and a perspective view showing an enlarged tip of a contact part of the probe pin. FIG. 3 is an essential part cross-sectional view showing an enlarged tip of a contact portion of a probe pin provided in the IC test socket according to the first embodiment. 3 is an enlarged photograph showing a tip surface of a contact portion of a probe pin according to the first embodiment. (A), (b) and (c) are enlarged views of the tip of the contact portion of the probe pin provided in the IC test socket according to the first modification, the second modification and the third modification of the first embodiment, respectively. FIG. FIG. 3 is an essential part cross-sectional view showing an enlarged tip of a probe pin provided in the probe card according to the first embodiment. (A) And (b) is principal part sectional drawing which expands and shows the front-end | tip of the probe pin with which the probe card by the 1st modification of Embodiment 1 and the 2nd modification is each provided. FIG. 10 is an essential part cross-sectional view showing an enlarged tip of a contact portion of a probe pin provided in an IC test socket according to a second embodiment. (A), (b), and (c) are enlarged views of the tip of the contact portion of the probe pin provided in the IC test socket according to the first, second, and third modifications of the second embodiment, respectively. FIG. (A) And (b) is principal part sectional drawing which expands and shows the front-end | tip of the contact part of the probe pin with which the socket for IC test by the 4th modification of Embodiment 2 and a 5th modification is provided, respectively. FIG. 9 is an essential part cross-sectional view showing an enlarged tip of a probe pin provided in a probe card according to a second embodiment. (A) And (b) is principal part sectional drawing which expands and shows the front-end | tip of the probe pin with which the probe card by the 1st modification of Embodiment 2 and a 2nd modification is each provided. It is principal part sectional drawing explaining the mode of contact with the vertex part of the front-end | tip of the contact part of the probe pin which the present inventors examined, and the external terminal (solder ball). (A), (b), (c), (d), (e), and (f) each show an example of the tip of the probe pin before the embodiment studied by the present inventors is applied. It is principal part sectional drawing.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  First, since the structure of the probe pin according to the present embodiment is considered to be clearer, the structure of the probe pin before the application of the present embodiment and its problems, which have been studied by the present inventors, are described with reference to FIG. And it demonstrates below using FIG. FIG. 15 is a cross-sectional view of the main part for explaining the state of contact between the apex at the tip of the contact portion of the probe pin and the external terminal (solder ball). 16 (a), (b), (c), (d), (e), and (f) are cross-sectional views of relevant parts showing an example of the tip of the probe pin before the embodiment is applied. is there.

  In the sorting step after assembling the semiconductor device, for example, an electrical test of the semiconductor device is performed using an IC test socket having a plurality of probe pins. For example, in the case of a BGA (Ball Grid Array) type semiconductor device (semiconductor package), a semiconductor device is inserted into an IC test socket, and a plurality of probe pins are brought into contact with a plurality of solder balls as external terminals. A predetermined electrical signal is transmitted from the tester to the plurality of probe pins to perform electrical inspection.

As shown in FIG. 15, in order to improve the contact performance, the tip of the contact portion of the probe pin PE has a tip shape, and the apex of the tip portion has an acute angle. The area of the surface where the external terminal (solder ball) SB and the apex at the tip of the contact portion of the probe pin PE contact is, for example, about 100 to 1000 μm ² .

  Furthermore, in order to improve the contact performance, the tip of the contact portion of the probe pin PE is covered with a conductive film. For example, as shown in FIG. 16 (a), Au (gold), AuCo (gold cobalt), via a barrier film Eb1, on the surface of a base material Es1 made of BeCu (beryllium copper) or SK material (tool carbon steel material), There is a contact portion PEb1 on which a conductive film Ep1 made of AuNi (gold nickel), Rh (rhodium), Ru (ruthenium), Ir (iridium) or Pa (palladium) alloy is formed. The barrier film Eb1 is a Ni (nickel) film, for example, and is formed as a diffusion prevention layer such as Cu (copper) and an adhesive layer.

  For example, as shown in FIG. 16B, a conductive film Ep2 made of Rh (rhodium), Ru (ruthenium) or Ir (iridium) is formed on the surface of a base material Es2 made of BeCu (beryllium copper) or SK material. There is a contact portion PEb2 in which is formed.

  Further, for example, as shown in FIG. 16C, there is also a contact portion PEb3 constituted only by a base material Es3 made of a Pd (palladium) alloy. The conductive film is formed by, for example, a plating method.

  However, such a probe pin has various technical problems described below.

  In the probe pin having the above structure, the area (number of points) of the true contact point at the tip of the contact portion that pierces the solder ball is small, and if the contact between the probe pin and the solder ball is repeated, the tip of the contact portion deforms or the contact portion The area of the true contact point varies due to the adhesion or diffusion of the solder scrap to the tip.

  Further, a hard Sn (tin) oxide film having a thickness of about 10 nm is formed on the surface of the solder ball. In order to break this Sn (tin) oxide film at the tip of the contact portion, the tip of the probe pin has an acute angle and the contact load is increased for the purpose of securing the contact area (true contact point). As the surface pressure increases, the tip of the contact portion is easily deformed. In addition, as the semiconductor device becomes thinner, the problem of destruction of the semiconductor device due to contact load also arises. On the other hand, when the contact load is lowered, the Sn oxide film is hard to break, and the solder waste adhering to the tip of the contact part and the oxide film formed on the contact part cannot be removed by the scrubbing operation. Since the contact point) also decreases, the contact resistance increases.

  In addition, in order to remove solder scraps and organic contamination adhered to the tip of the contact portion, contact between the probe pin and the solder ball is repeated, and then the tip surface of the contact portion is polished using a polishing sheet. However, in the probe pins shown in FIGS. 16A and 16B, the tip shape of the contact portion is changed by this polishing, and the conductive film covering the tip is removed to expose the base material. End up.

  Therefore, when the number of contact between the probe pin and the solder ball increases, the contact resistance at the time of inspection varies greatly. Especially in a high-speed waveform transmission test or a test that requires a large current to flow, a semiconductor device that is stable with high reproducibility. The electrical characteristics could not be measured.

  Note that the various technical problems described above are not limited to probe pins (such as long pins or leaf spring pins) used for electrical inspection of a semiconductor device performed after the semiconductor device is assembled. For example, a probe pin (vertical pin, cantilever, micro cantilever or MEMS (Micro Electro Mechanical Systems) pin, etc.) provided in a probe card used when judging whether each of a plurality of semiconductor chips formed on the main surface of a semiconductor wafer is good or bad ) Is the same.

  An example of the tip of the probe pin provided in the probe card is shown in FIGS. 16 (d), (e) and (f). For example, as shown in FIG. 16 (d), Au (gold), AuCo (gold cobalt), AuNi (gold nickel), Rh (via a barrier film Eb4) on the surface of a base material Es4 made of BeCu (beryllium copper). There is a probe pin tip PEb4 on which a conductive film Ep4 made of a rhodium), Ru (ruthenium), Ir (iridium) or Pd (palladium) alloy is formed. The barrier film Eb4 is a Ni (nickel) film, for example.

  Further, for example, as shown in FIG. 16 (e), a conductive material made of Rh (rhodium), Ru (ruthenium), Ir (iridium) or Pd (palladium) alloy is formed on the surface of the base material Es5 made of BeCu (beryllium copper). There is a probe pin tip PEb5 on which a conductive film Ep5 is formed.

  Further, for example, as shown in FIG. 16 (f), a probe composed only of a base material Es6 made of W (tungsten), Ru (ruthenium), Ir (iridium), ReW (rhenium tungsten) or Pd (palladium) alloy. There is also a pin tip PEb6.

  The tips of the plurality of probe pins provided in the probe card are in contact with a plurality of bonding pads mainly made of Al (aluminum) formed on the main surface of the semiconductor wafer. Therefore, when contact between the probe pin and the bonding pad is repeated, deformation of the tip of the probe pin or adhesion or diffusion of Al (aluminum) debris to the tip of the probe pin occurs.

  In addition, the tip of the probe pin breaks the Al (aluminum) oxide film formed on the surface of the bonding pad, and scrubs the Al (aluminum) debris attached to the tip of the contact portion and the oxide film formed on the contact portion. The contact load of the probe pin is increased to secure the contact area (true contact point). For this reason, the tip of the probe pin is easily deformed.

  In addition, in order to remove Al (aluminum) debris attached to the tip of the probe pin and organic contamination, the tip surface of the probe pin is polished with a polishing sheet after repeated contact between the probe pin and the bonding pad. . However, in the probe pins shown in FIGS. 16D and 16E described above, this polishing increases the tip diameter or the tip length, shortens the contact life of the probe pin, and reduces the conductive life that covers the tip. As a result, the base film is exposed.

  For these reasons, probe pins used in the inspection process of semiconductor devices have excellent durability, and stable contact resistance can be obtained even with low contact loads resulting from the increased number of pins and weakness of semiconductor devices. Is required.

(Embodiment 1)
≪Probe pin in IC test socket≫
First, an electrical inspection of a semiconductor device performed in a sorting step after the assembly of the semiconductor device and a structure of a probe pin provided in an IC test socket used in the electrical inspection will be described with reference to FIGS.

  FIG. 1 is a fragmentary cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a schematic perspective view of the IC test socket according to the first embodiment. FIG. 3 is an essential part cross-sectional view showing an enlarged part of the IC test socket into which the semiconductor device according to the first embodiment is inserted. FIG. 4 is a cross-sectional view of a main part showing an example of the structure of a probe pin provided in the IC test socket according to the first embodiment, and a perspective view showing an enlarged tip of a contact part of the probe pin. FIG. 5 is an essential part cross-sectional view showing an enlarged tip of a contact portion of a probe pin provided in the IC test socket according to the first embodiment. FIG. 6 is an enlarged photograph showing the tip surface of the contact portion of the probe pin according to the first embodiment. 7A, 7B, and 7C show the tips of the contact portions of the probe pins provided in the IC test sockets according to the first, second, and third modifications of the first embodiment, respectively. It is principal part sectional drawing which expands and shows.

<Semiconductor device>
As an example of the semiconductor device, a BGA type semiconductor device (semiconductor package) having a face-up bonding structure employing the wire bonding connection shown in FIG. 1 will be described.

  As shown in FIG. 1, the semiconductor device SM is not limited to this, but the semiconductor chip SC is mounted on the upper surface of the wiring board IS, and the lower surface of the wiring board IS (the surface opposite to the upper surface of the wiring board IS). The package structure has a plurality of ball-shaped external terminals (solder balls) SB arranged as external connection terminals.

Semiconductor chip The semiconductor chip SC has a main surface and a back surface opposite to the main surface, and the central portion of the upper surface of the wiring board IS so that the back surface of the semiconductor chip SC faces the upper surface of the wiring board IS. The semiconductor chip SC is mounted on the chip mounting region via a film-like adhesive DF such as paste or DAF (Die Attach Film).

  On the main surface of the semiconductor chip SC, a plurality of bonding pads (electrode pads) EP electrically connected to the semiconductor elements are arranged. These bonding pads EP are composed of the uppermost wiring of the multilayer wiring layers of the semiconductor chip SC, and a part of the upper surface is exposed by the opening formed in the surface protective film corresponding to each bonding pad EP. doing.

-Wiring board Wiring board IS is a buildup board etc., for example, Comprising: The plane shape which intersects the thickness direction is a rectangle. The wiring board IS is not limited to this, but mainly includes a core material (base material) and a multilayer wiring having wiring on one side (upper surface) side, the other surface (lower surface) side, and inside of the core material. It has a structure.

  On the upper surface of the wiring board IS, a plurality of bonding leads (electrode pads) BL are arranged along each side of the wiring board IS in an area around the chip mounting area. These bonding leads BL are composed of the uppermost wiring formed on the wiring board IS, and the upper surface of each bonding lead BL is exposed through an opening formed in the upper surface protective film.

  A plurality of bump lands (electrode pads) BLR are arranged on the lower surface of the wiring board IS. These bump lands BLR are composed of the lowermost wirings formed on the wiring board IS, and the lower surfaces of the respective bump lands BLR are exposed through openings formed in the lower surface protective film.

・ Conductive members (bonding wires, wires)
A plurality of bonding pads EP arranged on the surface of the semiconductor chip SC and a plurality of bonding leads BL arranged on the upper surface of the wiring board IS are electrically connected by a plurality of conductive wires WC, respectively. For the conductive wire WC, for example, an Au (gold) wire or a Cu (copper) wire of about 15 to 50 μmφ is used.

-Sealing body The semiconductor chip SC and the plurality of conductive wires WC are sealed by a sealing body RS formed on the upper surface of the wiring board IS. For the purpose of reducing the stress, the sealing body RS is formed of, for example, an epoxy thermosetting insulating resin to which a phenolic curing agent, silicone rubber, a large number of fillers (for example, silica) and the like are added. The sealing body RS is formed by, for example, a transfer mold method.

External terminals A plurality of external SBs SB are formed on the plurality of bump lands BLR formed on the lower surface of the wiring board IS, and these external terminals SB are electrically connected to the plurality of bump lands BLR and mechanically. Connected. As the external terminal SB, a solder bump having a lead-free solder composition substantially free of lead, for example, tin-3 [wt%] silver-0.5 [wt%] copper (Sn-3 [wt%] Ag-0 .5 [wt%] Cu) solder bumps are used.

<Socket for IC test>
Next, the IC test socket according to the first embodiment will be described with reference to FIGS.

  As shown in FIGS. 2 and 3, the IC test socket TS has a plurality of probe pins (contact pins, contact probes, probes, probes) PA which are respectively brought into contact with the plurality of external terminals SB of the semiconductor device SM during inspection. A socket base (probe guide) G1 for fixing a plurality of probe pins PA is provided. Further, the IC test socket TS includes a floating base (package guide) G2 that can accommodate the semiconductor device SM, and a package pressing cover G3 that presses the semiconductor device SM mounted in the floating base G2. A plurality of external terminals SB provided in the semiconductor device SM are directed to the bottom surface of the floating pedestal G2, the semiconductor device SM is mounted in the floating pedestal G2, and the package pressing cover G3 is closed to provide the bottom surface of the floating pedestal G2. The tips of the contact portions of the plurality of probe pins PA protrude from the plurality of through holes, respectively. As a result, the plurality of external terminals SB provided in the semiconductor device SM and the tips of the contact portions of the plurality of probe pins PA come into contact with each other, and electrical connection between them can be established.

<Structure of probe pin>
Next, the entire structure of the probe pin according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 4, a probe pin PA, which is an elongated pin member, includes an elongated cylindrical body part PAa and a contact part PAb that is slidably housed inside the body part PAa and has a tip that is tapered. And a spring member PAc that is housed inside the main body part PAa and presses the contact part PAb in the direction of pushing out the main body part PAa, and a support part PAd that serves as a contact support part on the test substrate electrode.

  The spring member PAc is housed in a state of being sandwiched between the support portion PAd and the contact portion PAb inside the main body portion PAa. Therefore, at the time of inspection, a load is always applied to the contact portion PAb in the direction of pushing out from the main body portion PAa by the spring member PAc so that the tip of the contact portion PAb is surely in contact with the external terminal SB provided in the semiconductor device SM. It has a structure.

  Further, in the probe pin PA, the main body part PAa, the contact part PAb, the spring member PAc, and the support part PAd are formed of a conductive material in order to electrically connect with the external terminal SB provided in the semiconductor device SM.

  Further, in order to improve the contact performance with respect to the external terminal SB of the semiconductor device SM, the tip end of the contact part PAb is in a cracked state, and the apex part PAe of the tip cracked shape has an acute angle. In the first embodiment, as shown in the enlarged view of FIG. 4, the tip of the contact portion PAb that is broken into four parts is illustrated, but the present invention is not limited to this. There may be.

  Next, the structure of the contact portion of the probe pin according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 5, the contact part PAb of the probe pin PA is formed on the surface of the base material As made of BeCu (beryllium copper) or SK material with a Pa (palladium) alloy, Au (gold), via a barrier film Ab. It has a structure in which a conductive film Ap made of AuCo (gold cobalt), Rh (ruthenium), Ru (rhodium, Ir (iridium) or AuNi (gold nickel) is formed. In order to improve contact performance, a conductive film Ap that is difficult to oxidize and has high conductivity is formed. The conductive film Ap is formed by, for example, a plating method.

  Further, as described with reference to FIG. 4 above, in order to improve the contact performance, the tip of the contact portion PAb of the probe pin PA has a tip crack shape, and the apex portion PAe of the tip crack shape has an acute angle. It has become. This apex portion PAe is a portion that is inserted into the external terminal SB provided in the semiconductor device SM at the time of inspection, and is a portion that substantially contacts the external terminal SB. Note that the tip of the contact portion PAb of the probe pin PA refers to a portion including the apex portion PAe that contacts the external terminal SB provided in the semiconductor device SM at the time of inspection.

  Further, as shown in the enlarged view of FIG. 5 and FIG. 6, the surface of the apex portion PAe at the tip of the contact portion PAb (the surface of the conductive film Ap (the portion indicated by a relatively thick line in FIG. 5)) ) Is subjected to irregular processing (a state in which a height difference can be confirmed, a state where it is not flat) periodically (period indicated by a symbol T in FIG. 6) at a first interval. For example, a plurality of striped patterns having a periodicity of the first interval are formed by the uneven processing. For the first interval, for example, one value in the range of 50 nm to 5 μm is considered appropriate (not to be limited to this range depending on other conditions). Further, as a range suitable for mass production, one value within a range having a central value of 0.8 μm is considered most suitable. In addition, it is preferable that a plurality of patterns be formed at a constant cycle. However, since there is a lack of specific validity in terms of processing accuracy, the pattern is not limited to a fixed cycle, and the first interval has a fixed cycle. A range that takes into account variations is also included.

  Further, from the viewpoint of sustaining the effect of maintaining the shape and prolonging the lifetime, the conductive film Ap has a higher hardness than that of Au (gold), AuCo (gold cobalt), or AuNi (gold nickel) having a low hardness. ), Ru (rhodium, Ir (iridium) or Pa (palladium) alloy is preferred.

  The plurality of stripe-like patterns having the periodicity are formed by, for example, performing uneven processing on the apex portion PAe at the tip of the contact portion PAb using a femtosecond laser.

  By forming a plurality of striped patterns on the surface of the apex portion PAe at the tip of the contact portion PAb, multipoint contact between the apex portion PAe at the tip of the contact portion PAb and the external terminal SB provided in the semiconductor device SM is possible. Therefore, the oxide film (for example, Sn (tin) oxide film) on the surface of the external terminal SB is easily destroyed. In particular, since a plurality of stripe-shaped patterns having periodicity are formed, the contact point can be controlled and the oxide film can be made more than when the surface of the apex portion PAe at the tip of the contact portion PAb is randomly roughened. It can be easily destroyed.

  Furthermore, by forming a plurality of stripe-shaped patterns on the surface of the apex portion PAe at the tip of the contact portion PAb, it becomes difficult for the scraps (solder scraps) of the external terminals SB to adhere due to the surface modification effect. Further, the strength of the apex portion PAe at the tip of the contact portion PAb is improved as compared with the case where a plurality of stripe-shaped patterns are not formed.

  As described above, the following effects can be obtained by forming a plurality of striped patterns having the periodicity of the first interval on the surface of the apex portion PAe at the tip of the contact portion PAb.

  Contact between the apex PAe at the tip of the contact portion PAb and the external terminal SB provided in the semiconductor device SM changes from surface contact to point contact, and the oxide film on the surface of the external terminal SB can be destroyed with a low contact load. Further, since the true contact point is increased and the adhesion of solder scraps to the apex portion PAe at the tip end of the contact portion PAb can be reduced, the contact area between the apex portion PAe at the tip end of the contact portion PAb and the external terminal SB ( The true contact point) increases, and a stable contact resistance can be obtained even at a low load. As a result, in the test, a large current can be passed through the semiconductor device SM, and stable electrical characteristics can be measured.

  In addition, since the contact load of the probe pin PA can be reduced, deformation of the tip of the contact portion PAb can be suppressed, and damage to the semiconductor device SM can be prevented.

  Further, since the surface shape of the tip of the contact portion PAb is uniform, when removing fine solder scraps and organic contamination adhering to the surface with an abrasive sheet, it is more than when a plurality of striped patterns are not formed. Since the polishing is uniformly performed, it is difficult to remove the conductive film Ap.

  Although FIG. 6 shows a stripe pattern, the present invention is not limited to this. For example, on the surface of the apex portion PAe at the tip of the contact portion PAb, the x direction is orthogonal to the x direction. It may be a dot-shaped pattern that is periodically concavo-convex with a first interval in the y direction.

<Inspection process after assembly of semiconductor device>
Next, an inspection process after the assembly of the semiconductor device will be described.

  First, the semiconductor device SM shown in FIG. 1 and the IC test socket TS shown in FIG. 2 are prepared. The semiconductor device SM is mounted in the floating base G2 with the plurality of external terminals SB provided in the semiconductor device SM facing the bottom surface of the floating base G2. Subsequently, by closing the package pressing cover G3, the tips of the contact portions PAb of the plurality of probe pins PA are protruded from the plurality of through holes provided on the bottom surface of the floating base G2. As a result, the plurality of external terminals SB provided in the semiconductor device SM and the tips (vertex portions PAe) of the contact portions PAb of the plurality of probe pins PA come into contact with each other, and a predetermined electrical signal is transmitted from the external tester to the semiconductor device SM. And sent for electrical inspection. At this time, the apex portion PAe at the tip of the contact portion PAb is stuck into the external terminal SB. However, a large number of contact points are formed on the surface of the apex portion PAe, and the contact area is large. Contact resistance can be obtained, and it is possible to cope with a large current.

<Modification of probe pin>
Next, a probe pin PA according to a modification of the first embodiment will be described with reference to FIGS. 7 (a), (b) and (c).

  As shown in FIG. 7A, a probe pin which is a first modified example of the probe pin PA has Rh (ruthenium), Ru (rhodium) on the surface of a base material As1 made of BeCu (beryllium copper) or SK material. Alternatively, the contact portion PAb1 having a structure in which a conductive film Ap1 made of Ir (iridium) is formed. The probe pin described with reference to FIG. 5 described above is provided on the surface of the apex portion PAe1 at the tip of the contact portion PAb1 (the surface of the conductive film Ap1 (the portion indicated by a relatively thick line in FIG. 7A)). Similar to PA, uneven processing is periodically performed at the first interval.

  Conductive film of Rh (ruthenium), Ru (rhodium) or Ir (iridium) harder than Pd (palladium) alloy, Au (gold), AuCo (gold cobalt) or AuNi (gold nickel) on the surface of the probe pin By forming as Ap1, the uneven shape of the conductive film Ap1 can be maintained.

  As shown in FIG. 7B, the probe pin, which is a second modification of the probe pin PA, constitutes the contact portion PAb2 only with the base material As2 made of Pd (platinum) alloy. The probe pin PA described with reference to FIG. 5 described above is provided on the surface of the apex portion PAe2 at the tip of the contact portion PAb2 (the surface of the base material As2 (portion indicated by a relatively thick line in FIG. 7B)). In the same manner as described above, the unevenness processing is performed in an integrated manner at the first interval.

  Since the conductive film is not formed, the problem of peeling of the conductive film does not occur.

  As shown in FIG. 7C, the probe pin which is the third modification of the probe pin PA has a basic structure in which the conductive film Ap3 is formed on the surface of the base material As3 via the barrier film Ab3. Is the same as the structure of the probe pin PA shown in FIG. 5 described above, but the shapes of the tips of the contact portions are different. That is, in the probe pin PA described above, an acute apex portion PAe is formed at the tip of the contact portion PAb. On the other hand, in the probe pin as the third modification, a flat portion PAf having a surface perpendicular to the direction in which the probe pin is pushed out is formed at the tip of the contact portion PAb3. Furthermore, the surface of the flat portion PAf (the surface in contact with the surface of the conductive film Ap3 and the external terminal SB (portion indicated by a relatively thick line in FIG. 7C)) will be described with reference to FIG. As in the case of the probe pin PA, the unevenness processing is performed in an integrated manner at the first interval.

  By providing the flat portion PAf at the tip of the contact portion PAb3, even when the number of tips of the contact portion PAb3 that contacts the external terminal SB provided in the semiconductor device SM becomes ¼ due to misalignment, it is oxidized at multiple points. Since the contact load is received over a large area after the film is destroyed and the true contact point is secured, the contact load can be dispersed, and the deformation of the tip of the contact portion PAb3 caused by the contact load and the destruction of the semiconductor device are suppressed. be able to.

  Although not shown, the contact portions PAb1 and PAb2, which are modifications of the contact portion PAb described above, similarly form a flat portion at the tip, and periodically perform uneven processing at a first interval on the surface of the flat portion. You may give it. Further, considering an even load distribution to the contact surface, an R shape that is an arc shape is desirable.

≪Probe pins on the probe card≫
Next, for example, the structure of the probe pin provided in the probe card used when determining whether each of the plurality of semiconductor chips formed on the main surface of the semiconductor wafer is good or bad will be described with reference to FIGS. The main surface of the semiconductor wafer is partitioned into a plurality of chip regions, and a plurality of bonding pads electrically connected to the semiconductor integrated circuit are formed on each main surface of the plurality of chip regions.

  FIG. 8 is an enlarged cross-sectional view showing a main part of the probe pin provided in the probe card according to the first embodiment. 9 (a) and 9 (b) are enlarged cross-sectional views illustrating the main parts of the probe pins provided in the probe cards according to the first modification and the second modification of the first embodiment, respectively.

<Structure of probe pin>
The structure of the tip of the probe pin provided in the probe card according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 8, the tip PBb of the probe pin is attached to the surface of a base material Bs made of BeCu (beryllium copper) via a barrier film Bb, Pa (palladium) alloy, Au (gold), AuCo (gold cobalt). , Rh (rhodium), Ru (ruthenium), Ir (iridium), or AuNi (gold nickel), a conductive film Bp is formed. The barrier film Bb is formed as a diffusion prevention layer and a diffusion layer such as Cu (copper), and for example, a Ni (nickel) film is used. In order to improve the contact performance, a conductive film Bp that is difficult to oxidize and has high conductivity is formed. The tip PBb of the probe pin has a gentle arc shape.

  Further, on the surface of the apex of the probe pin tip PBb (the surface of the conductive film Bp (the portion indicated by a relatively thick line in FIG. 8)), as shown in FIG. Unevenness is periodically applied, and a plurality of stripe-like patterns having periodicity at the first interval are formed. The uneven processing applied to the surface of the apex of the tip PBb of the probe pin may be a plurality of dot-like patterns.

  As described above, the probe pin provided in the probe card also has the above-described configuration by forming a plurality of stripe-shaped (or dot-shaped) patterns having the periodicity of the first interval on the surface of the apex of the tip PBb of the probe pin. The same effect as that of the probe pin provided in the socket for IC test can be obtained. That is, the contact point between the apex of the tip PBb of the probe pin and the bonding pad formed on the main surface of the semiconductor wafer increases, and the oxide film on the surface of the bonding pad can be destroyed with a low contact load. Further, since the contact points are increased and adhesion of metal (for example, Al (aluminum)) debris constituting the bonding pad to the apex of the probe pin tip PBb can be reduced, the apex of the probe pin tip PBb is bonded to the apex. The contact area (true contact point) with the pad increases, and a stable contact resistance can be obtained even at a low load. As a result, a large current can be passed in the test, and stable electrical characteristics can be measured.

  Moreover, since the contact load of the probe pin can be reduced, deformation of the tip PBb of the probe pin and destruction of the semiconductor device can be suppressed.

  In addition, since the surface shape of the tip PBb of the probe pin becomes uniform, a plurality of stripes (or dots) are formed when removing fine Al (aluminum) debris and organic contamination adhering to the surface with an abrasive sheet. The conductive film Bp is less likely to be removed because the polishing is performed more uniformly than when the pattern is not formed.

<Modification of probe pin>
Next, probe pins provided in a probe card according to a modification of the first embodiment will be described with reference to FIGS.

  As shown in FIG. 9A, the tip PBb1 of the probe pin according to the first modification is formed on the surface of a base material Bs1 made of BeCu (beryllium copper), with Rh (ruthenium), Ru (rhodium), and Ir (iridium). Or a conductive film Bp1 made of a Pd (palladium) alloy. The probe pin PA described with reference to FIG. 5 described above is provided on the apex surface of the probe pin tip PBb1 (the surface of the conductive film Bp1 (the portion indicated by a relatively thick line in FIG. 9A)). Similarly, uneven processing is periodically performed at the first interval.

  By forming hard Rh (ruthenium), Ru (rhodium), Ir (iridium) or Pd (palladium) alloy as the conductive film Bp1 on the surface of the probe pin, the peeling of the conductive film Bp1 and the uneven shape are reduced. can do.

  As shown in FIG. 9B, the probe pin tip PB2b according to the second modification is made of W (tungsten), Ru (ruthenium), Ir (iridium), ReW (rhenium tungsten) or Pd (palladium) alloy. It consists only of the base material Bs2. The surface of the apex of the tip PBb2 of the probe pin (the surface of the base material Bs2 (the portion indicated by a relatively thick line in FIG. 9B)) is the same as the probe pin PA described with reference to FIG. In addition, irregularities are periodically formed at the first interval.

  Since the conductive film is not formed, the problem of peeling of the conductive film does not occur.

(Embodiment 2)
≪Probe pin in IC test socket≫
First, the structure of a probe pin provided in an IC test socket used for electrical inspection of a semiconductor device performed in a sorting step after the assembly of the semiconductor device will be described with reference to FIGS.

  FIG. 10 is an essential part cross-sectional view showing an enlarged tip of a contact portion of a probe pin provided in the IC test socket according to the second embodiment. 11 (a), 11 (b), and 11 (c) show the tips of the contact portions of the probe pins provided in the IC test sockets according to the first, second, and third modifications of the second embodiment, respectively. It is principal part sectional drawing which expands and shows. 12 (a) and 12 (b) are enlarged cross-sectional views of the main parts showing the tips of the contact portions of the probe pins provided in the IC test sockets according to the fourth and fifth modifications of the second embodiment, respectively. is there.

<Structure of probe pin>
The structure of the contact portion of the probe pin according to the second embodiment will be described with reference to FIG.

  As shown in FIG. 10, the contact portion PCb of the probe pin has a conductive film Cp made of Pa (palladium) alloy on the surface of a base material Cs made of BeCu (beryllium copper) or SK material via a barrier film Cb. It has a formed structure. For example, a Ni (nickel) film is used as the barrier film Cb.

  Further, in order to improve the contact performance, the tip of the contact portion PCb of the probe pin has a tip crack shape, and the apex portion PCe of the tip crack shape has an acute angle. As in the first embodiment described above, the surface of the apex portion PCe at the tip of the contact portion PCb (the surface of the conductive film Cp (the portion indicated by a relatively thick line in FIG. 10)) A plurality of stripe-like patterns having periodicity of intervals are formed. The uneven processing applied to the surface of the apex portion PCe at the tip of the contact portion PCb may be a plurality of dot-like patterns.

  Further, a hard DLC (Diamond Like Carbon) film DC is formed so as to cover the conductive film Cp formed at the tip of the contact portion PCb. The DLC film DC used in the second embodiment is an amorphous conductive film that does not contain hydrogen, and its surface is relatively smooth. Further, even when the DLC film DC is formed, the thickness of the DLC film DC is set so that the concavo-convex shape of the surface can be maintained at the apex portion PCe at the tip of the contact portion PCb. For example, when the period of the concavo-convex shape is 0.8 μm, the thickness of the DLC film DC is about 0.15 μm.

  By covering the surface of the tip of the contact portion PCb with the hard DLC film DC, the surface strength of the tip of the contact portion PCb is improved. Accordingly, in addition to the effect of forming a plurality of stripe-shaped (or dot-shaped) patterns having periodicity on the surface of the apex portion PCe at the tip of the contact portion PCb, a plurality of stripe-shaped (or The shape of the (dot-like) pattern is difficult to collapse. In addition, when the organic contamination adhered to the tip of the contact portion PCb is removed with a polishing sheet, the conductive film Cp is difficult to remove, and the substrate Cs can be prevented from being exposed.

  Further, by covering the surface of the tip of the contact portion PCb with the hard DLC film DC, the activity of the surface is lowered, and the external terminal SB (refer to FIG. 1 and FIG. 4 described above) of the semiconductor device SM is scraped ( Solder scrap) is difficult to adhere to the tip of the contact portion PCb.

<Modification of probe pin>
Next, a modification of the probe pin according to the second embodiment will be described with reference to FIGS. 11 (a), 11 (b) and 11 (c).

  As shown in FIG. 11 (a), the probe pin according to the first modified example has Rh (ruthenium), Ru (rhodium) or Ir (iridium) on the surface of a base material Cs1 made of BeCu (beryllium copper) or SK material. The contact portion PCb1 having the structure in which the conductive film Cp1 is formed. On the surface of the apex portion PCe1 at the tip of the contact portion PCb1 (the surface of the conductive film Cp1 (the portion indicated by a relatively thick line in FIG. 11A)) is the probe pin described with reference to FIG. Similarly, uneven processing is periodically performed at the first interval. Further, a DLC film DC is formed so as to cover the conductive film Cp1 formed at the tip of the contact portion PCb1.

  As shown in FIG. 11B, the probe pin according to the second modified example forms the contact portion PCb2 only with the base material Cs2 made of a Pd (platinum) alloy. The surface of the apex portion PCe2 at the tip of the contact portion PCb2 (the surface of the base material Cs2 (the portion indicated by a relatively thick line in FIG. 11B)) is the same as the probe pin described with reference to FIG. In addition, irregularities are periodically formed at the first interval. Furthermore, a DLC film DC is formed so as to cover the tip of the contact part PCb2.

  As shown in FIG. 11C, the probe pin according to the third modification has a conductive film Cp3 formed on the surface of the base material Cs3 via the barrier film Cb3, and the basic structure is the same as that shown in FIG. 10 is the same as the structure of the probe pin shown in FIG. 10, but the shapes of the tips of both contact portions are different. That is, in the probe pin shown in FIG. 10 described above, an acute apex portion PCe is formed at the tip of the contact portion PCb. On the other hand, in the probe pin as the third modified example, a flat portion PCf having a surface perpendicular to the direction in which the probe pin is pushed out is formed at the tip of the contact portion PCb3. Further, the surface of the flat portion PCf (the surface of the conductive film Cp3 (the portion indicated by a relatively thick line in FIG. 11C)) is similar to the probe pin described with reference to FIG. Concave and convex processing is periodically performed at intervals of 1. Further, a DLC film DC is formed so as to cover the conductive film Cp3 formed at the tip of the contact portion PCb3.

  By providing the flat portion PCf at the tip of the contact portion PCb3, even when the number of tips of the contact portion PCb3 contacting the external terminal SB provided in the semiconductor device SM becomes ¼ due to misalignment, it is oxidized at multiple points. Since the contact load is received over a large area after the film is destroyed and the true contact point is secured, the contact load can be dispersed, and the deformation of the tip of the contact portion PCb3 caused by the contact load and the destruction of the semiconductor device are suppressed. be able to.

  Although not shown, the contact portions PCb1 and PCb2, which are modifications of the contact portion PCb described above, similarly form a flat portion at the tip, and periodically perform uneven processing at a first interval on the surface of the flat portion. The DLC film DC may be formed so as to cover the tips of the contact portions PCb1 and PCb2. Further, considering an even load distribution to the contact surface, an R shape that is an arc shape is desirable.

  Next, a probe pin according to another modification of the second embodiment will be described with reference to FIGS. 12 (a) and 12 (b).

  As shown in FIG. 12A, in the probe pin contact portion PCb4 according to the fourth modification, a barrier made of, for example, a Ni (nickel) film is formed on the surface of the base material Cs4 made of BeCu (beryllium copper) or SK material. A film Cb4 is formed. The surface of the apex portion PCe4 at the tip of the contact portion PCb4 (the surface of the barrier film Cb4 (the portion indicated by a relatively thick line in FIG. 12A)) is the same as the probe pin described with reference to FIG. In addition, irregularities are periodically formed at the first interval. A conductive film Cp4 made of Au (gold), AuCo (gold cobalt) or AuNi (gold nickel) is formed on the surface of the barrier film Cb4 except for the tip of the contact part PCb4. The DLC film DC is directly formed on the surface of the barrier film Cb4.

  As shown in FIG. 12B, in the probe pin contact portion PCb5 according to the fifth modification, a barrier made of, for example, a Ni (nickel) film is formed on the surface of the base material Cs5 made of BeCu (beryllium copper) or SK material. A film Cb5 is formed. Except for the tip of the contact portion PCb5, a conductive film Cp5 made of Au (gold), AuCo (gold cobalt) or AuNi (gold nickel) is formed on the surface of the barrier film Cb5. A DLC film DC is formed directly on the surface of the film Cb5. Further, the probe described with reference to FIG. 10 described above is provided on the surface of the apex portion PC5e at the tip of the contact portion PCb5 (the surface of the DLC film DC (the portion indicated by a relatively thick line in FIG. 12B)). Similar to the pins, irregularities are periodically formed at the first interval.

  Au (gold), AuCo (gold cobalt), and AuNi (gold nickel) maintain the conduction path (contact portion PAb → main body portion PAa (spring member PAc) → support portion PAd) of the probe pin PA shown in FIG. This is an excellent material and has a proven track record. However, since the hardness is relatively low, if a high hardness DLC film DC is formed on these surfaces, the uneven shape may not be maintained depending on the unit area load. Therefore, when using Au (gold), AuCo (gold cobalt) or AuNi (gold nickel) for the conductive films Cp4 and Cp5, Au (gold), AuCo (gold cobalt) at the tips of the contact portions PCb4 and PCb5 or AuNi (gold nickel) is removed, and the surface of the Ni (nickel) film (barrier film Cb4) having a relatively high hardness is processed to form a DLC film DC. Alternatively, after the DLC film DC is formed on the Ni (nickel) film (barrier film Cb4), uneven processing is periodically performed at the first interval.

≪Probe pins on the probe card≫
Next, for example, the structure of the probe pins provided in the probe card used when determining whether each of the plurality of semiconductor chips formed on the main surface of the semiconductor wafer is good or bad will be described with reference to FIGS.

  FIG. 13 is an essential part cross-sectional view showing an enlarged tip of a probe pin provided in the probe card according to the second embodiment. 14 (a) and 14 (b) are enlarged cross-sectional views of the principal parts of the probe pins provided in the probe cards according to the first modification and the second modification of the second embodiment, respectively.

<Structure of probe pin>
The structure of the tip of the probe pin provided in the probe card according to the second embodiment will be described with reference to FIG.

  As shown in FIG. 13, the tip PDb of the probe pin has a structure in which a conductive film Dp made of Pa (palladium) alloy is formed on the surface of a base material Ds made of BeCu (beryllium copper) via a barrier film Db. have. The barrier film Db is formed as a diffusion prevention layer such as Cu (copper) and an adhesive layer. For example, a Ni (nickel) film is used. The tip PDb of the probe pin has a gentle arc shape.

  Further, on the surface of the apex of the probe pin tip PDb (the surface of the conductive film Dp (the portion indicated by a relatively thick line in FIG. 13)), as shown in FIG. Unevenness is periodically applied, and a plurality of stripe-like patterns having periodicity at the first interval are formed. The uneven processing applied to the surface of the apex of the tip PDb of the probe pin may be a plurality of dot-like patterns. Further, a DLC film DC is formed so as to cover the conductive film Dp formed on the tip PDb of the probe pin.

  The surface strength of the probe pin tip PDb is improved by covering the surface of the probe pin tip PDb with the hard DLC film DC. Accordingly, in addition to the effect of forming a plurality of stripe-shaped (or dot-shaped) patterns having periodicity on the surface of the apex of the tip PDb of the probe pin, a plurality of stripe-shaped (or dot-shaped) formed on the surface thereof. ) Pattern shape is less likely to collapse. Further, when the organic contamination adhered to the tip PDb of the probe pin is removed with the polishing sheet, the conductive film Dp becomes difficult to remove, and the substrate Ds can be prevented from being exposed.

  Further, by covering the surface of the tip PDb of the probe pin with the hard DLC film DC, the activity of the surface is lowered, and the metal constituting the bonding pad formed on the main surface of the semiconductor wafer (for example, Al (aluminum)) ) It becomes difficult for debris to adhere to the tip PDb of the probe pin.

<Modification of probe pin>
Next, probe pins provided in a probe card according to a modification of the second embodiment will be described with reference to FIGS. 14 (a) and 14 (b).

  As shown in FIG. 14A, the tip PDb1 of the probe pin according to the first modified example has Rh (ruthenium), Ru (rhodium), Ir (iridium) on the surface of a base material Ds1 made of BeCu (beryllium copper). Or a conductive film Dp1 made of a Pd (palladium) alloy. On the surface of the apex of the probe pin tip PDb1 (the surface of the conductive film Dp1 (the portion indicated by a relatively thick line in FIG. 14A)) is the same as the probe pin described with reference to FIG. The irregularities are periodically processed at the first interval. Further, a DLC film DC is formed so as to cover the conductive film Dp1 formed on the tip PDb1 of the probe pin.

  As shown in FIG. 14 (b), the probe pin tip PDb2, which is the second modification, is made of W (tungsten), Ru (ruthenium), Ir (iridium), ReW (rhenium tungsten) or Pd (palladium) alloy. It is comprised only by the base material Ds2 which becomes. Similar to the probe pin described with reference to FIG. 10 described above, the surface of the apex of the tip PDb2 of the probe pin (the surface of the base material Ds2 (the portion indicated by a relatively thick line in FIG. 14A)) Concave and convex processing is periodically performed at intervals of 1. Further, a DLC film DC is formed so as to cover the tip PDb2 of the probe pin.

  By covering the tips PDb1 and PDb2 of the probe pins with the hard DLC film DC, the strength of the surface of the tips PDb1 and PDb2 of the probe pins is improved, and a plurality of stripes (or dots) formed on the surface are formed. It becomes difficult for the shape of the pattern to collapse, and exposure of the base materials Ds1, Ds2 can be prevented. Furthermore, the activity of the surface becomes low, and metal scraps are difficult to adhere to the tips PDb1 and PDb2 of the probe pins.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the embodiments of the probe pins provided in the IC test socket and the probe pins provided in the probe card studied by the present inventors have been specifically described. However, each probe pin described in the embodiment is an IC test socket. Or it is not limited to the probe pin with which a probe card is equipped.

  The present invention includes at least the following embodiments.

[Appendix 1]
A semiconductor device manufacturing method including the following steps:
(A) a step of preparing a semiconductor wafer in which a main surface is partitioned into a plurality of chip regions and a semiconductor integrated circuit is formed in each of the plurality of chip regions;
(B) a step of inspecting electrical characteristics of the semiconductor integrated circuit by bringing a plurality of probe pins into contact with a plurality of bonding pads formed in each of the plurality of chip regions;
Here, the surface of the tip of the probe pin in contact with the bonding pad is periodically roughened at a first interval, and the first interval is a value within a range of 50 nm to 5 μm. .

[Appendix 2]
In the method for manufacturing a semiconductor device according to attachment 1,
A plurality of striped patterns are formed on the surface of the tip of the probe pin by the uneven processing.

[Appendix 3]
In the method for manufacturing a semiconductor device according to attachment 1,
On the surface of the tip of the probe pin, a plurality of dot-like patterns are formed by the uneven processing.

[Appendix 4]
In the method for manufacturing a semiconductor device according to attachment 1,
Using the femtosecond laser, the surface of the tip of the probe pin is subjected to the uneven processing.

[Appendix 5]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin has BeCu as a base material, and a conductive film made of Pd alloy, Au, AuCo, Rh, Ru, Ir, or AuNi is formed on the surface of the base material via a barrier film. The surface of the conductive film is subjected to the uneven processing.

[Appendix 6]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin has BeCu as a base material, and a conductive film made of Rh, Ru, Ir, or Pd alloy is formed on the surface of the base material, and the unevenness processing is performed on the surface of the conductive film. Has been.

[Appendix 7]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin is made of W, Ru, Ir, ReW or Pd alloy as a base material, and the surface of the base material is subjected to the uneven processing.

[Appendix 8]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin has BeCu as a base material, a conductive film made of a Pd alloy is formed on the surface of the base material via a barrier film, the surface of the conductive film is subjected to the uneven processing, and The surface of the conductive film is covered with a conductive DLC film.

[Appendix 9]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin has BeCu as a base material, a conductive film made of Rh, Ru, Ir, or Pd alloy is formed on the surface of the base material, and the unevenness processing is performed on the surface of the conductive film, Further, the surface of the conductive film is covered with a conductive DLC film.

[Appendix 10]
In the method for manufacturing a semiconductor device according to attachment 1,
The tip of the probe pin is made of W, Ru, Ir, ReW or Pd alloy as a base material, and the surface of the base material is subjected to the uneven processing, and the surface of the base material is covered with a conductive DLC film. ing.

[Appendix 11]
In the method for manufacturing a semiconductor device according to attachment 5 or 8, the barrier film is made of Ni.

[Appendix 12]
In the method for manufacturing a semiconductor device according to any one of appendices 5, 6, 8 or 9, the conductive film is formed by a plating method.

Ab, Ab3 Barrier film Ap, Ap1, Ap3 Conductive film As, As1, As2, As3 Substrate Bb Barrier film Bp, Bp1 Conductive film Bs, Bs1, Bs2 Base material BL Bonding lead (electrode pad)
BLR bump land (electrode pad)
Cb, Cb3, Cb4, Cb5 Barrier film Cp, Cp1, Cp3, Cp4, Cp5 Conductive film Cs, Cs1, Cs2, Cs3, Cs4, Cs5 Base material Db Barrier film Dp, Dp1 Conductive film Ds, Ds1, Ds2 Base material DC DLC (diamond-like carbon) film DF Adhesive Eb1, Eb4 Barrier film Ep1, Ep2, Ep4, Ep5 Conductive film Es1, Es2, Es3, Es4, Es5, Es6 Base material EP Bonding pad (electrode pad)
G1 socket base (probe guide)
G2 floating base (package guide)
G3 Package pressing cover IS Semiconductor substrate PA Probe pin (contact pin, contact probe, probe, probe)
PAa Body PAb, PAb1, PAb2, PAb3 Contact part PAc Spring member PAd Indicating part PAe, PAe1, PAe2 Apex part PAf Flat part PBb, PBb1, PBb2 Probe pin tip PCb, PCb1, PCb2, PCb3, PCb4, PCb5 Contact part PCe, PCe1, PCe2, PCe4, PCe5 Apex part PCf Flat part PDb, PDb1, PDb2 Probe pin tip PE Probe pin PEb1, PEb2, PEb3 Contact part PEb4, PEb5, PEb6 Probe pin tip RS Sealed body SB External terminal ( Solder balls)
SC Semiconductor chip SM Semiconductor device TS IC test socket WC Conductive wire

Claims (14)

A semiconductor device manufacturing method including the following steps:
(A) preparing a semiconductor device including a semiconductor chip and provided with a plurality of external terminals electrically connected to a semiconductor integrated circuit formed on a main surface of the semiconductor chip;
(B) a step of inspecting electrical characteristics of the semiconductor integrated circuit by bringing a plurality of probe pins into contact with the plurality of external terminals,
Here, the surface of the tip of the contact portion of the probe pin that comes into contact with the external terminal is periodically roughened at a first interval, and the first interval is one in the range of 50 nm to 5 μm. Value. In the manufacturing method of the semiconductor device according to claim 1,
A plurality of striped patterns are formed on the surface of the tip of the contact portion by the uneven processing. In the manufacturing method of the semiconductor device according to claim 1,
A plurality of dot-like patterns are formed on the surface of the tip of the contact portion by the uneven processing. In the manufacturing method of the semiconductor device according to claim 1,
Using the femtosecond laser, the surface of the tip of the contact portion is subjected to the uneven processing. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion has a BeCu or SK material as a base material, and a conductive film made of Pd alloy, Au, AuCo, Rh, Ru, Ir, or AuNi is formed on the surface of the base material through a barrier film. The unevenness is applied to the surface of the conductive film. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion includes a BeCu or SK material as a base material, and a conductive film made of Rh, Ru, or Ir is formed on the surface of the base material, and the unevenness processing is applied to the surface of the conductive film. Yes. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion uses a Pd alloy as a base material, and the surface of the base material is subjected to the uneven processing. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion has a BeCu or SK material as a base material, a conductive film made of a Pd alloy is formed on the surface of the base material via a barrier film, and the unevenness processing is performed on the surface of the conductive film, Further, the surface of the conductive film is covered with a conductive DLC film. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion includes a BeCu or SK material as a base material, a conductive film made of Rh, Ru, or Ir is formed on the surface of the base material, and the unevenness processing is performed on the surface of the conductive film. The surface of the conductive film is covered with a conductive DLC film. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion is made of a Pd alloy as a base material, the surface of the base material is subjected to the uneven processing, and the surface of the base material is covered with a conductive DLC film. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion has a BeCu or SK material as a base material, and a conductive film made of Au, AuCo, or AuNi is formed on the surface of the base material through a barrier film in a region other than the tip of the contact portion, In the region of the tip of the contact portion, a conductive DLC film is formed on the surface of the base material via the barrier film, and the unevenness processing is performed on the surface of the barrier film. In the manufacturing method of the semiconductor device according to claim 1,
The contact portion has a BeCu or SK material as a base material, and a conductive film made of Au, AuCo, or AuNi is formed on the surface of the base material through a barrier film in a region other than the tip of the contact portion, In the region at the tip of the contact portion, a conductive DLC film is formed on the surface of the base material via the barrier film, and the unevenness processing is performed on the surface of the DLC film.   13. The method for manufacturing a semiconductor device according to claim 5, 8, 11, or 12, wherein the barrier film is made of Ni.   13. The method for manufacturing a semiconductor device according to any one of claims 5, 6, 8, 9, 11, or 12, wherein the conductive film is formed by a plating method.