CN107491407B - Self-adapting high-speed Transmission system based on SERDES in FPGA - Google Patents
Self-adapting high-speed Transmission system based on SERDES in FPGA Download PDFInfo
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- CN107491407B CN107491407B CN201710532840.6A CN201710532840A CN107491407B CN 107491407 B CN107491407 B CN 107491407B CN 201710532840 A CN201710532840 A CN 201710532840A CN 107491407 B CN107491407 B CN 107491407B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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Abstract
Based on the self-adapting high-speed Transmission system of SERDES in FPGA, sending module sends self-adaptive training sequence, real-time dynamic training sequences, operational data to receiving module；Adaptive training receiving module carries out bit correction and clock edge and the center of data window is aligned, and carries out word correction and recovers correct training sequence, and the two cooperates, and realizes being properly received for training sequence；Actual working state of the module of dynamic adjustment in real time according to system, dynamic adjusting data line time delay enable clock to snap to the center of data window always, guarantee the timeliness of time delay adjustment.Present system dynamically adjusts the relative time delay relationship for receiving data window and clock by adaptive training mode in real time, data transmission interface can be made constantly to adapt to the variation of external environment, avoid data sampling mistake caused by shaking due to delay skew, to ensure that the reliable transmission of data, there is good use value.
Description
Technical field
The present invention relates to a kind of self-adapting high-speed Transmission systems based on SERDES in FPGA.
Background technique
With the rapid development of Digital Signal Processing, the band of the digital signal processing appts processing based on FPGA circuitry
Wide, rate and scale are continuously improved.However since FPGA internal logic unit processing speed is limited, the high speed of Yao Shixian data is passed
Defeated to need to be converted to parallel low speed data high-speed serial data, receiving end is using the ISERDES unit in FPGA piece input
Converting high-speed serial be changed to low-speed parallel data.If serial data as multichannel is transmitted parallel, so that it may
Realize bigger transmission bandwidth.
In high speed data transmission interface, as single wire transmission rate is continuously improved, keep time window shared by data continuous
Reduce, sampling clock is caused to be difficult to accurately be sampled in its valid interval to the sampled point of signal wire；Along with transmission path
Difference, the delay time that each data line and sampling clock reach receiving end cannot be guaranteed it is completely the same, to bring each letter
Position offset and word offset between number line.Position offset refers to that sampling clock, can along not sampling in the center of each data window
Can will lead to the data sampling retention time falls short of, and easily makes bit that abrupt transients occur, unstable so as to cause received data
It is fixed；Word offset refer to sampling receive after each data-signal between it is asynchronous so that simultaneously transmitting terminal send data connecing
Receiving end is but unable to synchronization and is sampled, and leads to received data invalid.
Static time delay Adjusted Option makes each signal in its transmission by adjusting the relative time delay relationship of clock line and data line
It is delayed on line equal, to guarantee that the clock edge of data acquisition should be at optimum sampling position.Static time delay Adjusted Option process
Workload is huge, and parameter state of its setting is just for current application state and physical state, when application state is changed
Or physical state changes, the parameter originally set just may be no longer applicable in, can not be correctly to data so as to cause clock edge
It is sampled, needs to manually adjust relative time delay relationship again.Adaptive dynamic delay adjustment technology is then according to current each signal
Line physical state carries out offset operation to each signal wire automatically, so that the parameter for adjusting time delay is suitble to present physical state,
It ensure that the timeliness of phase adjustment.So adaptive dynamic delay adjustment technology can make communication interface constantly adapt to outside
The variation of environment, data sampling mistake caused by avoiding due to delay skew, to ensure that the reliable transmission of data.
Although existing adaptive dynamic delay adjustment technology to a certain extent can be automatically to data line and clock line
Relativeness is adjusted, but there is certain limitation, such as: detection algorithm can only be examined for specific training sequence
It surveys；There are problems that data jump along error detection.In addition, existing adaptive dynamic delay adjustment technology is detected into for the first time
Just start to transmit normal data after function, if during the work time, it, just can not be real since the external environments such as high/low temperature change
When dynamic adjusting data line and clock line relative time delay relationship, data sampling is wrong caused by may cause due to delay skew
Accidentally, the reliable transmission of data is not can guarantee.
Summary of the invention
Technical problem solved by the present invention is having overcome the deficiencies of the prior art and provide a kind of based on SERDES in FPGA
Self-adapting high-speed Transmission system, by adaptive training mode in real time dynamically adjustment receive data window and clock it is opposite when
Prolong relationship, data transmission interface can be made constantly to adapt to the variation of external environment, avoids caused by being shaken due to delay skew
Data sampling mistake, to ensure that the reliable transmission of data.
The technical solution of the invention is as follows: the self-adapting high-speed Transmission system based on SERDES in FPGA, including sends
Module, receiving module, wherein
Sending module sends self-adaptive training sequence, real-time dynamic training sequences to receiving module；When sampling clock is along position
In self-adaptive training sequence parallel data the parallel data of the center of each data window and self-adaptive training sequence output with
When the self-adaptive training sequence that sending module is sent is synchronous and consistent, operational data is sent to receiving module；
Receiving module carries out time delay adjustment to self-adaptive training sequence or operational data, updates the first time delay value, clock synchronization
Prolong serial self-adaptable training sequence adjusted or operational data carries out the first 1:N serioparallel exchange, so that sampling clock is along position
Then the center of each data window in parallel data adjusts the word offset of self-adaptive training sequence or operational data, makes
It is synchronous with the self-adaptive training sequence or operational data that sending module is sent and consistent to obtain parallel data output, and it is inclined to update word
The first bits of offset moved；
Time delay adjustment is carried out to real-time dynamic training sequences, updates the second time delay value, real-time dynamic adjusted to time delay
Training sequence carries out the 2nd 1:N serioparallel exchange, so that sampling clock edge is located at the center of each data window in parallel data, so
The word offset of real-time dynamic training sequences is adjusted afterwards, so that the real-time dynamic training sequence that parallel data output is sent with sending module
Column are synchronous and consistent, and update the second bits of offset of word offset, then by current second time delay value and preceding second time delay value of update
It is made the difference, obtains Delay Variation amount, and as the first time delay value, the increment of the second time delay value；First serioparallel exchange
It is carried out according to the first bits of offset of word offset, the second serioparallel exchange is carried out according to the second bits of offset of word offset；First, second partially
Shifting initial value is 0；The initial value of the first time delay value, the second time delay value that the time delay adjusts is 0, and increment initial value is 1.
The method that the receiving module carries out time delay adjustment are as follows: initial value or current time delay value and increasing to time delay adjustment
Amount is summed.
The receiving module using 1,2,3 ... N as the bits of offset of word offset by successively making parallel data defeated
It is synchronous and consistent with the self-adaptive training sequence or operational data that sending module is sent out.
The receiving module makes the sampling clock include along the method for center for being located at each data window in parallel data
Following steps:
(1) time delay adjustment is carried out to self-adaptive training sequence or operational data, then by time delay trained sequence adjusted
Column or operational data carry out 1:N serioparallel exchange；
(2) when first time parallel data exports the continuous N clock cycle and self-adaptive training sequence or operational data are same
When walking and is consistent, continue time delay adjustment, until second of parallel data output continuous N clock cycle and adaptive training
Sequence or operational data are synchronous and consistent, using time delay value at this time as A；
(3) continue time delay adjustment, until third time parallel data output continuous N clock cycle and adaptive training
Sequence or operational data are synchronous and consistent, using time delay value at this time as B；
(4) time delay is adjusted to (A+B)/2, so that sampling clock is along the centre bit for being located at each data window in parallel data
It sets.
The sending module, receiving module carry out data interaction by the I/O pin of FPGA.
The receiving module includes adaptive training receiving unit, real-time dynamic adjustment unit；Adaptive training receives
Unit carries out time delay adjustment to self-adaptive training sequence or operational data, the first time delay value is updated, to time delay string adjusted
Row self-adaptive training sequence or operational data carry out the first 1:N serioparallel exchange, so that sampling clock is along in parallel data
Then the center of each data window adjusts the word offset of self-adaptive training sequence or operational data, so that parallel data is defeated
It is synchronous and consistent with the self-adaptive training sequence or operational data that sending module is sent out, and update the first offset of word offset
Position；
Real-time dynamic adjustment unit carries out time delay adjustment to real-time dynamic training sequences, the second time delay value is updated, to time delay
Real-time dynamic training sequences adjusted carry out the 2nd 1:N serioparallel exchange, so that sampling clock is along positioned at each number in parallel data
According to the center of window, the word offset of real-time dynamic training sequences is then adjusted, so that parallel data output is sent out with sending module
The real-time dynamic training sequences sent are synchronous and consistent, and update the second bits of offset of word offset, then by current second time delay value
It is made the difference with preceding second time delay value is updated, obtains Delay Variation amount, and as the first time delay value, the increment of the second time delay value.
The advantages of the present invention over the prior art are that:
(1) present invention is solved by the relative time delay relationship of adaptive training mode adjust automatically data line and clock line
Delay parameter needs the problem of manually adjusting in static time delay Adjusted Option, improves design efficiency；
(2) present invention is closed by the relative time delay of dynamic adjustment module real-time dynamic monitoring data line and clock line in real time
System, so that clock is snapped to the center of data window always, solve due to external environment variation cause delay skew into
And cause to receive data sampling mistake, it ensure that the reliability of data transmission.
Detailed description of the invention
Fig. 1 is a kind of self-adapting high-speed Transmission system realization principle figure based on SERDES in FPGA of the present invention；
Fig. 2 is receiving module realization principle figure in present system；
Fig. 3 is adaptively to adjust principle flow chart in present system；
Fig. 4 is bit correction and word correction principle schematic diagram in present system.
Specific embodiment
In view of the deficiencies of the prior art, the present invention proposes a kind of self-adapting high-speeds based on SERDES in FPGA to transmit system
System is dynamically adjusted the relative time delay relationship for receiving data window and clock in real time by adaptive training mode, can make data
Coffret constantly adapts to the variation of external environment, avoids data sampling mistake caused by shaking due to delay skew, thus
It ensure that the reliable transmission of data.The present invention provides the real-time dynamic delay adjustment sides that high speed data transmission system can use
Case, can be automatic, real-time according to current each signal wire physical state, after each system electrification and in course of normal operation
Ground carries out time delay adjustment to each signal wire, makes it suitable for present physical state, ensure that automaticity, the timeliness of time delay adjustment,
Present system is described in detail with reference to the accompanying drawing.
It is as shown in Figure 1 a kind of self-adapting high-speed Transmission system realization principle figure based on SERDES in FPGA of the present invention,
The High-speed serial data signal that sending module is converted to the parallel data compared with low rate, receiving module pass through adaptive training
Mode completes between data and data, data and clock it is synchronous, serial data is reverted into parallel data, and by real-time
Dynamic training sequences carry out dynamic in real time to the synchronism for receiving data and clock and adjust.
One, sending module
In transmitting terminal, sends data and is divided into two major classes:
One kind is self-adaptive training sequence/operational data.Self-adaptive training sequence/operational data is divided into two parts again: from
Adaptation training sequence and operational data.The adaptive training state instruction mark that transmitting terminal is fed back according to receiving end determines to send
Self-adaptive training sequence or operational data send self-adaptive training sequence when adaptive training state instruction mark is 0,
When Warning Mark is 1, operational data is sent.After system electrification or reset, adaptive training state instruction mark is initial
0 is turned to, each 16 bit data in the road I, the road Q of input presses 4 bit groupings, is respectively divided into 4 groups.Every group of 4 bit data parallel-serial conversions are 4
The single-bit signal of haplotype data rate is sent to receiving module by the I/O pin of FPGA.
One kind is real-time dynamic training sequences.Real-time dynamic training sequences are sent for a long time, for receiving end according to practical work
Make state and dynamically adjusts time delay in real time, which is 4 bits, with the single-bit signal of 4 haplotype data rates after parallel-serial conversion,
Receiving module is sent to by the I/O pin of FPGA.
Two, receiving module
Receiving module in present system realizes structure chart in detail as shown in Fig. 2, receiving module is divided into two parts: adaptive
Receiving module, the module of dynamic adjustment in real time should be trained.
(1) adaptive training receiving module
When system electrification or reset, adaptive training state instruction mark is initialized as 0, and adaptive training connects at this time
It receives module and time delay and bits of offset is adaptively adjusted according to the training sequence received, if recovering training sequence (i.e. adaptive instruction
Practice receiving module and obtain time delay and bits of offset), adaptive training state instruction mark is set to 1, and notice transmitting terminal can start to send out
Send operational data.
The target of bit correction is so that clock edge and the alignment of the center of data window, the target of word correction is to pass through tune
Whole word offset bit recovery goes out correct training sequence, and the two cooperates, and realizes being properly received for training sequence.Present system
Middle adaptive training receiving module scheme specific implementation flow chart is as shown in Figure 3.
Specific workflow is as follows:
1) time delay tune is carried out by IODELAY unit to per serial data (self-adaptive training sequence or operational data) all the way
It is whole, wherein the time delay initial value of time delay adjustment is 0, increment 1；
2) IODELAY unit time delay serial data adjusted is sent into ISERDES unit, carries out 1:4 serioparallel exchange
(the bits of offset initial value of ISERDES unit is 0)；
3) data multiplexing module splices the parallel data after serioparallel exchange, forms each 16 bit data of I, Q；
4) bit correction module carries out self-adapting detecting, carries out to each data line according to the parallel data after multiple connection
Accurate wire delay makes sampling clock along the center for being placed exactly in respective signal data window, the bit of each data channel
After correction adjustment is completed, ready signal is sent to its word correction module respectively；
5) word correction module carries out word adjustment by adjusting word offset, makes to instruct in the parallel output data of each data line
Practice sequences match, so that the parallel output of each data line of receiving end all keeps synchronous, at this time i.e. it is believed that receiving end is completed
Adaptive training function, wherein word correction module realizes the parallel output data of each data line occur by traversal 1,2,3,4
Training sequence matching, when a match occurs using digit at this time as new bits of offset, when carrying out 1:N serioparallel exchange, traversal
1,2,3 ... N, N are positive integer；
6) after the completion of training, that is, training sequence is recovered, adaptive training state instruction mark is then set to 1, notice
Transmitting terminal can start to send operational data；
7) according to the Delay Variation amount dynamic adjusting data line time delay that dynamic adjustment module is sent in real time, guarantee time delay adjustment
Timeliness, i.e., the current increment for carrying out time delay adjustment is set to Delay Variation amount.
The key of adaptive Adjusted Option is to be automatically found the left margin of data window and the right edge, if Fig. 3 is the present invention
Principle flow chart is adaptively adjusted in system, if Fig. 4 is bit correction and word correction principle schematic diagram in present system.In work
During work, the output of real-time detection ISERDES, if output and the self-adaptive training sequence of continuous 1000 clock cycle
Or operational data is consistent, then it is assumed that this matching is successful.Increase delay TAP (i.e. time delay) numerical value if unsuccessful to the
Successful match, and must not believe that clock along the center for being aligned data window when first time successful match, it is therefore desirable to
Delay is continued growing until matching failure, continues growing TAP value later until second of successful match, second of successful match can
To be considered the left edge of clock alignment data window, current TAP value is denoted as A.Then, need to continue displacement until clock alignment number
According to the right edge of window.When clock edge reach data window on the right of along when, record at this time TAP numerical value be B, calculate target value (A+
B)/2, by TAP value adjusted value target value (A+B)/2, then clock edge can be snapped to the center of data window, wherein
When not receiving the Delay Variation amount for dynamically adjusting module transmission in real time, the increment of TAP is 1, dynamically adjusts mould in real time when receiving
When the Delay Variation amount that block is sent, the increment of TAP is Delay Variation amount, and Fig. 3 is illustrated so that increment is 1 as an example.
(2) module of dynamic adjustment in real time
The main function of the module of dynamic adjustment in real time is actual working state according to system, when dynamic adjusting data line
Prolong, clock is enable to snap to the center of data window always, guarantees the timeliness of time delay adjustment.
The module is trained according to time delay and bits of offset is adaptively adjusted according to the real-time dynamic training sequences received first
After success, current time delay numerical value is recorded, then restarts to train, after training succeeds again, when recording current again
Prolong numerical value, the numerical value and last time delay numerical value are done into difference, then export Delay Variation amount to adaptive training module.
It is trained repeatedly, persistently exports Delay Variation amount.
Specific workflow is as follows:
1) time delay adjustment is carried out by IODELAY unit to serial data, wherein the time delay initial value of time delay adjustment is 0, is increased
Amount is 1；
2) IODELAY unit output data is sent into ISERDES unit (carrying out serioparallel exchange), carries out 1:4 serioparallel exchange
(the bits of offset initial value of ISERDES unit is 0)；
3) bit correction module carries out self-adapting detecting, to each data line according to the parallel data after serioparallel exchange
Accurate wire delay is carried out, makes sampling clock along the center for being placed exactly in respective signal data window.Each data channel
After bit correction adjustment is completed, ready signal is sent to its word correction module respectively；
4) word correction module carries out word adjustment by adjusting word offset, makes to instruct in the parallel output data of each data line
Practice sequences match, so that the parallel output of each data line of receiving end all keeps synchronous, at this time i.e. it is believed that receiving end is completed
Adaptive training function records current time delay numerical value, bits of offset, updates the inclined of the module of dynamic adjustment in real time using the bits of offset
Initial value is shifted, then restarts to train；
5) after training succeeds again, current time delay numerical value is recorded again, by the numerical value and last time delay numerical value
Difference is done, then exports Delay Variation amount to adaptive training module.It is trained repeatedly, persistently exports Delay Variation
Amount.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (5)
1. the self-adapting high-speed Transmission system based on SERDES in FPGA, it is characterised in that including sending module, receiving module,
In
Sending module sends self-adaptive training sequence, real-time dynamic training sequences to receiving module；When sampling clock is along positioned at certainly
The output of the parallel data of the center of each data window and self-adaptive training sequence and transmission in adaptation training sequential parallel data
When the self-adaptive training sequence that module is sent is synchronous and consistent, operational data is sent to receiving module；
Receiving module carries out time delay adjustment to self-adaptive training sequence or operational data or real-time dynamic training sequences, more
New time delay value distinguishes time delay serial self-adaptable training sequence adjusted or operational data or real-time dynamic training sequences
1:N serioparallel exchange is carried out, so that sampling clock is along the center for being located at each data window in parallel data, then adjustment is adaptive
The word offset of training sequence or operational data or real-time dynamic training sequences, so that parallel data output is sent out with sending module
The self-adaptive training sequence or operational data that send be synchronous or dynamic training sequences and consistent in real time, and updates the inclined of word offset
Displacement, while calculation delay variable quantity, the increment as time delay value；
The receiving module includes adaptive training receiving unit, real-time dynamic adjustment unit；Adaptive training receiving unit,
Time delay adjustment is carried out to self-adaptive training sequence or operational data, updates the first time delay value, it is adjusted to time delay it is serial from
Adaptation training sequence or operational data carry out the first 1:N serioparallel exchange, so that sampling clock is along positioned at each number in parallel data
According to the center of window, then adjust the word offset of self-adaptive training sequence or operational data so that parallel data output with
The self-adaptive training sequence or operational data that sending module is sent are synchronous and consistent, and update the first bits of offset of word offset；
Real-time dynamic adjustment unit carries out time delay adjustment to real-time dynamic training sequences, updates the second time delay value, adjusts to time delay
Real-time dynamic training sequences afterwards carry out the 2nd 1:N serioparallel exchange, so that sampling clock is along positioned at each data window in parallel data
Center, then adjust the word offset of real-time dynamic training sequences so that parallel data output with sending module send
Real-time dynamic training sequences are synchronous and consistent, and update the second bits of offset of word offset, then by current second time delay value and more
New preceding second time delay value is made the difference, and obtains Delay Variation amount, and as the first time delay value, the increment of the second time delay value；It is described
The first serioparallel exchange carried out according to the first bits of offset of word offset, the second serioparallel exchange according to the second bits of offset of word offset into
Row；First, second bits of offset initial value is 0；The initial value of the first time delay value, the second time delay value that the time delay adjusts is 0, is increased
Measuring initial value is 1.
2. the self-adapting high-speed Transmission system according to claim 1 based on SERDES in FPGA, it is characterised in that: described
The receiving module method that carries out time delay adjustment are as follows: sum to the initial value or current time delay value of time delay adjustment with increment.
3. the self-adapting high-speed Transmission system according to claim 1 or 2 based on SERDES in FPGA, it is characterised in that:
The receiving module is by successively making parallel data output as the bits of offset of word offset for 1,2,3 ... N and sending
The self-adaptive training sequence or operational data that module is sent are synchronous and consistent.
4. the self-adapting high-speed Transmission system according to claim 1 or 2 based on SERDES in FPGA, it is characterised in that:
The receiving module includes the following steps: sampling clock along the method for being located at the center of each data window in parallel data
(1) time delay adjustment is carried out to self-adaptive training sequence or operational data, then by time delay training sequence adjusted or
Person's operational data carries out 1:N serioparallel exchange；
(2) when first time parallel data output the continuous N clock cycle it is synchronous with self-adaptive training sequence or operational data and
When consistent, continue time delay adjustment, until second of parallel data output continuous N clock cycle and self-adaptive training sequence
Or operational data is synchronous and consistent, using time delay value at this time as A；
(3) continue time delay adjustment, until third time parallel data output continuous N clock cycle and self-adaptive training sequence
Or operational data is synchronous and consistent, using time delay value at this time as B；
(4) time delay is adjusted to (A+B)/2, so that sampling clock is along the center for being located at each data window in parallel data.
5. the self-adapting high-speed Transmission system according to claim 1 or 2 based on SERDES in FPGA, it is characterised in that:
The sending module, receiving module carry out data interaction by the I/O pin of FPGA.
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| CN110162503B (en) * | 2019-05-23 | 2024-03-22 | 灿芯半导体(上海)股份有限公司 | High-speed data synchronization circuit and data synchronization method |
| CN111143269A (en) * | 2020-01-09 | 2020-05-12 | 四川卫士通信息安全平台技术有限公司 | Boundary clock window determining method, circuit, terminal equipment and storage medium |
| CN111586324B (en) * | 2020-05-25 | 2021-08-31 | 中国科学院长春光学精密机械与物理研究所 | Serial CMOS image data training method adaptive to real-time line period change |
| CN112306943B (en) * | 2020-11-08 | 2023-03-07 | 西安电子工程研究所 | Idelay real-time adjustment method based on FPGA high-speed SerDes |
| WO2022252197A1 (en) * | 2021-06-03 | 2022-12-08 | 华为技术有限公司 | Transmitter, receiver, parameter adjustment method, serdes circuit and electronic device |
| CN113886300B (en) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
| CN114896186B (en) * | 2022-05-23 | 2023-09-26 | 北京计算机技术及应用研究所 | Pre-training-based FPGA and external bus data interaction method |
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| CN107491407A (en) | 2017-12-19 |
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