CN109302257A - A kind of implementation method of the OTL agreement multi-channel data alignment based on FPGA - Google Patents

Abstract

The implementation method for the OTL agreement multi-channel data alignment based on FPGA that the invention discloses a kind of.This method has the following steps: 1, inputting after respective fifo module is cached each channel data and read；2, each channel data of fifo output is inputted respective head marker module to carry out finding frame head operation, exports head_flag signal；3, align module receives head_flag signal and is handled, and output rd signal is read out control to each fifo module；4, align module is judged by the head_flag signal inputted, exports alignment identification signal align_ok, and signal is drawn high expression alignment and completed, and is dragged down expression and is not completed alignment.This method realizes the function of OTL agreement multi-channel data alignment inside FPGA, has a wide range of applications in fields such as fiber optic communication, fiber data acquisition, digital communications.

Description

A kind of implementation method of the OTL agreement multi-channel data alignment based on FPGA

Technical field

The present invention relates to fields such as fiber optic communication, fiber data acquisition, digital communication more particularly to a kind of based on FPGA's The implementation method of OTL agreement multi-channel data alignment.

Background technique

With the development of communication technology, the demand to big data quantity high-speed transfer is higher and higher, and conventional one-channel is limited Transmission bandwidth is not able to satisfy current demand, and multi-channel parallel transmission becomes widely applied solution.

In fiber backbone network, the OTN signal for supporting channel transmission is mainly carry, the interface protocol of OTN signal is OTL (Optical Transport Lane), means optical transmission line agreement, assists including OTL3.4, OTL4.4, OTL4.10 etc. View.Due to the long distance transmission of optical fiber and the error of receiving device, each channel data is on receiving end easily time of occurrence Deviation, each channel data cannot reach in synchronization, and some channel datas are relatively advanced, and some channel datas are relatively stagnant Afterwards, how registration process is carried out to each channel, is the difficult point for being properly received OTL agreement.

Summary of the invention

In view of present technology there are the problem of, the present invention provide it is a kind of based on FPGA OTL agreement multi-channel data alignment Implementation method.Present invention aim to solve problems of the prior art, it is more that OTL agreement is completed using FPGA The technology of channel data alignment, the function of alignment OTL agreement multi-channel data is completed by FPGA.This method is real inside FPGA Show the feedback system being made of fifo module, head marker module, align module, thus adjusts prolonging for each channel data When time and relative position, to achieve the purpose that each channel data alignment of OTL agreement.

The technical solution adopted by the present invention is that: a kind of implementation method of the OTL agreement multi-channel data alignment based on FPGA, This method is using fpga chip as the platform of sequence, which is characterized in that steps are as follows:

One, each channel data is inputted after respective fifo module is cached and is read, fifo is first input first The abbreviation of output is a kind of data buffer of first in first out, can be realized and be sequentially written in and sequentially read, used Fifo interface include: Data Input Interface din, data output interface dout, write-in enable signal wr, read enable signal rd, Clock clock is driven, when it is high level that enable signal wr, which is written, the data of din interface, into fifo, work as reading by clock buffer When to take enable signal rd be high level, the data in fifo are write by clock output if the data in each channel are effective from dout interface Entering enable signal wr is often high level, and during not completing alignment, reading enable signal rd, which has, drags down a clock week The case where phase, occurs, and after completing alignment, reading enable signal rd is often high level, and the data of each fifo output are at this time The channel data of alignment；

Two, each channel data of fifo output respective head marker module is inputted to carry out finding frame head operation, output Head_flag signal, head marker module carry out frame head search to the data of input, and head_flag signal is often low electricity Flat, when present clock period finds frame head, next clock cycle head_flag signal is drawn high, and is dragged down and is kept again later；

Three, align module receives head_flag signal and is handled, and output rd signal is read out control to each fifo module System, align module are to realize the main module of channel data alignment, and align module passes through control rd Signal Regulation fifo mould The output of block, and then adjust the delay time of the fifo each channel data exported and relative position；

Four, align module is judged by the head_flag signal inputted, exports alignment identification signal align_ok, signal It draws high expression alignment to complete, drags down expression and do not complete alignment.

The beneficial effect comprise that: in optical communication field, based on OTL transport protocol (OTL3.4, OTL4.4, OTL4.10), the factors such as optical fiber distance transmission and receiving device error will cause the channel data offset of receiving end, this inclined The continuity destroyed between each channel data in time is moved, the present invention provides a kind of, and the time adjustment based on receiving end is mended Compensation structure realizes multi-channel data alignment function, has restored continuity in time between each channel data, for it is subsequent into One step correctly parses data content and provides necessary condition.Channel alignment is realized by conventional equipment, generally uses embedded chip The calculating of each channel compensation time is carried out, then sends fpga chip for calculated result by embedded chip to realize channel pair Together, structure used by this method does not need the assist process of external embedded chip based entirely on fpga chip, reduces embedding The usage quantity for entering formula chip reduces the purchase cost of embedded chip, enormously simplifies the layout complexity journey of PCB circuit board Degree, reduces the cost of manufacture of PCB circuit board.This method realizes the function of OTL agreement multi-channel data alignment inside FPGA Can, have a wide range of applications in fields such as fiber optic communication, fiber data acquisition, digital communications.

Detailed description of the invention

Fig. 1 is OTL3.4 protocol frame structural schematic diagram of the present invention；

Fig. 2 is OTL4.4 and OTL4.10 protocol frame structural schematic diagram of the present invention；

Fig. 3 is OTL3.4 agreement frame head position view of the present invention；

Fig. 4 is OTL4.4 and OTL4.10 agreement frame head position view of the present invention；

Fig. 5 is OTL3.4 protocol channel data advancing offset schematic diagram of the present invention；

Fig. 6 is OTL3.4 protocol channel data hysteresis offset schematic diagram of the present invention；

Fig. 7 is fifo module interface structural schematic diagram of the present invention；

Fig. 8 is that fifo module of the present invention reads time diagram；

Fig. 9 is head marker module interface structural schematic diagram of the present invention；

Figure 10 is head marker module working sequence schematic diagram of the present invention；

Figure 11 is align module interface structural schematic diagram of the present invention；

Figure 12 is OTL protocol channel alignment of data function general structure schematic diagram of the present invention；

Figure 13 is the logical flow chart that 4 channel align modules of the invention control rd signal；

Figure 14 is the logical flow chart of align module alignment state-detection of the present invention；

Figure 15 is the channel alignment procedure schematic diagram that OTL3.4 agreement single-channel data of the present invention lagged for 1 clock cycle.

Specific embodiment

The present invention will be further described below with reference to the accompanying drawings.

Multidiameter delay data are received based on FPGA, refer to that FPGA receives multi-channel data, each channel is 1 clock week Phase transmits 1 data, and for N (N >=2) a channel, FPGA connects N number of data in 1 clock cycle, this is multidiameter delay The meaning of data.

OTL3.4 agreement frame structure is as shown in Figure 1, the information content of a frame is 16320Byte, wherein each grid indicates The 1:16 of grid indicates the 1st to 16Byte data where the information of 16Byte bit wide, such as framehead mark, and 1Byte is 8bit bit wide, OTL3.4 agreement include 4 channels, have 255 column with the every frame of rule arrangement of Fig. 1.

The frame structure of OTL4.4 and OTL4.10 agreement as shown in Fig. 2, the information content of a frame is identical as OTL3.4 protocol frame, For 16320Byte, arrangement rule is similar with OTL3.4 agreement frame structure, and difference is that port number increase is 20, corresponding every Frame columns is reduced to 51.

For alignment function mainly using the position that frame head occurs as parameter foundation, what Fig. 3 was indicated is OTL3.4 agreement frame head position Schematic diagram is set, can intuitively show that the occurrence law of frame head, the frame head of every frame are occurred by channel rotation, such as: the 1st frame frame Head appear in channel 0(channel 0), the 2nd frame frame head appear in channel 1(channel 1), the 3rd frame frame head appear in channel 2 (channel 2), the 4th frame frame head appear in channel 3(channel 3), the 5th frame frame head appear in channel 0(channel again 0) it, being moved in circles with this, the frame head of multichannel occurs at equal intervals with N number of clock cycle, for single channel, frame head every 4 Frame occurs 1 time, and (1 data frame has the width of N number of clock cycle in figure, then single channel every 4N clock cycle occurs once Frame head), occur at equal intervals with 4N clock cycle, the frame head occurrence law in single channel be it is fixed, not by transmission delay etc. The influence of factor.

For OTL4.4 and OTL4.10 agreement frame header position as shown in figure 4, its arrangement rule is similar with Fig. 3, difference is channel Increase be 20, every frame frame head successively appears in channel 0(channel 0), channel 1(channel 1) ..., channel 18 (channel 18), channel 19(channel 19), channel 0(channel 0), moved in circles with this, multichannel frame head is with N number of Clock cycle occurs at equal intervals, and 1 frame head occurs in single every 20 frame in channel, occurs at equal intervals with 20N clock cycle.

The frame head occurrence law in single channel is fixed and invariable, and there may be offsets between the channel of multichannel, existing It may be advancing offset, it is also possible to it is hysteresis offset, it is convenient for statement, by taking OTL3.4 agreement as an example, advancing offset such as Fig. 5 institute Show, channel 1(channel 1) with respect to other channels advanced 1 clock cycle, with channel 0(channel 0)；Hysteresis offset is such as Shown in Fig. 6, channel 1(channel 1) with respect to other channels 1 clock cycle of lag；It is advanced and lag issues in order to eliminate It influences, provides solution by step as follows.

It is read 1. each channel data is inputted after respective fifo module is cached.

Fifo of the present invention is as shown in fig. 7, its interface includes: Data Input Interface din, data output interface Dout, write-in enable signal wr, enable signal rd, driving clock clock are read, when it is high level that enable signal wr, which is written, The data of din interface are by clock buffer into fifo, and when reading enable signal rd is high level, data in fifo are from dout Interface presses clock output, and in the present invention, if the data in each channel are effective, write-in enable signal wr is often high level, and data are deposited Enter fifo, during not completing alignment, reads enable signal rd and have the case where dragging down clock cycle appearance, complete After alignment, reading enable signal rd is often high level, and the reading timing of fifo is as shown in figure 8, when rd signal drags down, fifo Output remain unchanged, when drawing high, fifo exports remaining data in order, logical by control rd Signal Regulation output with this The delay time of track data.

2. each channel data of fifo output is inputted respective head marker module to carry out finding frame head operation, it is defeated Head_flag signal out.

Head marker module diagram is as shown in figure 9, its interface includes: Data Input Interface din, output signal Head_flag, driving clock clock, head marker module carry out frame head search, head_flag signal to the data of input It is often low level, when present clock period finds frame head, next clock cycle head_flag signal is drawn high, and is dragged down again later And keep, temporal characteristics can refer to Figure 10.

3. align module receives head_flag signal and handled, output rd signal reads each fifo module Take control.

Align module is to realize the main module of channel data alignment, and as shown in figure 11, interface includes: that signal is defeated Incoming interface head_flag [N-1:0], it signal output interface rd [N-1:0], alignment mark signal output interface align_ok, drives Dynamic clock clock, wherein head_flag signal and rd signal are signal bus, and the meaning of rd [N-1:0] is by rd [0], rd [1] ..., the bus of rd [N-1] N number of signal composition altogether, similarly, head_flag [N-1:0] be head_flag [0], Head_flag [1] ..., the bus of head_flag [N-1] N number of signal composition altogether；Align module passes through control rd The output of Signal Regulation fifo module, and then adjust the delay time of the fifo each channel data exported and relative position, The logic for controlling rd signal is as shown in figure 13, and for Figure 13 by taking OTL3.4 agreement as an example, input and output are 4 channel signals, is expressed as 16 bit register cnt [15:0] are arranged as counter, logical circuit of counter are as follows: judgement in head_flag [3:0], rd [3:0] first Whether head_flag [3:0] bus of input is not equal to 0, by cnt [15:0] clear 0 if not equal to 0, continues to be transferred to judgement Head_flag, if being equal to 0 by cnt [15:0] from plus 1 for counting, continue to be transferred to and judge head_flag；The control of rd signal Logic are as follows: judge whether head_flag [3:0] bus of input is not equal to 0, rd [3:0] all draws high (rd's if being equal to 0 1) 4bit assignment is all, continue to be transferred to and judge head_flag, if continue judge not equal to 0 cnt [15:0] whether less than N-1(this In N refer to the clock periodicity of normal interval between multichannel frame head, it is consistent with the definition of N in Fig. 3), if it is greater than or equal to N-1 Then rd [3:0] all draws high (the 4bit assignment of rd is all 1), drags down the rd signal for the channel of frame head occur if being less than N-1 Rd [3:0] is then all drawn high (the 4bit assignment of rd is all 1) again, continues to be transferred to and judge head_ by one clock cycle Flag, the logic that rd is dragged down are as follows: if head_flag [0] is height, indicate that frame head occurs in the 0th channel, if cnt [15:0] is less than N-1 indicates that the spacing of the 0th channel and previous frame is less than expection, and the 0th channel is relatively advanced, needs the 0th communication channel delay, corresponding Rd [0] drag down a clock cycle, concrete operations are that rd [0] and head_flag [0] exclusive or result are assigned to rd [0], symbol ^ is xor operation, and rd signal is often high level, therefore rd [0] is often 1, then rd [0] ^head_flag [0] actually 1^1 result Be 0, by result 0 be assigned to rd [0] with realize control fifo by channel 0 be delayed a clock cycle target, other channels Rd signal control principle is identical, and which is not described herein again, rd [3:0]≤rd [3:0] ^ head_flag [3:0] meaning in Figure 13 It is to be assigned to rd [3:0] or, obtaining a result for rd [3:0] is different with the corresponding position of head_flag [3:0], to realize to correspondence The delay in channel；It is directed to OTL agreement, complete alignment structures can refer to Figure 12.

4. align module is judged by the head_flag signal inputted, alignment identification signal align_ok is exported, Signal is drawn high expression alignment and is completed, and drags down expression and does not complete alignment.

Alignment identification signal align_ok indicates whether channel alignment is completed, and provides state instruction for subsequent processing, believes Number draw high expression alignment to complete, drag down expression and do not complete alignment, control logic such as Figure 14, Figure 14 by taking OTL3.4 agreement as an example, 32 bit register check [31:0] are set first as historical storage register, every 1bit of check register represents history The correctness of upper frame head appearance position, if position correctly if the bit be 0, be otherwise 1, the register constantly update, always deposit Store up the state of newest 32 frame.The historic state of Figure 14 stores logic are as follows: whether not to judge head_flag [3:0] bus of input Equal to 0, continue to be transferred to and judge head_flag if being equal to 0, if judging whether cnt [15:0] is not equal to N- at this time not equal to 0 1, if being not equal to N-1, indicate that the frame head does not appear in correct position, the low 30bit of check integrally moves up 1, and lowest order is inserted Enter 1, be then assigned to check [31:0], if being equal to N-1, indicate that the frame head appearance position is correct, the low 30bit of check is whole 1 is moved up, lowest order insertion 0, N here refers to the clock periodicity of normal interval between multichannel frame head, with N in Fig. 3 Definition is consistent；Align_ok signal control logic are as follows: whether the value for judging check [31:0] is 0, if 0, indicate continuous 32 frame Frame head appear in correct position, channel is aligned realization of goal, and align_ok signal is drawn high, after continue to judge check, if not 0, indicate that the frame head of 32 frame of history not exclusively appears in correct position, channel alignment is not implemented, and align_ok signal drags down.

Illustrate that OTL3.4 agreement single-channel data lags the channel alignment procedure of 1 clock cycle below with reference to Figure 15, such as schemes Shown in 15, to 0(cycle homoperiodic 0) in, the 1st channel (channel 1) opposite other channels stagnant the latter clock cycle, Align module detects the 2nd channel (channel 2) with respect to the frame head in the 1st channel (channel 1) apart from close, adjusting the 2nd Channel (channel 2) is delayed 1 clock cycle；To 1(cycle homoperiodic 1) in, the 1st channel (channel 1) and the 2nd The frame head spacing in channel (channel 2) is normal, and align module detects the 3rd channel (channel 3) with respect to the 2nd channel The frame head of (channel 2) is apart from close, the 3rd channel (channel 3) of adjusting 1 clock cycle of delay；To homoperiodic 2 In (cycle 2), the frame head spacing in the 2nd channel (channel 2) and the 3rd channel (channel 3) is normal, the inspection of align module The 0th channel (channel 0) is measured with respect to the frame head in the 3rd channel (channel 3) apart from close, the 0th channel of adjusting (channel 0) is delayed 1 clock cycle；To 3(cycle homoperiodic 3) in, each channel frame head spacing is normal, has been aligned At from macroscopically, since the 1st channel lags, other channels being caused all to lag the corresponding clock cycle, finally reaches alignment knot Fruit, for single channel lag multiple clock cycle the case where, then need to consume more to homoperiodic, but last can be reached surely To alignment as a result, which is not described herein again.

The alignment procedure of advancing offset can be illustrated in conjunction with Fig. 5 and Fig. 3, when align module detects the 1st channel (channel 1) is with respect to the frame head in the 0th channel (channel 0) apart from close, the 1st channel (channel 1) of adjusting delay 1 Clock cycle, obtain the alignment of Fig. 3 later as a result, for single channel in advance multiple clock cycle the case where, then need consume more It is more to homoperiodic, but last can reach alignment as a result, which is not described herein again surely.

Claims (1)

1. a kind of implementation method of the OTL agreement multi-channel data alignment based on FPGA, this method is using fpga chip as number According to the platform of alignment, which is characterized in that steps are as follows:

One, each channel data is inputted after respective fifo module is cached and is read, fifo is first input first The abbreviation of output is a kind of data buffer of first in first out, can be realized and be sequentially written in and sequentially read, used Fifo interface include: Data Input Interface din, data output interface dout, write-in enable signal wr, read enable signal rd, Clock clock is driven, when it is high level that enable signal wr, which is written, the data of din interface, into fifo, work as reading by clock buffer When to take enable signal rd be high level, the data in fifo are write by clock output if the data in each channel are effective from dout interface Entering enable signal wr is often high level, and during not completing alignment, reading enable signal rd, which has, drags down a clock week The case where phase, occurs, and after completing alignment, reading enable signal rd is often high level, and the data of each fifo output are at this time The channel data of alignment；

Two, each channel data of fifo output respective head marker module is inputted to carry out finding frame head operation, output Head_flag signal, head marker module carry out frame head search to the data of input, and head_flag signal is often low electricity Flat, when present clock period finds frame head, next clock cycle head_flag signal is drawn high, and is dragged down and is kept again later；

Three, align module receives head_flag signal and is handled, and output rd signal is read out control to each fifo module System, align module are to realize the main module of channel data alignment, and align module passes through control rd Signal Regulation fifo mould The output of block, and then adjust the delay time of the fifo each channel data exported and relative position；

Four, align module is judged by the head_flag signal inputted, exports alignment identification signal align_ok, signal It draws high expression alignment to complete, drags down expression and do not complete alignment.