CN105681018A - Data sending and receiving method, data sending and receiving device and PCS sending and receiving equipment - Google Patents
Data sending and receiving method, data sending and receiving device and PCS sending and receiving equipment Download PDFInfo
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- CN105681018A CN105681018A CN201610025712.8A CN201610025712A CN105681018A CN 105681018 A CN105681018 A CN 105681018A CN 201610025712 A CN201610025712 A CN 201610025712A CN 105681018 A CN105681018 A CN 105681018A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0041—Delay of data signal
Abstract
The invention discloses a data sending and receiving method, a data sending and receiving device and PCS sending and receiving equipment. The data sending method comprises the following steps of: judging whether a preset condition is satisfied or not; bypassing a module possibly causing uncertain delay in a data sending path if the preset condition is satisfied; and sending data in the data sending path, and fixing the delay of the sent data in a preset manner. The data receiving method comprises the following steps of: judging whether the preset condition is satisfied or not; bypassing the module possibly causing uncertain delay in a data receiving path if the preset condition is satisfied; and receiving data in the data receiving path, and fixing the delay of the received data in a preset manner. By means of the technical scheme, the problem that specific application environment requirements cannot be supported due to the fact that the fixed physical layer processing delay cannot be ensured in the existing scheme can be solved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of data sending, receiving method and device and PCS transmitting and receiving device.
Background technology
In high speed serial receive-transmit system, physical code sublayer (physicalcodingsub-layer, PCS) transmitting-receiving of data flow is completed, along with the development of the communication technology, the carrying ability of data service is more and more stronger, transmission bandwidth is more and more higher, in order to adapt to the transmission ability of high bandwidth, transfer also has corresponding change, for Ethernet data service, according to OSI (OpenSystemInterconnect, open system interconnection) the medium extraneous data interface of data link layer and physical layer in OSI seven layer model that defines of/IEC (International Electrotechnical Commission), 10M/100M Ethernet interface is MII (MediumIndependenceInterface, medium independent interfaces), 1G Ethernet interface is GMII (GigabitMediumIndependenceInterface, 1G medium independent interfaces), 10GE Ethernet interface is XGMII (10GigabitMediumIndependenceInterface, 10G medium independent interfaces). meanwhile, due to the increase of data service bandwidth, traditional Technique of Parallel evolves to the serial technology with clock recovery gradually. different communication protocol have can not function requirement, the system for transceiver designs, it is necessary to ensure enough flexibly to support various agreement.
Concerning a PCS transceiver supporting various protocols flexibly, the requirement that PCS is processed by different agreement is inconsistent, the agreements such as such as XAUI/PCIE only need to complete the encoding and decoding of data, passage synchronously goes the functions such as skew, but for common public radio interface (CommonPublicRadioInterface, CPRI) agreement etc., for point-to-point direct-connected patten's design, except completing corresponding codec functions, also require that physical layer ensures strict timing relationship.
Prior art mainly pays close attention to the configurable pcs system how realizing a multichannel, it is achieved that the general function of PCS, but for requiring the specific agreement of strict timing, and general configurable general system cannot processing delay that not only practical function but also ensure is fixed.
Summary of the invention
The present invention provides a kind of data sending, receiving method and device and PCS transmitting and receiving device, solves the physical layer process time delay that existing scheme cannot ensure to fix, to support the problem that specific application environment needs.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of data transmission method for uplink, comprising:
Judge whether to meet pre-conditioned;
If meeting pre-conditioned, then data are sent the module bypass that may cause uncertain time delay in path;
Send in path in data and send data, and adopt the fixing time delay being sent data of predetermined manner.
In certain embodiments, judge whether described in meet pre-conditioned comprising:
Judge whether to adopt the data preset to send agreement; If then meeting pre-conditioned.
In certain embodiments, described transmission in path in data sends data, and adopts the fixing time delay being sent data of predetermined manner to comprise:
The collection clock phase place of transmission clock phase place and described data to be sent that higher level's module sends data to be sent is adjusted to consistent;
Adopt described collection clock from described higher level's module to gather described data to be sent;
Send after the data collected are carried out presets process.
In certain embodiments, the data collected are carried out default process to comprise:
The data collected are carried out bit wide adjustment, coding and/or bit displacement.
A kind of data receive method, comprising:
Judge whether to meet pre-conditioned;
If meeting pre-conditioned, then data receiving path will may cause the module bypass of uncertain time delay;
Data receiving path receives data, and adopts the time delay of the fixing received data of predetermined manner.
In certain embodiments, judge whether described in meet pre-conditioned comprising:
Judge whether to adopt the data preset to receive agreement; If then meeting pre-conditioned.
In certain embodiments, described in data receiving path, receive data, and the time delay adopting the fixing received data of predetermined manner comprises:
It is sent to subordinate's module, and the collection clock phase place that described subordinate module acquires receives data is adjusted to consistent with the transmission clock phase place receiving data to receiving after data carry out presetting process.
In certain embodiments, reception data are carried out default process to comprise: reception data carry out byte-aligned, decoding and/or bit wide adjustment.
A kind of data dispensing device, comprising:
First judges module, pre-conditioned for judging whether to meet;
Data, when judging the judged result of module as meeting pre-conditioned for first, are sent the module bypass that may cause uncertain time delay in path by the first control module;
First transmission module, sends data for sending in path in data;
First processing module, fixes the time delay that the first transmission module is sent data for adopting predetermined manner.
In certain embodiments, the first processing module is adjusted to consistent specifically for higher level's module sends the transmission clock phase place of data to be sent with the collection clock phase place of data to be sent described in the first transmission module acquires;
First transmission module, specifically for adopting described collection clock from described higher level's module to gather described data to be sent, sends after the data collected carry out preset process.
In certain embodiments, this data dispensing device also comprises described higher level's module, for adopting described transmission clock to send described data to be sent to the first transmission module.
A kind of data receive device, comprising:
2nd judges module, pre-conditioned for judging whether to meet;
2nd control module, when judging the judged result of module as meeting pre-conditioned for the 2nd, will may cause the module bypass of uncertain time delay in data receiving path;
2nd receiver module, for receiving data in data receiving path;
2nd processing module, for adopting predetermined manner to fix the time delay of the 2nd receiver module received data.
In certain embodiments, the 2nd receiver module is specifically for receiving data, and is sent to subordinate's module to receiving after data carry out presetting process;
2nd processing module is adjusted to consistent specifically for described subordinate module acquires receives the collection clock phase place of data with the transmission clock phase place of the 2nd receiver module transmitting and receiving data.
In certain embodiments, these data receive device and also comprise described subordinate module, for adopting described collection clock acquisition to receive data.
A kind of PCS sends equipment, comprising:
First judging unit, pre-conditioned for judging whether to meet;
First control unit, during for the judged result of the first judging unit for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in this equipment;
First transmission unit, for adopting collection clock to gather data to be sent from superordinate elements, sends after the data collected carry out preset process;
First process unit, the collection clock phase place gathering described data to be sent with the first transmission unit for superordinate elements sends the transmission clock phase place of data to be sent is adjusted to consistent.
A kind of PCS receives equipment, comprising:
2nd judging unit, pre-conditioned for judging whether to meet;
2nd control unit, during for the judged result of the 2nd judging unit for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in data receiving path;
2nd reception unit, for receiving data, and is sent to bottom-ranked unit to receiving after data carry out presetting process;
2nd process unit, the transmission clock phase place for collection clock phase place with the 2nd reception unit transmitting and receiving data that described bottom-ranked unit collection receives data is adjusted to consistent.
The present invention is directed to the transmitting-receiving device supporting various protocols, for the agreement specifically requiring strict timing, ensureing the basis that data are correctly received and dispatched can provide the physical layer process time delay fixed, to support specific application environment needs.
Especially to the transmitting-receiving device of the support various protocols realized at PCS layer, PCS receives and dispatches equipment to be needed process physics M AC device (PhyMAC) data brought or will pass to PhyMAC after the data processing received again. equipment is sent for PCS, existing PCS sends data path: PCS sends equipment and the processing clock of oneself is passed to phyMAC, this clock can through oversampling clock tree after entering phyMAC, phyMAC sends data to PCS with this clock again and sends equipment, owing to the path of clock process is different, PCS sends equipment and is gathering clock that the data brought of phyMAC use and data are not alignment, it is thus desirable to the phase bit compensation circuit of the first order in PCS transmission equipment carry out phase place compensate correct property to ensure data, but that this phase bit compensation circuit is used is asynchronous FIFO stack FIFO, asynchronous FIFO may cause data time delay after it uncertain owing to there is the problems such as the enable control of read-write, in order to solve the above problems, the present invention sends in the data transmission procedure of equipment at PCS, the module bypass of uncertain time delay may be caused, and the clock phase place adjusting PhyMAC transmission data is consistent from the collection clock phase place of PhyMAC image data with PCS transmission equipment, sending equipment at guarantee PCS like this can accurately collect on the basis of data to be sent, the transmission time delay achieving PCS is fixed, PCS sends after the data collected are carried out presetting process by equipment again and sends, default process comprises bit wide adjustment, coding and/or bit displacement, preferably, bit displacement be placed on link stable after, time delay above is compensated in the way of bit slip. it is also similar that PCS receives equipment, the module bypass of uncertain time delay may be caused, by byte-aligned module, that recover and row data is undertaken that border is synchronous, pass to subordinate PhyMAC after decoding, the clock that byte-aligned and decoder module use is passed to PhyMAC, the transmission clock phase place that subordinate PhyMAC gathers collection clock phase place and the PCS reception equipment transmitting and receiving data receiving data is adjusted to consistent, ensure that the collection PCS that it can be correct receives on the basis of the data that equipment passes through like this, it is achieved that the time delay receiving data is fixed. owing to the module of uncertain time delay may be caused to be bypassed, therefore the process time delay of whole path is fixed up.
Accompanying drawing explanation
The flow chart of the data transmission method for uplink that Fig. 1 provides for one embodiment of the invention;
The flow chart of the data receive method that Fig. 2 provides for one embodiment of the invention;
The schematic diagram of the data dispensing device that Fig. 3 provides for one embodiment of the invention;
The schematic diagram of the data reception device that Fig. 4 provides for one embodiment of the invention;
The schematic diagram of the PCS transmission equipment that Fig. 5 provides for one embodiment of the invention;
The schematic diagram of the PCS reception equipment that Fig. 6 provides for one embodiment of the invention.
Specific embodiment party formula
In the present invention, data send in path, data receiving path and the module of uncertain time delay may be caused including, but not limited to asynchronous FIFO stack fifo module. Utilize other circuit to optimize interface sequence after bypassing these modules, strict communication agreement is required for for timing, accomplish fixing time delay, and ensure that the correct property of image data, after interface sequence has adjusted, path is stablized, and only determines to process the logic function module of time delay, therefore the process time delay of whole path is fixed up in transmitting-receiving path. Not strict communication agreement is required, it is possible to keep using the module that may cause uncertain time delay for timing. Data in the present invention send path, data receiving path sends path, PCS receiving path including, but not limited to PCS.
Below by specific embodiment, the design of the present invention is further described.
As shown in Figure 1, it is the flow chart of the data transmission method for uplink that one embodiment of the invention provides, mainly comprises the following steps:
S101, judge whether to meet pre-conditioned; If meeting pre-conditioned, then entering step S102, if not meeting pre-conditioned, then entering step S104.
Preferably, judge whether to adopt the data preset to send agreement; If then meeting pre-conditioned, if not, then do not meet pre-conditioned.
These data preset send protocol include and timing are required strict communication agreement, including, but not limited to: CPRI agreement.
By this step, to different communication agreements, there is different processing schemes, timing is required strict communication agreement, adopts step S102 to S103, to the module bypass that may cause uncertain time delay in path, and adopt the fixing time delay being sent data of predetermined manner, carry out data transmission. Timing is required not strict communication agreement, adopts step S104, retain the normal use of the module that may cause uncertain time delay in path, carry out data transmission in a conventional manner.
S102, then data are sent the module bypass that may cause uncertain time delay in path, enter step S103.
The module being specifically bypassed sends path depending on data, and it is different that different data send the module that may cause uncertain time delay in path, and the module being therefore bypassed is also just different. Including, but not limited to asynchronous FIFO stack fifo module.
S103, send in path in data and send data, and adopt the fixing time delay being sent data of predetermined manner.
Step S102 and S103 can carry out parallel. Concrete, the place of uncertain time delay may be caused in path to carry out predetermined manner process, with fixing time delay. The place such as gathering data to be sent at path may cause uncertain time delay, then should be positioned at the phase compensation block bypass going time delay function that this place runs, and adopt predetermined manner to be fixed time delay, such as:
The collection clock phase place of the transmission clock phase place data to be sent with this that higher level's module sends data to be sent is adjusted to consistent;
Adopt this collection clock from this higher level's module to gather this data to be sent;
Send after the data collected are carried out presets process (presetting process to comprise: the data collected carry out bit wide adjustment, coding and/or bit displacement etc.).
The collection clock phase place of the transmission clock phase place data to be sent with this sending data to be sent due to higher level's module is adjusted to consistent, therefore ensure that data send path and can correctly collect data to be sent, and achieves the fixing time delay sending data.
S104, carry out data transmission in a conventional manner. Data retention sends the normal use of the module that may cause uncertain time delay in path.
The present embodiment, it is achieved that data are sent the fixing time delay of path.
As shown in Figure 2, it is the flow chart of the data receive method that one embodiment of the invention provides, mainly comprises the following steps:
S201, judge whether to meet pre-conditioned; If meeting pre-conditioned, then entering step S202, if not meeting pre-conditioned, then entering step S204.
Preferably, judge whether to adopt the data preset to receive agreement; If then meeting pre-conditioned, if not, then do not meet pre-conditioned.
These data preset receive protocol include and timing are required strict communication agreement, including, but not limited to: CPRI agreement.
By this step, to different communication agreements, there is different processing schemes, timing is required strict communication agreement, adopts step S202 to S203, to the module bypass that may cause uncertain time delay in path, and adopt the time delay of the fixing received data of predetermined manner, carry out data reception. Timing is required not strict communication agreement, adopts step S404, retain the normal use of the module that may cause uncertain time delay in path, carry out data reception in a conventional manner.
S202, by data receiving path may cause the module bypass of uncertain time delay, enter step S203.
The module being specifically bypassed, depending on data receiving path, may cause the module of uncertain time delay different in different data receiving paths, the module being therefore bypassed is also just different. Including, but not limited to asynchronous FIFO stack fifo module.
S203, in data receiving path, receive data, and adopt the time delay of the fixing received data of predetermined manner.
Step S202 and S203 can carry out parallel. Concrete, the place of uncertain time delay may be caused in path to carry out predetermined manner process, with fixing time delay. Such as at path, the place that reception data are sent to subordinate's module may be caused uncertain time delay, then should be positioned at the phase compensation block bypass going time delay function that this place runs, and adopt predetermined manner to be fixed time delay, such as:
It is sent to subordinate's module to receiving after data carry out presetting process, and the collection clock phase place that this subordinate's module acquires receives data is adjusted to consistent with the transmission clock phase place receiving data, like this this subordinate's module can accurate acquisition to reception data, and achieve receive data time delay fix.
S204, carry out data reception in a conventional manner. Data retention receiving path may cause the normal use of the module of uncertain time delay.
The present embodiment, it is achieved that to the fixing time delay of data receiving path.
The schematic diagram of the data dispensing device that Fig. 3 provides for one embodiment of the invention, data dispensing device comprises:
First judges module 31, pre-conditioned for judging whether to meet;
Data, when judging the judged result of module 31 as meeting pre-conditioned for first, are sent the module bypass that may cause uncertain time delay in path by the first control module 32; In other words, for module bypass enable, that rest energy may cause uncertain time delay, the first processing module 34;
First transmission module 33, sends data for sending in path in data;
First processing module 34, fixes the time delay that the first transmission module 31 is sent data for adopting predetermined manner.
In certain embodiments, the collection clock phase place that the first processing module 34 gathers these data to be sent specifically for higher level's module sends the transmission clock phase place of data to be sent with the first transmission module 33 is adjusted to consistent; First transmission module 33, specifically for adopting this collection clock from this higher level's module to gather this data to be sent, sends after the data collected carry out preset process.
In certain embodiments, this data dispensing device also comprises the module that may cause uncertain time delay, for under the control of the first control module 32, it is bypassed or normally runs, namely first when judging the judged result of module 31 as meeting pre-conditioned, being bypassed, first when judging the judged result of module 31 as not meeting pre-conditioned, normally runs.
In certain embodiments, this data dispensing device also comprises this higher level's module, for adopting this transmission clock to send these data to be sent to the first transmission module 33.
The schematic diagram of the data reception device that Fig. 4 provides for one embodiment of the invention, data receive device and comprise:
2nd judges module 41, pre-conditioned for judging whether to meet;
2nd control module 42, when judging the judged result of module 41 as meeting pre-conditioned for the 2nd, will may cause the module bypass of uncertain time delay in data receiving path;
2nd receiver module 43, for receiving data in data receiving path;
2nd processing module 44, for adopting predetermined manner to fix the time delay of the 2nd receiver module 43 received data.
In certain embodiments, the 2nd receiver module 43 is specifically for receiving data, and is sent to subordinate's module to receiving after data carry out presetting process; 2nd processing module 44 is specifically for being adjusted to consistent by the collection clock phase place that this subordinate's module acquires receives data with the transmission clock phase place of the 2nd receiver module 43 transmitting and receiving data.
In certain embodiments, these data receive device and also comprise the module that may cause uncertain time delay, for under the control of the 2nd control module 42, it is bypassed or normally runs, namely the 2nd when judging the judged result of module 41 as meeting pre-conditioned, being bypassed, the 2nd when judging the judged result of module 41 as not meeting pre-conditioned, normally runs.
In certain embodiments, these data receive device and also comprise this subordinate's module, for adopting this collection clock acquisition to receive data.
The schematic diagram of the PCS transmission equipment that Fig. 5 provides for one embodiment of the invention, as shown in Figure 5, PCS sends equipment and comprises:
First judging unit 51, pre-conditioned for judging whether to meet;
First control unit 52, during for the judged result of the first judging unit 51 for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in this equipment;
First transmission unit 53, for adopting collection clock to gather data to be sent from superordinate elements, sends after the data collected carry out preset process;
First process unit 54, the collection clock phase place gathering described data to be sent with the first transmission unit for superordinate elements sends the transmission clock phase place of data to be sent is adjusted to consistent.
In certain embodiments, this PCS sends equipment and also comprises the module 55 that may cause uncertain time delay, such as, as the asynchronous FIFO stack fifo module that phase place compensates, when the judged result of the first judging unit 51 is for meeting pre-conditioned, under the control of the first control unit 52, it is bypassed, when the judged result of the first judging unit 51 is not for meeting pre-conditioned, normally run.
Superordinate elements is such as: physics M AC device (PhyMAC).
The schematic diagram of the PCS reception equipment that Fig. 6 provides for one embodiment of the invention, as shown in Figure 6, PCS receives equipment and comprises:
2nd judging unit 61, pre-conditioned for judging whether to meet;
2nd control unit 62, during for the judged result of the 2nd judging unit 61 for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in data receiving path;
2nd reception unit 63, for receiving data, and is sent to bottom-ranked unit to receiving after data carry out presetting process;
2nd process unit 64, the transmission clock phase place for collection clock phase place with the 2nd reception unit 63 transmitting and receiving data that described bottom-ranked unit collection receives data is adjusted to consistent.
In certain embodiments, this PCS receives equipment and also comprises the module that may cause uncertain time delay, such as, as the asynchronous FIFO stack fifo module that phase place compensates, when the judged result of the 2nd judging unit 61 is for meeting pre-conditioned, under the control of the 2nd control unit 62, it is bypassed, when the judged result of the 2nd judging unit 61 is not for meeting pre-conditioned, normally run.
Bottom-ranked unit is such as: physics M AC device (PhyMAC).
Sending equipment for PCS below, present inventive concept is explained explanation further, the data to be sent that PCS transmission equipment reception is brought from upper one-level PhyMAC send, and process comprises:
PCS sends equipment and judges whether to need bypass may cause the module of uncertain time delay according to the communication agreement of application;
When adopting the agreement transmission data that timing requirement is not strict, it is judged as not needing, then retain the normal use that may cause the process uncertain phase compensation block of time delay, data send and adopt usual manner to carry out, such as: PCS sends equipment and the processing clock of oneself is passed to upper one-level phyMAC, this clock can through oversampling clock tree after entering one-level phyMAC, upper one-level phyMAC sends data to PCS with this clock again and sends equipment, owing to the path of clock process is different, the collection clock that the PCS transmission equipment data that one-level phyMAC brings on gathering use and data are not alignment, therefore PCS sends after equipment collects data to be sent needs the phase compensation block in equipment to carry out the compensation of phase place, the data that phase compensation block exports adjust through bit wide according to this, the process such as coding send again. but, what use due to phase compensation block is asynchronous FIFO, and asynchronous FIFO exists the problems such as the enable control of read-write and data time delay after it may be caused uncertain.
When adopting when regularly requiring that strict agreement sends data, such as require the CPRI agreement of the strict timing of physical layer, then it is judged as needs, then bypass may cause the process uncertain phase compensation block of time delay, selected phase alignment adjusting module (as the first process unit), the main function of phase alignment adjusting module is when phase compensation block is bypassed, and optimizes the interface sequence receiving data, owing to the problems such as the asynchronous FIFO existence enable control of read-write that phase compensation block is used may cause data time delay after it uncertain, therefore this process is by its bypass, simultaneously in order to solve the problem of time delay, the clock that employing phase alignment adjusting module adjusts phyMAC transmission data is consistent with the clock phase place that PCS transmission equipment gathers data to be sent, Deng phase alignment adjusting module complete adjustment after, passage is stablized, then computing postpones, the adjustment process of phase alignment adjusting module comprises: PCS sends equipment and the processing clock of oneself is passed to phase alignment adjusting module, the time delay unit (configured in advance well adjust step-length and adjust enable) of this input clock in phase alignment adjusting module, clock after output time delay, after this time delay, clock is as the work clock of upper one-level phyMAC, phase alignment adjusting module is sent back to again after clock tree in upper one-level phyMAC, this clock is also the clock CLK that upper one-level phyMAC is used for sending data to PCS simultaneously, again clock CLK is adjusted: periodically control signal saltus step from low to high, notice that saltus step frequency is lower than CLK, at the rising edge sampling clock to be adjusted of CLK, regulate the adjustment step-length number in time delay unit from low to high, until observing adjustment state from low saltus step for high, now on this one-level phyMAC send data CLK and PCS to input clock phase alignment, adjustment terminates, after phase alignment adjusting module adjusts, PCS sends equipment can directly gather, with the clock of oneself, the data that upper one-level phyMAC sends over, then carries out bit wide, coding, and the data after coding can be selected whether enter bit displacement as required and send. and the modules such as above bit wide, coding, bit shifting processing are all Digital Logic process unit, process time delay is determined along with scheme and is fixed, wherein the main function of bit shifting processing is slided on the border sending also row data, this is corresponding with the function of PCS reception equipment first order byte-aligned module, due to the byte-aligned function of data in PCS reception equipment be need from high speed serial line interface by data being carried out the border that displacement detection goes out data, when after system stability, the number of displacement can be sent equipment at PCS and be retracted by transmission data bit shifts module, can fix the process time delay of whole receive-transmit system so further. further, if PCS receives equipment does not carry out byte-aligned, then PCS sends equipment and can also bypass bit shift module.
The scheme being exactly this PCS and sending the fixing processing delay of equipment described above, bypass the phase compensation block using asynchronous FIFO, open phase alignment adjusting module, utilize phase alignment adjusting module adjustment interface clock phase place relation, gather the data to be sent that upper one-level phyMAC brings on this basis again, data to be sent are carried out bit wide adjustment, coding etc., after treating that the phase alignment of PCS receive-transmit system adjusts, the byte-aligned displacement amount adjustment receiving equipment according to PCS sends data bit shifts module displacement value. For the agreement not needing fixing processing delay, it is possible to bypass phase alignment adjusting module, selected phase compensating module and corresponding function module realize.
Receiving equipment for PCS below, present inventive concept is explained explanation further, PCS receives equipment receiving data, and decoded data are sent back to next stage PhyMAC:
PCS receives the also row data that equipment receives high speed serial circuit and recovers, and judges whether to need bypass may cause the module of uncertain time delay according to the communication agreement of application;
When adopting the agreement transmission data that timing requirement is not strict, being judged as not needing, then retain the normal use that may cause the process uncertain phase compensation block of time delay, data receive employing usual manner and carry out, such as:
PCS receives the also row data of equipment reception first through byte-aligned process, finds the boundary of packet, and by the specific border character of insertion in detection packet, the bit position moving data is until this character becomes the initial of data flow, in order to determine the delay of byte-aligned resume module, can selecting data to be shifted by the interface module of transformation from serial to parallel or this module, a mobile bit, until byte-aligned module detects correct specific border character, namely stops data shifts every time, data through byte-aligned enter link decoder module subsequently, and decoded data give data width adjustment module again, adjust according to the needs of data bit width, data after data bit width adjusts enter phase compensation block, are sent to next stage PhyMAC after phase place compensates, the Principle of Process of phase compensation block is: PCS receives equipment and the processing clock of oneself is passed to next stage phyMAC, this clock can through oversampling clock tree after entering next stage phyMAC, the data that next stage phyMAC sends with this clock acquisition PCS reception equipment again, owing to the path of clock process is different, the collection clock that next stage phyMAC uses and data are not alignment, therefore PCS receive need before equipment sending data by these data first the phase compensation block in equipment to carry out the compensation of phase place, owing to the problems such as the asynchronous FIFO existence enable control of read-write that phase compensation block is used may cause data time delay after it uncertain.
When adopting when regularly requiring that strict agreement sends data, such as require the CPRI agreement of the strict timing of physical layer, then be judged as needs, then bypass may cause the process uncertain phase compensation block of time delay, selected phase alignment adjusting module (as the 2nd process unit), it receives data procedures: PCS receives equipment reception and row data first processes through byte-aligned, find the boundary of packet, by the specific border character of insertion in detection packet, the bit position of mobile data is until this character becomes the initial of data flow, in order to determine the delay of byte-aligned resume module, can selecting data to be shifted by the interface module of transformation from serial to parallel or this module, a mobile bit, until byte-aligned module detects correct specific border character, namely stops data shifts every time, data through byte-aligned enter link decoder module subsequently, and decoded data give data width adjustment module again, adjust according to the needs of data bit width, data after data bit width adjusts are without phase compensation block, in order to solve the problem of time delay, utilize phase alignment adjusting module to improve sequential, the work principle of phase alignment adjusting module is: the phase alignment adjusting module of phase alignment adjusting module and PCS transmission equipment that PCS receives equipment adopts identical scheme, PCS receives equipment and the processing clock of oneself is passed to phase alignment adjusting module, clock after output time delay after the time delay unit (configured in advance adjusts well step-length and adjusts enable) of this input clock in phase alignment adjusting module, after this time delay, clock is as the work clock of next stage phyMAC, after oversampling clock tree, send back to PCS again receive equipment, this clock can be used for gathering PCS and receives the reception data that send out of equipment simultaneously. when the mark signal of phase alignment adjusting module is set to height, illustrate the clock sent back and PCS receive equipment to the phase alignment of input clock, then next stage phyMAC utilize this clock can correctly gather PCS receive device processes after reception data.
The scheme being exactly this PCS and receiving the fixing processing delay of equipment described above, bypass the phase compensation block using asynchronous FIFO, open phase alignment adjusting module, byte-aligned module adjustment data, decoding data, bit wide adjustment after alignment, utilize phase alignment adjusting module adjustment interface clock phase place relation, give next stage phyMAC by data after decoding on this basis. After the mark signal of phase alignment adjusting module is set to a high position, illustrating that it settles out, the now process time delay of whole passage is all fixed up. For the agreement not needing fixing processing delay, it is possible to bypass phase alignment adjusting module, selected phase compensating module and corresponding function module realize.
Above content is in conjunction with concrete enforcement mode further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations. For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, it is also possible to make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (16)
1. a data transmission method for uplink, it is characterised in that, comprising:
Judge whether to meet pre-conditioned;
If meeting pre-conditioned, then data are sent the module bypass that may cause uncertain time delay in path;
Send in path in data and send data, and adopt the fixing time delay being sent data of predetermined manner.
2. data transmission method for uplink as claimed in claim 1, it is characterised in that, described in judge whether to meet pre-conditioned comprising:
Judge whether to adopt the data preset to send agreement; If then meeting pre-conditioned.
3. data transmission method for uplink as claimed in claim 1, it is characterised in that, described transmission in path in data sends data, and adopts the fixing time delay being sent data of predetermined manner to comprise:
The collection clock phase place of transmission clock phase place and described data to be sent that higher level's module sends data to be sent is adjusted to consistent;
Adopt described collection clock from described higher level's module to gather described data to be sent;
Send after the data collected are carried out presets process.
4. data transmission method for uplink as claimed in claim 3, it is characterised in that, the data collected are carried out default process and comprises:
The data collected are carried out bit wide adjustment, coding and/or bit displacement.
5. a data receive method, it is characterised in that, comprising:
Judge whether to meet pre-conditioned;
If meeting pre-conditioned, then data receiving path will may cause the module bypass of uncertain time delay;
Data receiving path receives data, and adopts the time delay of the fixing received data of predetermined manner.
6. data receive method as claimed in claim 5, it is characterised in that, described in judge whether to meet pre-conditioned comprising:
Judge whether to adopt the data preset to receive agreement; If then meeting pre-conditioned.
7. data receive method as claimed in claim 5, it is characterised in that, described in data receiving path, receive data, and the time delay adopting the fixing received data of predetermined manner comprises:
It is sent to subordinate's module, and the collection clock phase place that described subordinate module acquires receives data is adjusted to consistent with the transmission clock phase place receiving data to receiving after data carry out presetting process.
8. data receive method as claimed in claim 7, it is characterised in that, reception data are carried out default process and comprises:
Reception data are carried out byte-aligned, decoding and/or bit wide adjustment.
9. a data dispensing device, it is characterised in that, comprising:
First judges module, pre-conditioned for judging whether to meet;
Data, when judging the judged result of module as meeting pre-conditioned for first, are sent the module bypass that may cause uncertain time delay in path by the first control module;
First transmission module, sends data for sending in path in data;
First processing module, fixes the time delay that the first transmission module is sent data for adopting predetermined manner.
10. data dispensing device as claimed in claim 9, it is characterized in that, the first processing module is adjusted to consistent specifically for higher level's module sends the transmission clock phase place of data to be sent with the collection clock phase place of data to be sent described in the first transmission module acquires;
First transmission module, specifically for adopting described collection clock from described higher level's module to gather described data to be sent, sends after the data collected carry out preset process.
11. data dispensing device as claimed in claim 10, it is characterised in that, also comprise described higher level's module, for adopting described transmission clock to send described data to be sent to the first transmission module.
12. 1 kinds of data receive device, it is characterised in that, comprising:
2nd judges module, pre-conditioned for judging whether to meet;
2nd control module, when judging the judged result of module as meeting pre-conditioned for the 2nd, will may cause the module bypass of uncertain time delay in data receiving path;
2nd receiver module, for receiving data in data receiving path;
2nd processing module, for adopting predetermined manner to fix the time delay of the 2nd receiver module received data.
13. data as claimed in claim 12 receive device, it is characterised in that, the 2nd receiver module is specifically for receiving data, and is sent to subordinate's module to receiving after data carry out presetting process;
2nd processing module is adjusted to consistent specifically for described subordinate module acquires receives the collection clock phase place of data with the transmission clock phase place of the 2nd receiver module transmitting and receiving data.
14. data as claimed in claim 13 receive device, it is characterised in that, also comprise described subordinate module, for adopting described collection clock acquisition to receive data.
15. 1 kinds of PCS send equipment, it is characterised in that, comprising:
First judging unit, pre-conditioned for judging whether to meet;
First control unit, during for the judged result of the first judging unit for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in this equipment;
First transmission unit, for adopting collection clock to gather data to be sent from superordinate elements, sends after the data collected carry out preset process;
First process unit, the collection clock phase place gathering described data to be sent with the first transmission unit for superordinate elements sends the transmission clock phase place of data to be sent is adjusted to consistent.
16. 1 kinds of PCS receive equipment, it is characterised in that, comprising:
2nd judging unit, pre-conditioned for judging whether to meet;
2nd control unit, during for the judged result of the 2nd judging unit for meeting pre-conditioned, will may cause the module bypass of uncertain time delay in data receiving path;
2nd reception unit, for receiving data, and is sent to bottom-ranked unit to receiving after data carry out presetting process;
2nd process unit, the transmission clock phase place for collection clock phase place with the 2nd reception unit transmitting and receiving data that described bottom-ranked unit collection receives data is adjusted to consistent.
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| CN201610025712.8A CN105681018B (en) | 2016-01-14 | 2016-01-14 | Data sending, receiving method and device and PCS transmitting and receiving device |
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| CN201610025712.8A CN105681018B (en) | 2016-01-14 | 2016-01-14 | Data sending, receiving method and device and PCS transmitting and receiving device |
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| CN105681018A true CN105681018A (en) | 2016-06-15 |
| CN105681018B CN105681018B (en) | 2019-01-15 |
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