CN111586324B - Serial CMOS image data training method adaptive to real-time line period change - Google Patents

Serial CMOS image data training method adaptive to real-time line period change Download PDF

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CN111586324B
CN111586324B CN202010445752.4A CN202010445752A CN111586324B CN 111586324 B CN111586324 B CN 111586324B CN 202010445752 A CN202010445752 A CN 202010445752A CN 111586324 B CN111586324 B CN 111586324B
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control signal
correction
data
train
bitslip
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CN111586324A (en
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余达
孔德柱
刘金国
梅贵
万志
傅瑶
张琨
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A serial CMOS image data training method adapting to real-time line period change relates to a CMOS image data training method, solves the problem that the existing CMOS image data training method cannot meet the application requirement of continuous line period adjustment of linear array TDI detector push-broom imaging, and comprises a CMOS data training system which mainly comprises a CMOS image sensor and a data processor. The data processor internally comprises iodelay1, iserdes1, a data asynchronous FIFO, a control asynchronous FIFO, a georbox, ram based shift and a controller. The controller is used as the core of the CMOS data training system and controls all parts to work in coordination. Under the control of the controller, the output serial image data of the CMOS image sensor is finally converted into parallel image data with a bit width p through iodelay1, iserdes1, data asynchronous FIFO, gearbox and ram based shift. The invention provides an improved training method based on a controllable shift register, which ensures the correctness of single-pulse training words and simultaneously ensures the continuous adjustability of line periods.

Description

Serial CMOS image data training method adaptive to real-time line period change
Technical Field
The invention relates to a training method of CMOS image data, in particular to a training method of serial CMOS image data adaptive to real-time line period change.
Background
Nowadays, a high-resolution (not less than 10k) high-line-frequency (not less than 20kHz) TDICMOS image sensor generally adopts multiple (not less than 20 channels) high-speed serial channels to transmit image data, each data transmission channel has no definite phase relation during each power-on, and the relative position of serial data intercepted each time in the serial-parallel conversion process may be different along with the change of ambient temperature, which brings great difficulty to the serial-parallel conversion of data. Directly adopting ISERDES1 modules integrated inside, such as virtex 6 and the like, can not meet the application requirement of high bit width, and needs further serial-parallel conversion; the correct training word may be obtained by combining the data positions where errors occur during the word correction process, and the correct training word may not be obtained during the channel training process. For example, the correct training word is AB, parallel data a and B obtained after ISERDES1, and a possible data combination mode in the word correction process after further serial-parallel conversion is ababababababab … or bababababababa, where both combinations include the correct training word AB; in the channel training process, corresponding to a single training pulse, the parallel data obtained in the former combination mode are … 00,00, AB,00,00 …, and also contain correct training characters AB; and the parallel data obtained by the latter combination method are … 0,00,0B, A0,00,0 …, and the channel training will always fail without containing the correct training word AB. The granted patent "a training method for CMOS image data based on alternating pulses" can solve the above problems, but can only adapt to the application occasions where the line period is even times of the pixel clock, such as the reading of an area array detector, but is not suitable for the application requirements of continuous line period adjustment of push-scan imaging of a linear array TDI detector.
Disclosure of Invention
The invention provides a serial CMOS image data training method suitable for real-time change of line periods, aiming at solving the problem that the conventional CMOS image data training method cannot meet the application requirement of continuous line period adjustment of push-scan imaging of a linear array TDI detector.
A serial CMOS image data training method adapting to real-time variation of line period, the data correction includes bit correction that the control signal train is a fixed high level, the control signal train is word correction of the fixed high level, the control signal train is channel correction of the single pulse width and data correction completion state;
after the bit correction of the control signal train for the fixed high level is finished, directly entering the word correction of the control signal train for the fixed high level; after the word correction is successful, directly entering the channel correction of which the control signal train is in a single pulse width from the word correction of which the control signal train is in a fixed high level;
when the first channel correction fails, entering the word correction with the control signal train being a fixed level from the channel correction with the control signal train being a single pulse width, negating the control signal bitslip _ swap, and clearing the correct and wrong times of the word correction; if the second channel correction fails, the channel correction with the single pulse width from the control signal train enters a data correction completion state;
the specific process of the word correction is as follows:
firstly, p/2-bit parallel data _ in output by iserdes1 is output to parallel data _ t1 through a controllable delayer, a control signal is bitslip _ swap, and when the bitslip _ swap is in a low level, no delay is output; when the bitslip _ swap is in a high level, the output is delayed, and the output parallel data _ t1 is delayed 1/2pixel clock cycles relative to the parallel data _ in, namely, the width is
Figure BDA0002505789430000021
Step two, converting the parallel data _ t1 with the bit width of p/2 into parallel data _ out _ bbuf with the bit width of p through a serial-parallel converter with the bit width of 1: 2; the parallel data _ out _ bbuf with the bit width p realizes the selective output of the p-bit parallel data _ out through a check device MUX, and the selection process is controlled by a control signal bitslip _ turn; circulating the value of bitslip _ turn from 1 to 2, and correspondingly taking different values, and selecting different bit combinations of the data _ out _ bbuf for outputting by the parallel data _ out; the method specifically comprises the following steps:
when the control signal bitslip _ turn is 1, selecting p-1-0 bits of the data _ out _ bbuf to output; when the control signal bitslip _ turn is 2, selecting p/2-1-0 bits and p-1-p/2 bits of the data _ out _ bbuf to output;
setting p times of control signals bitslip as a cycle period; every p/2 times the control signal bitslip pulse passes, the control signal bitslip _ turn is increased by 1.
The invention has the beneficial effects that: the invention provides an improved training method based on a controllable shift register, which ensures the correctness of single-pulse training words and simultaneously ensures the continuous adjustability of line periods. Has the following advantages:
1. the clock domain control is divided, so that the load of a local clock is reduced, and the system can work at higher frequency;
2. the inc pin of the iodelay1 is constantly enabled to be at high level, so that the number of control signals crossing a clock domain is reduced, and resources are saved;
3. the asynchronous FIFO is controlled to be effective only in the read-write operation in the data training stage, so that the energy consumption is saved;
4. the fixed high level is used in the word correction stage, and alternating pulses are not used, so that the application requirement of continuously variable line period length can be met;
5. by adding an optional shift register before parallel p/2 bit parallel data, controllable 1/2pixel clock period delay is realized, and training errors caused by different relative positions of serial data intercepted each time in the serial-parallel conversion process due to environment temperature change can be overcome.
Drawings
FIG. 1 is a diagram of a serial CMOS image data training system adapted to real-time variation of line period according to the present invention;
FIG. 2 is a data correction flow chart of a serial CMOS image data training method adapted to real-time variation of line period according to the present invention;
FIG. 3 is a schematic diagram of word correction and channel correction in a serial CMOS image data training method adapted to real-time variation of line period according to the present invention.
Detailed Description
In the first embodiment, the present embodiment is described with reference to fig. 1 to 3, and a serial CMOS image data training method adapted to real-time line period changes includes a CMOS data training system mainly including a CMOS image sensor and a data processor. The data processor internally comprises a programmable delay element (iodelay1), a special serial-parallel converter (iserdes1), a data asynchronous FIFO, a control asynchronous FIFO, a data bit width doubling conversion module (gearbox), a RAM-based shift register (RAM-based shift) and a controller. The controller is used as the core of the CMOS data training system and controls all parts to work in coordination. Under the control of the controller, the output serial image data of the CMOS image sensor is finally converted into parallel image data with a bit width p through iodelay1, iserdes1, data asynchronous FIFO, gearbox and ram based shift.
In this embodiment, the data correction flow mainly includes bit correction in which train is at a fixed high level, word correction in which train is at a fixed level, channel correction in which train is at a single pulse width, and a data correction completion state. After the bit correction of train for fixed high level is finished, directly entering the word correction of train for fixed level. After the word correction is successful, the word correction with the train as a fixed level is directly carried out to the channel correction with the train as a single pulse width. When the first channel correction fails, the channel correction with single pulse width from the train enters the word correction with fixed level from the train, the bitslip _ swap is inverted, and the correct and error times of the word correction are cleared; if the second channel correction fails, the channel correction with single pulse width from train enters a data correction complete state.
The present embodiment is described with reference to fig. 2 and fig. 3, and in the present embodiment, the bit correction process is: the input serial image data is first subjected to a phase-controllable delay through iodelay 1; the bit correction is controlled by control signals, i delay _ reset _ pulse and i delay _ ce _ pulse, generated by a controller, and is converted into a reset pin and a ce pin which are respectively sent to the i delay1 along with clock domain signals, i delay _ reset _ pulse _ io and i delay _ ce _ pulse _ io, through a control asynchronous FIFO for control; the controller generates a control signal train high and the controller generates a control signal vtz low.
The word correction process is as follows: 1 via iserdes 1: p/2 serial-parallel conversion p/2 bit parallel data, the data accompanying the clock domain is converted into the global clock domain through asynchronous data asynchronous FIFO, and then 1:2 conversion is carried out through the georbox to finally realize 1: p is converted in a serial-parallel mode; the word correction is controlled by control signals bitslip and bitslip _ pulse generated by a controller; the bitslip signal is directly sent to the georbox; the bitslip _ pulse is converted into the companion clock domain signal bitslip _ pulse _ io via the control asynchronous FIFO and finally fed into the bitslip pin of the iserdes 1. The controller generates a control signal train that is a fixed high level and vtz is a low level.
The specific steps of the word correction are as follows:
(a) the p/2-bit parallel data _ in output by the iserdes1 firstly passes through a controllable 1/2pixel _ delay delayer, a control signal is bitslip _ swap, and when the bitslip _ swap is at a low level, no delay is output; when the bitslip _ swap is at a low level, the output is not delayed, and the output parallel data _ t1 is delayed 1/2pixel clock cycles relative to the input parallel data _ in, namely, the width is 4fcplk_io。
(b) The parallel data _ t1 with the bit width of p/2 is converted into parallel data _ out _ bbuf with the bit width of p through a serial-parallel converter with the bit width of 1: 2; the parallel data _ out _ bbuf with the bit width p realizes the selective output of the p-bit parallel data _ out through a check device MUX, and the selection process is controlled by a control signal bitslip _ turn. The value of bitslip _ turn cycles from 1 to 2, and the data _ out selects different bit combinations of the data _ out _ bbuf to output corresponding to different values.
When the bitslip _ turn is 1, selecting (p-1 to 0) bit of the data _ out _ bbuf to output; when bitslip _ turn is 2, the ((p/2-1 to 0)) bit sum (p-1 to p/2) output of data _ out _ bbuf is selected.
(c) Setting p times of control signals bitslip (bitslip _ pulse)) as a cycle period; each time the bitslip pulse passes p/2 times, then bitslip _ turn is incremented by 1.
During word correction, the control signal vtz generated by the controller is low and Train is high.
In this embodiment, the channel correction process is as follows: p-bit parallel data of the global clock domain is subjected to controllable data bit delay of the parallel data through rambled shift; the channel correction is controlled by a control signal chan _ shift generated by the controller. The controller generates control signals train and vtz as periodic signals, with the positive pulse width of train in each period being
Figure BDA0002505789430000061
Control signal vtz at eachThe negative pulse width in one cycle is
Figure BDA0002505789430000062
fclk_ioThe DDR, which is serial image data, accompanies the clock frequency.
In this embodiment, the channel correction is controlled by a control signal chan _ shift generated by the controller, and the position of the parallel data is relatively delayed by one pixel clock length every time a pulse is generated. The control signal of bitslip _ swap is not generated in the word correction stage, but is inverted under the condition that the first channel training fails, and meanwhile, the correct and wrong times of word correction are cleared.
In the channel correction process, control signals train and vtz generated by the controller are periodic signals; a positive pulse width of train in each period of
Figure BDA0002505789430000063
The phase is the same as the word _ train; vtz has a negative pulse width of
Figure BDA0002505789430000064
The phase is the same as wordstate _ train.
In this embodiment, the data processor employs a virtex 6 device and its internal resources; CMOS image sensors employ a custom product of long-photostudio core.

Claims (5)

1. A serial CMOS image data training method adapting to real-time variation of line period is characterized in that:
the data correction comprises bit correction of a control signal train with a fixed high level, word correction of the control signal train with the fixed high level, and channel correction and data correction completion states of the control signal train with a single pulse width;
after the bit correction of the control signal train for the fixed high level is finished, directly entering the word correction of the control signal train for the fixed high level; after the word correction is successful, directly entering the channel correction of which the control signal train is in a single pulse width from the word correction of which the control signal train is in a fixed high level;
when the first channel correction fails, entering the word correction with the control signal train being a fixed level from the channel correction with the control signal train being a single pulse width, negating the control signal bitslip _ swap, and clearing the correct and wrong times of the word correction; if the second channel correction fails, the channel correction with the single pulse width from the control signal train enters a data correction completion state;
the specific process of the word correction is as follows:
firstly, p/2-bit parallel data _ in output by a special serial-parallel converter iserdes1 is output to parallel data _ t1 through a controllable delayer, a control signal is bitslip _ swap, and no delay is output when the bitslip _ swap is at a low level; when the bitslip _ swap is in a high level, the output is delayed, and the output parallel data _ t1 is delayed 1/2pixel clock cycles relative to the parallel data _ in, namely, the width is
Figure FDA0003053064990000011
fclk_ioDDR companion clock frequency for serial image data;
step two, converting the parallel data _ t1 with the bit width of p/2 into parallel data _ out _ bbuf with the bit width of p through a serial-parallel converter with the bit width of 1: 2; the parallel data _ out _ bbuf with the bit width p realizes the selective output of the p-bit parallel data _ out through a check device MUX, and the selection process is controlled by a control signal bitslip _ turn; circulating the value of bitslip _ turn from 1 to 2, and correspondingly taking different values, and selecting different bit combinations of the data _ out _ bbuf for outputting by the parallel data _ out; the method specifically comprises the following steps:
when the control signal bitslip _ turn is 1, selecting p-1-0 bits of the data _ out _ bbuf to output; when the control signal bitslip _ turn is 2, selecting p/2-1-0 bits and p-1-p/2 bits of the data _ out _ bbuf to output;
setting p times of control signals bitslip as a cycle period; every p/2 times the control signal bitslip pulse passes, the control signal bitslip _ turn is increased by 1.
2. The serial CMOS image data training method adapting to real-time variation of line period as claimed in claim 1, wherein:
during word correction, the controller generates control signal vtz as low and train as high.
3. The serial CMOS image data training method adapting to real-time variation of line period as claimed in claim 1, wherein:
the channel correction process is as follows: p-bit parallel data of the global clock domain is subjected to controllable data bit delay of the parallel data through a RAM based shift register based on the RAM; the controller generates control signals train and vtz as periodic signals, with the positive pulse width of train in each period being
Figure FDA0003053064990000021
The phase is the same as the phase of the control signal word _ train; the control signal vtz has a negative pulse width of
Figure FDA0003053064990000022
The phase is the same as the phase of the control signal word _ train.
4. The serial CMOS image data training method adapting to real-time variation of line period as claimed in claim 1, wherein:
the channel correction is controlled by a control signal chan _ shift generated by a controller, and the position of parallel data is relatively delayed by one pixel clock length every time a pulse is issued.
5. The serial CMOS image data training method adapting to real-time variation of line period as claimed in claim 1, wherein:
the bit correction process is as follows: the input serial image data is firstly subjected to phase-controllable delay through a programmable delay element iodelay 1; the bit correction is controlled by control signals, i delay _ reset _ pulse and i delay _ ce _ pulse, generated by a controller, and is converted into signals, i delay _ reset _ pulse _ io and i delay _ ce _ pulse _ io, respectively sent to the reset and ce pins of the programmable delay element, i delay1, for control through a control asynchronous FIFO; the controller generates a control signal train high and the controller generates a control signal vtz low.
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