CN107482047B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107482047B
CN107482047B CN201710390940.XA CN201710390940A CN107482047B CN 107482047 B CN107482047 B CN 107482047B CN 201710390940 A CN201710390940 A CN 201710390940A CN 107482047 B CN107482047 B CN 107482047B
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pattern
channel
insulating layer
patterns
source
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CN107482047A (zh
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梁正吉
裴东一
裴金钟
宋昇珉
李钟昊
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种半导体装置，其包括：衬底上的绝缘层；第一沟道图案，其位于绝缘层上，并且接触绝缘层；第二沟道图案，其位于第一沟道图案上并且彼此水平地间隔开；栅极图案，其位于绝缘层上，并且包围第二沟道图案；以及各个第二沟道图案之间的源极/漏极图案。

Description

半导体装置
相关申请的交叉引用
本申请要求于2016年6月7日在韩国知识产权局提交的韩国专利申请No.10-2016-0070494的优先权，该申请的公开以引用方式全文并入本文中。
技术领域
本发明构思的示例实施例涉及半导体装置，并且例如，至少一些示例实施例涉及包括环绕栅极(GAA)结构的半导体装置。
背景技术
具有高性能、小尺寸和/或低制造成本特性的半导体装置已用于电子工业中。半导体装置可分为用于存储逻辑数据的半导体存储器装置、用于计算逻辑数据的半导体逻辑装置和包括存储器元件和逻辑元件的混合半导体装置。随着电子工业的高度发展，对高速度、高可靠性和多功能的半导体装置的需求增加了。为了满足半导体装置的这些特性，半导体装置高度集成并且半导体装置中的内部结构也高度复杂化。
发明内容
根据本发明构思的示例实施例，一种半导体装置可包括：衬底上的绝缘层；第一沟道图案，其位于绝缘层上，并且接触绝缘层；第二沟道图案，其位于第一沟道图案上并且彼此水平地间隔开；栅极图案，其位于绝缘层上，并且包围第二沟道图案；以及各个第二沟道图案之间的源极/漏极图案。
根据本发明构思的示例实施例，一种半导体装置可包括：衬底上的绝缘层；沟道图案，其位于绝缘层上并且彼此竖直地间隔开，所述沟道图案包括对应于最下面的一个沟道图案的第一沟道图案和第一沟道图案上的第二沟道图案；栅极图案，其位于绝缘层上并且包围第二沟道图案；以及在栅极图案一侧的源极/漏极图案。第一沟道图案的底表面可相对于衬底的顶表面位于与源极/漏极图案的底表面基本上相同的水平高度。
根据本发明构思的示例实施例，一种半导体装置可包括：接触绝缘层的第一沟道图案；沟道图案上的栅极图案；栅极图案一侧的源极/漏极图案；以及沟道图案上的具有环绕栅极结构的第二沟道图案。
附图说明
如下列附图所示，通过本发明构思的非限制性示例实施例的更具体的描述，本发明构思的以上和其它特征将变得清楚：
通过以下结合附图的详细描述将更加清楚地理解示例实施例；
图1是示出根据示例实施例的半导体装置的平面图；
图2是根据一些示例实施例的沿着图1的线I-I'截取的剖视图；
图3是根据一些示例实施例的沿着图1的线II-II'截取的剖视图；
图4是根据其它示例实施例的沿着图1的线I-I'截取的剖视图；
图5是示出根据示例实施例的半导体装置的平面图；
图6是沿着图5的线I-I'截取的剖视图；
图7A、图8A、图9A、图10A、图11A和图13A是示出制造根据示例实施例的半导体装置的方法的各阶段的平面图；
图7B、图8B、图9B、图10B、图11B、图12A和图13B分别是沿着图7A、图8A、图9A、图10A、图11A和图13A的线I-I'截取的剖视图；以及
图7C、图8C、图9C、图10C、图11C、图12B、图13C分别是沿着图7A、图8A、图9A、图10A、图11A和图13A的线II-II'截取的剖视图。
具体实施方式
现在，将参照示出了一些示例实施例的附图更加完全地描述各个示例实施例。然而，本发明构思可按照许多替代形式实现并且不应理解为仅限于本文阐述的示例实施例。
在附图中，为了清楚起见，夸大了层、膜、面板、区等的厚度。相同的附图标记在整个说明书中指代相同元件。
应该理解，当诸如层、膜、区或衬底的元件被称作“位于”另一元件“上”时，其可直接位于所述另一元件上，或者也可存在中间元件。相反，当元件被称作“直接位于”另一元件“上”时，则不存在中间元件。用于描述元件或层之间的关系的其它词语也应该按照相同方式解释(例如，“在……之间”与“直接在……之间”、“邻近”与“直接邻近”、“连接”与“直接连接”)。如本文所用，术语“和/或”包括相关所列项中的一项或多项的任何和所有组合。
应该理解，虽然本文中可使用术语第一、第二、第三等来描述各个元件、组件、区、层和/或部分，但是这些元件、组件、区、层和/或部分不应被这些术语限制。这些术语仅用于将一个元件、组件、区、层或部分与另一区、层或部分区分开。因此，下面讨论的第一元件、第一组件、第一区、第一层或第一部分可被称作第二元件、第二组件、第二区、第二层或第二部分，而不脱离示例实施例的教导。
为了方便描述，本文中可使用空间相对术语(诸如“在……下方”、“在……之下”、“下”、“在……之上”、“上”等)，以描述附图中所示的一个元件或特征与另一个(一些)元件或特征的关系。应该理解，空间相对术语旨在涵盖使用或操作中的装置的除图中所示的取向之外的不同取向。例如，如果图中的装置颠倒，则被描述为“在其它元件或特征之下”或“在其它元件或特征下方”的元件将因此被取向为“在其它元件或特征之上”。因此，术语“在……之下”可涵盖“在……之上”和“在……之下”这两个取向。装置可按照其它方式取向(旋转90度或位于其它取向)，并且本文所用的空间相对描述语将相应地解释。
本文所用的术语仅是为了描述各个实施例，而不旨在限制示例实施例。如本文所用，除非上下文另外明确地指明，否则单数形式“一”、“一个”和“该”也旨在包括复数形式。还应该理解，当术语“包括”、“包括……的”、“包含”和/或“包含……的”用于本说明书中时，指明存在所列特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
本文参照作为理想实施例(和中间结构)的示意图的剖视图描述示例实施例。这样，作为例如制造技术和/或公差的结果，附图中的形状的变化是可预见的。因此，示例实施例不应被理解为限于本文示出的区的形状，而是包括例如由制造导致的形状的偏差。
除非另外限定，否则本文中使用的所有术语(包括技术和科学术语)具有与示例实施例所属领域的普通技术人员之一通常理解的含义相同的含义。还应该理解，除非本文中另外明确地进行了定义，否则包括诸如在通用词典中定义的那些的术语应该被解释为具有与它们在相关技术的上下文中的含义一致的含义，而不应该按照理想化或过于正式的含义解释它们。
图1是示出根据示例实施例的半导体装置的平面图。图2是根据一些示例实施例的沿着图1的线I-I'截取的剖视图。图3是根据一些示例实施例的沿着图1的线II-II'截取的剖视图。
参照图1、图2和图3，可在衬底100上布置绝缘层102。衬底100可包括硅衬底、硅锗衬底、锗衬底或者从单晶体硅衬底生长的单晶体外延层。绝缘层102可包括氧化硅层。
可在绝缘层102上布置沟道图案110a和110b，并且它们可在相对于衬底100的顶表面的竖直方向上彼此间隔开。沟道图案110a和110b可包括第一沟道图案110a和第二沟道图案110b。第一沟道图案110a可排列为在第一方向X上彼此间隔开并且可在第二方向Y上延伸。第一沟道图案110a可对应于沟道图案110a和110b中的最下面的一个沟道图案。作为示例，第一沟道图案110a可接触绝缘层102。
第二沟道图案110b可布置在第一沟道图案110a上。作为示例，第二沟道图案110b可在竖直方向上布置在单个第一沟道图案110a上并且可彼此水平地间隔开。第二沟道图案110b中的至少一个可布置在单个第一沟道图案110a上，以与所述单个第一沟道图案110a竖直地间隔开。相对于衬底100的顶表面位于相同水平高度的各个第二沟道图案110b可在第一方向X和第二方向Y上彼此间隔开。第二沟道图案110b各自可在第二方向Y上比在第一方向X上延伸得更远。例如，沟道图案110a和110b可包括硅(Si)。
第一沟道图案110a各自可包括第一部分P1和第二部分P2。第一部分P1可布置在在第二方向Y上相邻的第二沟道图案110b之间，第二部分P2可布置在第二沟道图案110b下方。作为示例，第一部分P1的顶表面可相对于衬底100顶表面位于比第二部分P2的顶表面更低的水平高度。作为示例，第一部分P1的厚度T1可小于第二部分P2的厚度T2(T1＜T2)。
可在绝缘层102上布置栅极图案120。栅极图案120可在第一方向X上延伸，并且可在第二方向Y上彼此间隔开。栅极图案120各自可包括导电图案121和栅极绝缘层123。导电图案121可布置在绝缘层102上。导电图案121可包围第二沟道图案110b。例如，导电图案121可布置在第二沟道图案110b的顶表面、侧壁和底表面上。导电图案121可布置在第一沟道图案110a的一些表面上。例如，导电图案121可布置在第一沟道图案110a的顶表面和侧壁上，但是可不布置在第一沟道图案110a的底表面上。例如，导电图案121可包括诸如钽(Ta)、钛(Ti)、铝(Al)、铪(Hf)、钨(W)的至少一种金属、金属氮化物、金属碳化物和/或金属硅化物。
栅极绝缘层123可布置在第一沟道图案110a和第二沟道图案110b与导电图案121之间。布置在第一沟道图案110a的顶表面和侧壁上的栅极绝缘层123可在绝缘层102的顶表面上延伸。作为示例，栅极绝缘层123可接触绝缘层102。例如，栅极绝缘层123可包括高k电介质层和/或氧化硅层。例如，高k电介质层可包括二氧化铪(HfO2)、铪硅氧化物(HfSiO)、铪硅氧氮化物(HfSiON)、氧氮化铪(HfON)、铪铝氧化物(HfAlO)、铪镧氧化物(HfLaO)、二氧化锆(ZrO2)、二氧化钽(TaO2)、锆硅氧化物(ZrSiO)、氧化铝(Al2O3)和氧化镧(La2O3)中的至少一个。
导电图案121可包括第一至第三导电图案(121a、121b和121c)。第一导电图案121a可布置在第一沟道图案110a与最下面的一个第二沟道图案110b之间。第二导电图案121b可布置在在竖直方向上相邻的第二沟道图案110b之间，并且第三导电图案121c可布置在最上面的一个第二沟道图案110b上。第三导电图案121c的厚度可大于第一导电图案121a和第二导电图案121b中的每一个的厚度。
源极/漏极图案SD可布置在第一沟道图案110a上。作为示例，源极/漏极图案SD可布置在在第二方向Y上相邻的栅极图案120之间。例如，源极/漏极图案SD可布置在对应的第一沟道图案110a上，并且可布置在在第二方向Y上相邻的第二沟道图案110b之间。源极/漏极图案SD可布置在第一沟道图案110a的第一部分P1上。源极/漏极图案SD各自可接触第一沟道图案110a和第二沟道图案110b。源极/漏极图案SD的顶表面可相对于衬底100的顶表面位于比最上面的第二沟道图案110b的顶表面更高的水平高度。作为示例，源极/漏极图案SD的底表面11可相对于衬底100位于比第一沟道图案110a的底表面113更高的水平高度。源极/漏极图案SD的下部可位于第一沟道图案110a中。例如，源极/漏极图案SD可包括硅(Si)。作为示例，源极/漏极图案SD可包括外延层。
源极/漏极图案SD可包括杂质。例如，杂质可包括磷(P)、碳(C)、硼(B)和锡(Sn)中的至少一种。在一些示例实施例中，在半导体装置是PMOS晶体管并且第一沟道图案110a和第二沟道图案110b包括硅的情况下，源极/漏极图案SD可包括硅锗或者锗。在其它示例实施例中，在半导体装置是NMOS晶体管并且第一沟道图案110a和第二沟道图案110b包括硅(Si)的情况下，源极/漏极图案SD可包括碳化硅(SiC)。
间隔件131和133可布置在各个栅极图案120的侧壁上。栅极绝缘层123可在导电图案121中的每一个与间隔件131和133中的每一个之间延伸。间隔件131和133可包括第一间隔件131和第二间隔件133。第一间隔件131可布置在第三导电图案121c的侧壁上并且可在第一方向X上延伸。第二间隔件133可布置在第一导电图案121a的侧壁和第二导电图案121b的侧壁上。例如，第二间隔件133可布置在第一导电图案121a与邻近于第一导电图案121a的源极/漏极图案SD之间以及第二导电图案121b与邻近于第二导电图案121b的源极/漏极图案SD之间。第二间隔件133可布置在第二沟道图案110b之间，以彼此竖直地间隔开。第二间隔件133可布置为在第二方向Y上彼此间隔开。作为示例，第二沟道图案110b中的每一个的宽度W1可基本上等于栅极图案120中的每一个在第二方向Y上的宽度W2与一对第一间隔件131和第二间隔件133的宽度W3之和(W1＝W2+W3+W3)。例如，第一间隔件131和第二间隔件133可包括氧化硅层、氮化硅层和/或氧氮化硅层。
掩埋的绝缘层140可布置在在第二方向Y上相邻的栅极图案120之间以及在第一方向X上相邻的源极/漏极图案SD之间。掩埋的绝缘层140的顶表面可与栅极图案120的顶表面基本上共面。例如，掩埋的绝缘层140可包括氧化硅层、氮化硅层和/或氧氮化硅层。
可在栅极图案120和掩埋的绝缘层140上布置层间绝缘层150。例如，层间绝缘层150可包括氧化硅层、氮化硅层和/或氧氮化硅层。接触插塞160可布置在源极/漏极图案SD上。接触插塞160可穿过层间绝缘层150和掩埋的绝缘层140，以接触对应的源极/漏极图案SD。例如，接触插塞160可包括金属氮化物(例如，TiN、TaN、AlN、WN和/或MoN)、金属(例如，W、Al或Cu)和金属硅化物中的至少一种。
图4示出了根据另一示例实施例的半导体装置，并且其是沿着图1的线I-I'截取的剖视图。使用相同的标号或者相同的指示符指代与图1至图3中的相同元件，并且为了简明起见省略对它们的重复描述。
参照图4，源极/漏极图案SD可布置在第一沟道图案110a上以及在第二方向Y上相邻的第二沟道图案110b之间。第一沟道图案110a的第一部分P1的厚度T1可基本上等于第一沟道图案110a的第二部分P2的厚度T2(T1＝T2)。第一沟道图案110a的第一部分P1的顶表面可与第一沟道图案110a的第二部分P2的顶表面基本上共面。第一沟道图案110a的底表面113可相对于衬底100的顶表面位于比源极/漏极图案SD的底表面11更低的水平高度。
图5是示出根据示例实施例的半导体装置的平面图。图6是沿着图5的线I-I'截取的剖视图。使用相同的标号或者相同的指示符指代与图1至图3中的相同元件，并且为了简明起见省略对它们的重复描述。
参照图5和图6，源极/漏极图案SD可穿过第一沟道图案110a。因此，源极/漏极图案SD可接触绝缘层102。第一沟道图案110a可在第一方向X和第二方向Y上彼此间隔开。作为示例，第一沟道图案110a在第二方向Y上的宽度可基本上等于第二沟道图案110b在第二方向Y上的宽度。第一沟道图案110a的底表面13可相对于衬底100的顶表面位于与源极/漏极图案SD的底表面111基本上相同的水平高度。
图7A、图8A、图9A、图10A、图11A和图13A是示出制造根据示例实施例的半导体装置的方法的各阶段的平面图。图7B、图8B、图9B、图10B、图11B、图12A和图13B分别是沿着图7A、图8A、图9A、图10A、图11A和图13A的线I-I'截取的剖视图。图7C、图8C、图9C、图10C、图11C、图12B、图13C分别是沿着图7A、图8A、图9A、图10A、图11A和图13A的线II-II'截取的剖视图。
参照图7A、图7B和图7C，可在衬底100上按次序形成绝缘层102和第一沟道图案110a。可形成牺牲图案110c和第二沟道图案110b，使它们以重复和交替方式堆叠在对应的第一沟道图案110a上。衬底100可包括硅衬底、硅锗衬底、锗衬底或者从单晶体硅衬底生长的单晶体外延层。例如，绝缘层102可包括氧化硅层。
第一沟道图案110a可形成为在第一方向X上彼此间隔开并且可在第二方向Y上延伸。牺牲图案110c和第二沟道图案110b可形成为分别在第一方向X和第二方向Y上彼此间隔开。牺牲图案110c可包括硅锗(SiGe)，并且第二沟道图案110b可包括硅(Si)。
第一沟道图案110a、牺牲图案110c和第二沟道图案110b的形成可包括以下步骤：在绝缘层102上形成包括硅的第一半导体层；在第一半导体层上以重复和交替方式形成包括硅锗的第二半导体层和包括硅的第三半导体层；以及将第一半导体层、第二半导体层和第三半导体层图案化以形成分别在第一方向X上彼此间隔开并且在第二方向Y上延伸的第一半导体图案、第二半导体图案和第三半导体图案。
第一沟道图案110a、牺牲图案110c和第二沟道图案110b的形成还可包括以下步骤：形成牺牲绝缘图案210以共形地覆盖最上面的第三半导体图案的顶表面、绝缘层102的通过在第一方向X上相邻的第一半导体图案之间、在第一方向X上相邻的第二半导体图案之间以及在第一方向X上相邻的第三半导体图案之间的空间暴露的顶表面的那些部分以及第一半导体图案至第三半导体图案的通过所述空间暴露的侧壁；在牺牲绝缘图案210上形成牺牲导电图案212以填充所述空间；在牺牲导电图案212上形成第二掩模图案214；形成第一间隔件131以覆盖牺牲绝缘图案210、牺牲导电图案212和第二掩模图案214的侧壁；以及利用第二掩模图案214、牺牲导电图案212和第一间隔件131作为蚀刻掩模将第一半导体图案至第三半导体图案图案化。
可在在第二方向Y上相邻的牺牲图案110c之间、在第二方向Y上相邻的第二沟道图案110b之间以及在第二方向Y上相邻的间隔件131之间形成沟槽220。
牺牲绝缘图案210可包括绝缘材料(例如，氧化硅、氮化硅或氧氮化硅)。例如，牺牲导电图案212可包括多晶硅。第二掩模图案214可包括绝缘材料(例如，氧化硅、氮化硅或者氧氮化硅)。例如，第一间隔件131可包括氧化硅层、氮化硅层和/或氧氮化硅层。
参照图8A、图8B和图8C，可蚀刻牺牲图案110c的通过沟槽220暴露的一些部分以使得牺牲图案110c凹进。因此，凹进区225可各自形成在彼此竖直相邻的每个第一沟道图案110a与每个最下面的第二沟道图案110b之间以及彼此竖直相邻的第二沟道图案110b之间。作为示例，通过蚀刻处理，牺牲图案110c之间的沟槽220的宽度WD1可大于第二沟道图案110b之间的沟槽220的宽度WD2(WD1＞WD2)。可利用相对于第一沟道图案110a和第二沟道图案110b具有蚀刻选择性的蚀刻配方去除牺牲图案110c的所述部分。例如，牺牲图案110c的蚀刻选择性可为第一沟道图案110a和第二沟道图案110b的蚀刻选择性约10倍。因此，虽然蚀刻了牺牲图案110c的一部分，但是第一沟道图案110a和第二沟道图案110b可不被蚀刻。
参照图9A、图9B和图9C，第二间隔件133可形成在牺牲图案110c的侧壁上。可通过以下步骤在凹进区225中选择性地或局部形成第二间隔件133：形成间隔件层以覆盖通过沟槽220暴露的第一沟道图案110a的顶表面和侧壁、第二沟道图案110b的侧壁、第一间隔件131的外侧壁以及第二掩模图案214的顶表面，并且填充凹进区225；以及在间隔件层上执行蚀刻处理(例如，回蚀处理)。通过蚀刻处理，可暴露出第一沟道图案110a的顶表面和侧壁、第二沟道图案110b的侧壁、第一间隔件131的外侧壁和第二掩模图案214的顶表面。
可在沟槽220中形成源极/漏极图案SD。可通过利用通过沟槽220暴露的第一沟道图案110a的顶表面和侧壁、第二沟道图案110b的侧壁作为种子执行外延生长处理来形成源极/漏极图案SD。换句话说，源极/漏极图案SD可包括外延层。作为示例，源极/漏极图案SD的顶表面可相对于衬底100的顶表面位于比牺牲导电图案212的顶表面更低的水平高度。源极/漏极图案SD可包括杂质。例如，杂质可包括磷(P)、碳(C)、硼(B)和锡(Sn)中的至少一种。
根据示例实施例，由于在沟槽220的底表面和邻近于沟槽220的底表面的侧壁暴露的第一沟道图案110a是由半导体材料形成的，因此可通过从第一沟道图案110a的生长外延层容易地形成源极/漏极图案SD。
可在源极/漏极图案SD上形成掩埋的绝缘层140。掩埋的绝缘层140可填充牺牲导电图案212之间的沟槽220和在第一方向X上相邻的源极/漏极图案SD之间的空间。例如，可通过以下步骤形成掩埋的绝缘层140：形成绝缘层以填充牺牲图案212之间的沟槽220和在第一方向X上相邻的源极/漏极图案SD之间的空间，并覆盖第二掩模图案214的顶表面；以及在绝缘层上执行平面化处理直至将第二掩模图案214的顶表面暴露出来为止。掩埋的绝缘层140可包括绝缘材料(例如，氧化硅、氮化硅和/或氧氮化硅)。
参照图10A、图10B和图10C，可将掩埋的绝缘层140的上部和第二掩模图案214的上部去除，以暴露出牺牲导电图案212的顶表面。通过所述去除处理也可使第一间隔件131的顶表面暴露出来。例如，可利用化学机械抛光处理执行去除处理。作为示例，通过去除处理，从牺牲导电图案212的底表面至牺牲导电图案212的顶表面的高度可减小。牺牲导电图案212的顶表面可与掩埋的绝缘层140的顶表面共面。
参照图11A、图11B和图11C，按次序将牺牲导电图案212和牺牲绝缘图案210去除以形成第一间隙区GRR1。通过第一间隙区GRR1可使第一间隔件131的内侧壁、最上面的第二沟道图案110b的顶表面、第一沟道图案110a和第二沟道图案110b的面对第一方向X的侧壁以及绝缘层102的顶表面的一些部分暴露出来。可利用相对于第一间隔件131、第二沟道图案110b和掩埋的绝缘层140具有蚀刻选择性的蚀刻配方去除牺牲导电图案212和牺牲绝缘图案210。
参照图11A、图12A和图12B，可去除通过第一间隙区GRR1暴露的牺牲图案110c，以在第一沟道图案110a和在竖直方向上与第一沟道图案110a相邻的最下面的第二沟道图案110b之间以及彼此竖直相邻的第二沟道图案110b之间形成第二间隙区GRR2。第二间隙区GRR2可暴露出第一沟道图案110a的顶表面的一些部分、第二沟道图案110b的顶表面和底表面的一些部分和第二间隔件133的内侧壁。可利用相对于第一沟道图案110a和第二沟道图案110b、第一间隔件131和第二间隔件133以及掩埋的绝缘层140具有蚀刻选择性的蚀刻配方去除牺牲图案110c。作为示例，牺牲图案110c的蚀刻选择性可为第一沟道图案110a和第二沟道图案110b的蚀刻选择性的约10倍。
参照图13A、图13B和图13C，可在第一间隙区GRR1和第二间隙区GRR2中按次序形成栅极绝缘层123和导电图案121。可通过以下步骤形成栅极绝缘层123和导电图案121：形成绝缘层以共形地覆盖绝缘层102的顶表面的一些部分、第一沟道图案110a的顶表面的一些部分、第二沟道图案110b的顶表面的一些部分、第二沟道图案110b的底表面的一些部分、第二间隔件133的内侧壁、第一间隔件131的内侧壁和顶表面以及掩埋的绝缘层140的顶表面；形成包括金属的导电层以覆盖绝缘层并填充第一间隙区GRR1和第二间隙区GRR2；以及通过执行化学机械抛光处理蚀刻绝缘层和导电层直至暴露出掩埋的绝缘层140的顶表面为止。
再参照图1、图2和图3，可形成层间绝缘层150以覆盖栅极绝缘层123、导电图案121、第一间隔件131和掩埋的绝缘层140。层间绝缘层150可包括绝缘材料(例如，氧化硅、氮化硅和/或氧氮化硅)。接触插塞160可布置在各个源极/漏极图案SD上。可通过蚀刻层间绝缘层150的一部分和掩埋的绝缘层140的一部分以形成接触孔以及用金属材料填充该接触孔来形成接触插塞160。
根据本发明构思的示例实施例，可将对应于最下面的一个沟道图案并且由半导体材料形成的第一沟道图案110a布置为接触设置在衬底100上的绝缘层102，并且可在其中形成有源极/漏极图案SD的沟槽的底表面和邻近于底表面的侧壁将该第一沟道图案110a暴露出来。因此，可通过利用第一沟道图案110a作为种子从第一沟道图案110a的生长外延层容易地形成源极/漏极图案SD。
虽然已经参照本发明构思的示例实施例具体示出并且描述了本发明构思的示例实施例，但是本领域普通技术人员应该理解，可在不脱离由权利要求限定的示例实施例的精神和范围的情况下对其作出各种形式和细节上的改变。

Claims (11)

1.一种半导体装置，包括：
衬底上的绝缘层；
绝缘层上的第一沟道图案，所述第一沟道图案接触绝缘层；
第一沟道图案上的第二沟道图案，所述第二沟道图案彼此水平地间隔开；
绝缘层上的栅极图案，所述栅极图案包围所述第二沟道图案；以及
第二沟道图案之间的源极/漏极图案，
其中，源极/漏极图案位于第一沟道图案上，以使得源极/漏极图案不接触绝缘层。
2.根据权利要求1所述的半导体装置，其中，栅极图案包括：
导电图案，其位于第一沟道图案的顶表面和侧壁上以及第二沟道图案的顶表面、底表面和侧壁上；以及
栅极绝缘层，其位于导电图案与第一沟道图案和第二沟道图案之间。
3.根据权利要求2所述的半导体装置，其中，栅极绝缘层在绝缘层的顶表面上延伸。
4.根据权利要求1所述的半导体装置，还包括：
栅极图案与源极/漏极图案之间的间隔件，间隔件通过介于它们之间的对应的一个第二沟道图案彼此竖直地间隔开。
5.根据权利要求4所述的半导体装置，其中，间隔件包括：
第一间隔件，其选择性地位于第一沟道图案与最下面的第二沟道图案之间和第二沟道图案之间，以及
第二间隔件，其位于最上面的第二沟道图案上，第二间隔件在一方向上延伸。
6.根据权利要求1所述的半导体装置，其中，第一沟道图案包括源极/漏极图案下方的第一部分和第二沟道图案下方的第二部分，
其中，第一部分的厚度小于第二部分的厚度。
7.根据权利要求1所述的半导体装置，其中，第一沟道图案包括源极/漏极图案下方的第一部分和第二沟道图案下方的第二部分，
其中，第一部分的厚度等于第二部分的厚度。
8.根据权利要求1所述的半导体装置，其中，源极/漏极图案接触第一沟道图案和第二沟道图案。
9.一种半导体装置，包括：
接触绝缘层的第一沟道图案；
第一沟道图案上的栅极图案；
栅极图案一侧的源极/漏极图案；以及
第一沟道图案上的具有环绕栅极结构的第二沟道图案，
其中，源极/漏极图案位于第一沟道图案上，以使得源极/漏极图案不接触绝缘层。
10.根据权利要求9所述的半导体装置，其中，栅极图案包括：
导电图案；以及
栅极绝缘层，其位于导电图案与第一沟道图案之间和导电图案与第二沟道图案之间。
11.根据权利要求9所述的半导体装置，其中，第一沟道图案包括源极/漏极图案下方的第一部分和栅极图案下方的第二部分，
其中，第一部分的厚度小于第二部分的厚度。
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