CN107481980A - 一种薄型指纹芯片封装方法及封装结构 - Google Patents
一种薄型指纹芯片封装方法及封装结构 Download PDFInfo
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- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000003292 glue Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 238000009422 external insulation Methods 0.000 claims description 3
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- 239000010935 stainless steel Substances 0.000 claims description 3
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- 238000009413 insulation Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 18
- 238000005538 encapsulation Methods 0.000 abstract description 9
- 238000012856 packing Methods 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 3
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- 238000005530 etching Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
本发明提供一种指纹识别芯片的封装方法以及封装结构,封装方法包括:提供指纹识别芯片,每一指纹识别芯片具有指纹识别区以及位于所述指纹识别区外的连接焊盘;基板上附着有粘性体,所述的指纹识别芯片的第二表面通过所述的粘性体固定于基板上;导电柱与指纹识别芯片一同塑封在一个塑封体中;塑封体的第一表面形成重布线结构,所述重布线层将指纹识别芯片的连接焊盘和导电柱进行电连接;塑封体第二表面进行磨削,将导电柱暴露并达到设计厚度;对塑封体进行切割形成独立的芯片封装结构;暴露出的导电柱直接柔性电路板的电触电相连接。该发明降低指纹识别芯片的封装结构尺寸从而提高指纹识别芯片的集成度,代替传统的硅穿孔和减少使用电镀工艺有效降低了封装成本同时提高封装良率。
Description
技术领域
本发明涉及一种薄型指纹芯片封装方法及封装结构,属于半导体封装技术领域。
背景技术
指纹识别技术具有安全性好,可靠性高,使用简单等特点,使得其广泛应用于各种安全领域。随着移动支付等应用的发展,指纹识别技术被广泛应用于移动终端,例如手机、平板等领域。
根据安装位置的不同,在移动终端上的指纹识别器件分为前置安装与后置安装,由于前置安装使用方便,且能与压感传感器相结合,使得该安装方式逐步成为主流。随着显示技术的发展,特别是OLED技术的广泛使用,显示模组的厚度大幅度的降低,为了确保移动终端整体的厚度的减小,对指纹芯片的封装高度提出了新的挑战。
传统的指纹封装采用全包封的封装结构,该结构中位于指纹芯片正面的感应区连接点通过打线的方式与基板上的焊盘连接,由于打线工艺存在线弧高度使得塑封后的整体厚度较大,且较厚的塑封层使得感应区灵敏度有所下降,该方案成本低廉,主要应用于低端手机。为了消除线弧导致的封装厚度过大的问题,引入了Trench(刻蚀凹槽)技术,通过再布线技术将指纹芯片正面的感应区连接点引至凹槽处,确保线弧的最高点低于芯片感应平面,从而降低封装的整体厚度。
为了进一步降低封装厚度采用TSV(硅穿孔)技术直接将感应区的连接点垂直连接到芯片背面与基板连接,但是由于基板的存在,无论Trench和TSV技术能达到的极限厚度都有所限制。
另外Trench和TSV工艺中需要的硅刻蚀与镀铜工艺成本高,产率低且环境成本高。附图1~3分别是现有全包封,Trench和TSV的封装技术的截面图。
为降低封装的整体厚度以下专利从不同角度进行了改进与改良。
专利CN104051366A,CN104051367A采用聚合物改变了盖板的厚度,用导线以及穿孔技术连接指纹芯片感应区与电路版,由于载板的存在使得整体厚度难以降低。
专利CN106022253A提出一种将指纹芯片通过下部垫高层键合在柔性电路板上,从而调节指纹模组的设计高度,但文中并没有提及如何将指纹芯片的电极从上部引到下部,以及如何将芯片进行可靠的超薄封装。
专利CN106485236A将指纹放置在LGA基板上,统一打线连接后一起塑封,之后再进行切割以提高生产效率。
专利CN10654892A采用刻蚀的工艺将指纹芯片的晶圆背面先制作出凹槽,然后在凹槽内产生贯穿孔,通过重布线技术将芯片正面的焊点与背面相连,该工艺需要用到刻蚀技术,成本高,且生产率不高。
发明内容
本发明为解决现有技术中存在的不足,提出一种薄型指纹识别芯片的封装结构和封装方法,所述封装结构不需要基板,对感应芯片灵敏度的要求降低,适合对封装高度要求较低的场合。
为了解决上述技术问题,本发明提供了一种薄型指纹芯片封装方法,包括以下步骤:
步骤1.使用作为临时支撑的基板,并在该基板上附着有粘性体,将指纹识别芯片的非指纹识别区面通过粘性体固定在基板上,以指纹识别区和位于指纹识别区外的连接焊盘作为指纹识别芯片的第一表面,该非指纹识别区面为指纹识别芯片的第二表面;
步骤2.在指纹识别芯片的四周固定导电柱;
步骤3.将导电柱和指纹识别芯片塑封在一个塑封体中,以与所述指纹识别芯片第一表面共面的作为塑封体的第一表面,以不与指纹识别芯片第一表面共面的作为塑封体的第二表面;
步骤4.在塑封体的第一表面上将指纹识别芯片的连接焊盘和导电柱进行电连接;
步骤5.将塑封体第二表面进行磨削,直至导电柱暴露。
进一步的,步骤4具体包括以下步骤:
4.1在塑封体第一表面施加第一层绝缘体膜;
4.2将导电柱和指纹识别芯片的连接焊盘上的绝缘体膜移除;
4.3在经过步骤4.2处理后的导电柱和指纹识别芯片上形成导电膜,并形成重布线层;
4.4完成重布线层后再施加一层绝缘层与外界绝缘。
进一步的,基板为不透光的不锈钢基板或为透光的玻璃或硅基板。
进一步的,粘结体为热剥离胶或UV剥离胶。
进一步的,塑封体的软化温度低于粘结体失去粘性的温度。
本发明还公开了一种薄型指纹芯片封装结构,包括指纹识别芯片、设置在所述指纹识别芯片周围的导电柱和通过导电柱与指纹识别芯片相连的柔性电路板,所述指纹识别芯片包括指纹识别区和位于指纹识别区外的连接焊盘,所述导电柱的一侧通过重布线层与连接焊盘相连,该导电柱的另一侧与柔性电路板连接。
进一步的,重布线层与除指纹芯片连接焊盘和导电柱之外的物体绝缘。
进一步的,导电柱高度高于所述指纹识别芯片高度。
有益效果:本发明与现有技术相比,具有以下优点:降低指纹识别芯片的封装结构尺寸从而提高指纹识别芯片的集成度,采用放置导电柱的方式代替传统的硅穿孔并减少使用电镀工艺有效降低了封装成本同时提高封装良率。
附图说明
图1是现有全包封技术的剖面结构示意图;
图2是现有Trench封装技术的剖面结构示意图;
图3是现有TSV封装技术的剖面结构示意图;
图4(a)是本发明优选实施案例中最终封装器件的截面图;
图4(b)是本发明优选实施案例中最终封装器件的俯视示意图;
图5是本发明优选实施例基板的平面示意图;
图6为图5沿A-A截面示意图;
图7为封装体完成重布线以及背部磨削后切割前的截面示意图。
具体实施方式
本实施例提供的指纹识别芯片封装方法以及利用该封装方法形成的指纹识别芯片封装结构。参考图5展示了基板和放置于其上的芯片的关系,图6为其截面示意。基板10上附着有临时粘性体160,导电柱120和指纹芯片100的感应面105朝下放置在粘性体上,导电柱120的高度不小于芯片100的高度。
在本实施中,将位于粘结体160上的导电柱120和芯片100将整体塑封于塑封体130中,塑封体130的边角不大于粘结体160,粘结体160的边界不大于基板10的边界。指纹识别芯片的感应面在塑封体的第一表面,相对地另一个面为塑封体的第二表面。
在本实施中,若基板10为不锈钢基板,临时粘结体160的材质为对温度敏感的热剥离胶,当基板温度提高一定水平时,粘结体160时将失去粘性,然后移除基板10。塑封体130的软化温度低于粘结体160失去粘性的温度。
若基板10选用透光基板,则临时粘结体160的材质为UV胶,将UV光透过基板照射到粘结体160使其失去粘性,然后移除基板10。
移除基板10之后通过清洗工艺清除塑封体130上残留的临时粘结体。
清洗后的塑封体130可作为新的载板在其识别芯片的感应面采用光刻、刻蚀以及电镀沉积的方法制作出重布线层110,其中介电材料层140可为聚酰亚胺。该重布线层110用于将指纹识别芯片100的连接焊盘和导电柱110相连,请参考图4(b)。
重布线层110完成后,将会涂覆一层绝缘层将重布线层与外界绝缘,该层的厚度范围为5~30微米。
完成重布线层后,将采用磨削的方法在塑封体的第二表面进行磨削,直到导电柱完全暴露并且达到设计的高度。
请参考图7,采用切割工艺切割完成磨削后的塑封体130,将相邻的指纹芯片封装彼此分离,形成多个独立的指纹识别芯片封装结构。所述的经过磨削后的导电柱120可与柔性电路板150直接键合。
Claims (8)
1.一种薄型指纹芯片封装方法,其特征在于:包括以下步骤:
步骤1.使用作为临时支撑的基板,并在该基板上附着有粘性体,将指纹识别芯片的非指纹识别区面通过粘性体固定在基板上,以指纹识别区和位于指纹识别区外的连接焊盘作为指纹识别芯片的第一表面,与第一表面相对的为指纹识别芯片的第二表面;
步骤2.在指纹识别芯片的四周固定导电柱;
步骤3.将导电柱和指纹识别芯片塑封在一个塑封体中,以与所述指纹识别芯片第一表面共面的表面作为塑封体的第一表面,与塑封体的第一表面相对应的面作为塑封体的第二表面;
步骤4.在塑封体的第一表面上将指纹识别芯片的连接焊盘和导电柱进行电连接;
步骤5.将塑封体第二表面进行磨削,直至导电柱暴露。
2.根据权利要求1所述的一种薄型指纹芯片封装方法,其特征在于:所述步骤4具体包括以下步骤:
4.1在塑封体第一表面施加第一层绝缘体膜;
4.2将导电柱和指纹识别芯片的连接焊盘上的绝缘体膜移除;
4.3在经过步骤4.2处理后的导电柱和指纹识别芯片上形成导电膜,并形成重布线层;
4.4完成重布线层后再施加一层绝缘层与外界绝缘。
3.根据权利要求1或2所述的一种薄型指纹芯片封装方法,其特征在于:所述基板为不透光的不锈钢基板或为透光的玻璃或硅基板。
4.根据权利要求1或2所述的一种薄型指纹芯片封装方法,其特征在于:所述粘结体为热剥离胶或UV剥离胶。
5.根据权利要求1或2所述的一种薄型指纹芯片封装方法,其特征在于:所述塑封体的软化温度低于粘结体失去粘性的温度。
6.采用权利要求1或2所述的一种薄型指纹芯片封装方法制得的封装结构,其特征在于:包括指纹识别芯片、设置在所述指纹识别芯片周围的导电柱和通过导电柱与指纹识别芯片相连的柔性电路板,所述指纹识别芯片包括指纹识别区和位于指纹识别区外的连接焊盘,所述导电柱的一侧通过重布线层与连接焊盘相连,该导电柱的另一侧与柔性电路板连接。
7.根据权利要求6所述的一种薄型指纹芯片封装结构,其特征在于:所述重布线层与除指纹芯片连接焊盘和导电柱之外的物体绝缘。
8.根据权利要求6所述的一种薄型指纹芯片封装结构,其特征在于:所述导电柱高度高于所述指纹识别芯片高度。
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