CN107480090A - A kind of circuit and method that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment - Google Patents
A kind of circuit and method that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment Download PDFInfo
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- CN107480090A CN107480090A CN201710645572.9A CN201710645572A CN107480090A CN 107480090 A CN107480090 A CN 107480090A CN 201710645572 A CN201710645572 A CN 201710645572A CN 107480090 A CN107480090 A CN 107480090A
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- chip selection
- gpio
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
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- Dc Digital Transmission (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a kind of circuit that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment and method interface equipment to include, main equipment and slave unit, connected between main equipment and slave unit by communication data line, and the chip selection signal pin of main equipment and the chip selection signal pin of slave unit are connected by chip selection signal line；Wherein, including：A holding circuit is provided, holding circuit includes：First resistor, it is series on chip selection signal line；Electric capacity, one end are connected to the chip selection signal pin of slave unit, other end ground connection；Resistor voltage divider circuit, one end are connected with a power supply circuit, and other end ground connection, the divider node of resistor voltage divider circuit is connected on the chip selection signal pin of main equipment；Peripheral apparatus, it is that low level is effective to be series at peripheral apparatus between resistor voltage divider circuit and ground.The beneficial effect of its technical scheme is, GPIO function can be achieved on chip selection signal line, and chip selection signal line will not be interfered.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of GPIO functions of being realized in Serial Peripheral Interface (SPI) equipment
Circuit and method.
Background technology
SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)), is a kind of high speed, full duplex, together
The communication bus of step, takes four lines on the pin of chip, this communication protocol of increasing integrated chip, such as
AT91RM9200；With existing chip integration more and more higher, it is more next that it encapsulates pin that is also less and less therefore making chip
It is fewer, therefore set up GPIO pin on chip in needs and realize that GPIO functions then seem extremely difficult, existing way is logical
Cross and set up I/O expansion chip, or the related SPI controllers of IO are provided and realized, but both implementations not only cost compared with
Height, and need to take bigger space on a printed circuit board.
The content of the invention
For the above mentioned problem present in Serial Peripheral Interface (SPI) equipment in the prior art, one kind is now provided and is intended to piece choosing letter
GPIO functions are realized on number line, and the circuit and method not interfered to chip selection signal line.
Concrete technical scheme is as follows：
A kind of circuit that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, Serial Peripheral Interface (SPI) equipment include, and master sets
Standby and slave unit, connected between the main equipment and the slave unit by communication data line, and the piece of the main equipment
The chip selection signal pin of signal pins and the slave unit is selected to be connected by chip selection signal line；It is characterised in that it includes：
A holding circuit is provided, the holding circuit includes：
First resistor, it is series on the chip selection signal line；
Electric capacity, one end are connected to the chip selection signal pin of the slave unit, other end ground connection；
Resistor voltage divider circuit, one end are connected with a power supply circuit, other end ground connection, the partial pressure section of the resistor voltage divider circuit
Point is connected on the chip selection signal pin of the main equipment；
Peripheral apparatus, it is series between the resistor voltage divider circuit and ground；
The peripheral apparatus is that low level is effective.
Preferably, the bleeder circuit includes：
One second resistance, it is connected between the power supply circuit and the divider node；
One 3rd resistor, it is connected between the divider node and the peripheral apparatus.
Preferably, the resistance of the first resistor is between 1kohm-10kohm.
Preferably, the value of the electric capacity is between 1pF-1nF.
Preferably, the resistance of the second resistance is between 4.7kohm-100kohm.
Preferably, the resistance of the 3rd resistor is between 1ohm-1kohm.
Also include a kind of method for realizing GPIO functions, wherein, connect applied to above-mentioned in serial peripheral
The circuit of GPIO functions is realized on jaws equipment, specifically includes following steps：
Step S1, the main equipment a predetermined period start export one first scheduled time high level to maintain
It is idle condition to state chip selection signal line；
Step S2, described main equipment is in the chip selection signal pin that the main equipment is received in one second scheduled time
Input, and whether the level for judging to input is low level,
If so, judge to receive GPIO signals,
If it is not, judge not receiving GPIO signals；
Step S3, described main equipment maintains current state to the predetermined period to terminate；
Step S4, return to step S1.
Preferably, the predetermined period is 8 milliseconds.
Preferably, first scheduled time is 3 milliseconds.
Preferably, second scheduled time is 1 millisecond.
Above-mentioned technical proposal has the following advantages that or beneficial effect：GPIO function can be achieved on chip selection signal line, and
And chip selection signal line will not be interfered, overcome and set up I/O expansion chip by crossing in the prior art, or IO phases are provided
The SPI controller of pass realizes that the cost that GPIO functional bands are come is higher, and needs to take bigger space on a printed circuit board
The defects of.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is a kind of structural representation for the circuit embodiments that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment of the present invention
Figure；
Fig. 2 is a kind of schematic flow sheet of the embodiment for the method for realizing GPIO functions of the present invention.
Reference represents：
1st, main equipment；2nd, slave unit；3rd, holding circuit；4th, bleeder circuit；5th, peripheral apparatus；6th, power supply circuit；31st, first
Resistance, 32, electric capacity；41st, second resistance；42nd, 3rd resistor.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
Technical scheme includes a kind of circuit that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment；.
As shown in figure 1, a kind of circuit that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, Serial Peripheral Interface (SPI) equipment
Including, main equipment 1 and slave unit 2, connected between main equipment 1 and slave unit 2 by communication data line, and main equipment 1
Chip selection signal pin and the chip selection signal pin of slave unit 2 are connected by chip selection signal line；Wherein, including：
A holding circuit 3 is provided, holding circuit 3 includes：
First resistor 31, it is series on chip selection signal line；
Electric capacity 32, one end are connected to the chip selection signal pin of slave unit 2, other end ground connection；
Resistor voltage divider circuit 4, one end are connected with a power supply circuit 6, other end ground connection, the partial pressure section of resistor voltage divider circuit 4
Point is connected on the chip selection signal pin of main equipment 1；
Peripheral apparatus 5, it is series between resistor voltage divider circuit 4 and ground；
Peripheral apparatus 5 is that low level is effective.
I/O expansion chip is set up for setting up the use of GPIO functions on chip in the prior art, or IO correlations are provided
The cost that SPI controller is brought is higher and the problem of needing to take bigger space on a printed circuit board；
In the present invention, by the holding circuit 3 and resistor voltage divider circuit 4 of setting, after peripheral apparatus input low level,
Main equipment 1 receives GPIO signals, and before low level is not received, the electric capacity 32 in holding circuit 3 is in charged state, and
After the peripheral apparatus 5 of bleeder circuit 4 is connected, the voltage of bleeder circuit 4 reduces, that is, after exporting the low level now power-off of electric capacity 32
Start to discharge, to maintain the chip select pin of slave unit 2 to continue to keep high level, to avoid causing signal interference to slave unit 2.
In a kind of preferably embodiment, bleeder circuit 4 includes：
One second resistance 41, is connected between power supply circuit 6 and divider node；
One 3rd resistor 42, is connected between divider node and peripheral apparatus.
In above-mentioned technical proposal, the driving force on peripheral apparatus 5 can be by adjusting second resistance 41 and 3rd resistor 42
To realize.
In a kind of preferably embodiment, the resistance of first resistor 31 is between 1kohm-10kohm.
In a kind of preferably embodiment, the value of electric capacity 32 is between 1pF-1nF.
In a kind of preferably embodiment, the resistance of second resistance 41 is between 4.7kohm-100kohm.
In a kind of preferably embodiment, the resistance of 3rd resistor 42 is between 1ohm-1kohm.
In above-mentioned technical proposal, it can be can be achieved by adjusting the resistance of first resistor 31 and the value of electric capacity 32 of electric capacity 32,
Discharge the time of high level.
Also include a kind of method for realizing GPIO functions in technical scheme, wherein, gone here and there applied to above-mentioned
The circuit of GPIO functions is realized on row Peripheral Interface Device, as shown in Fig. 2 specifically including following steps：
Step S1, main equipment 1 a predetermined period the high level for starting to export one first scheduled time to maintain piece to select
Signal wire is idle condition；
Step S2, main equipment 1 is in the input for the chip selection signal pin that main equipment 1 is received in one second scheduled time, and sentences
Whether the level of disconnected input is low level,
If so, judge to receive GPIO signals,
If it is not, judge not receiving GPIO signals；
Step S3, main equipment 1 maintains current state to predetermined period to terminate；
Step S4, return to step S1.
In above-mentioned technical proposal, peripheral apparatus can be button.
In a kind of preferably embodiment, predetermined period is 8 milliseconds.
In a kind of preferably embodiment, first scheduled time was 3 milliseconds.
In a kind of preferably embodiment, second scheduled time was 1 millisecond.
Illustrated below with a kind of specific embodiment, it is assumed that predetermined period is 8 milliseconds, and first scheduled time was 3 millis
Second, second scheduled time was 1 millisecond；
In main equipment 1 after the high level that idle condition exports 3 milliseconds, the reception chip selection signal of main equipment 1 draws in 1 millisecond
The input of pin, judge to receive GPIO signals if low level is received as, main equipment 1 performs related behaviour according to GPIO signals
Make, such as read-write operation.It is then no GPIO signals input for high level, after low level is received, in order to avoid low level
Output causes effect of signals, the electric capacity 32 in holding circuit 3 now is changed into putting from charged state to slave unit 2 to slave unit 2
Electricity condition, to maintain the chip selection signal pin of slave unit 2 as high level state, until predetermined period terminates.
It should be noted that the idle timer period of the chip selection signal line between main equipment and slave unit is generally 8 milliseconds,
Predetermined period is arranged to 8 milliseconds in order to facilitate in the control present invention, 3 milliseconds are to export high level maintenance idle condition, 4 milliseconds
Maintain slave unit 2 chip selection signal pin be high level be in order to consider electric capacity 32 from discharge capability.
Preferred embodiments of the present invention are the foregoing is only, not thereby limit embodiments of the present invention and protection model
Enclose, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Scheme obtained by equivalent substitution and obvious change, should be included in protection scope of the present invention.
Claims (10)
1. a kind of circuit that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, Serial Peripheral Interface (SPI) equipment include, main equipment
And slave unit, connected between the main equipment and the slave unit by communication data line, and the piece choosing of the main equipment
The chip selection signal pin of signal pins and the slave unit is connected by chip selection signal line；It is characterised in that it includes：
A holding circuit is provided, the holding circuit includes：
First resistor, it is series on the chip selection signal line；
Electric capacity, one end are connected to the chip selection signal pin of the slave unit, other end ground connection；
Resistor voltage divider circuit, one end are connected with a power supply circuit, and other end ground connection, the divider node of the resistor voltage divider circuit connects
It is connected on the chip selection signal pin of the main equipment；
Peripheral apparatus, it is series between the resistor voltage divider circuit and ground；
The peripheral apparatus is that low level is effective.
2. the circuit according to claim 1 that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, it is characterised in that institute
Stating bleeder circuit includes：
One second resistance, it is connected between the power supply circuit and the divider node；
One 3rd resistor, it is connected between the divider node and the peripheral apparatus.
3. the circuit according to claim 1 that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, it is characterised in that institute
The resistance of first resistor is stated between 1kohm-10kohm.
4. the circuit according to claim 1 that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, it is characterised in that institute
The value of electric capacity is stated between 1pF-1nF.
5. the circuit according to claim 2 that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, it is characterised in that institute
The resistance of second resistance is stated between 4.7kohm-100kohm.
6. the circuit according to claim 2 that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment, it is characterised in that institute
The resistance of 3rd resistor is stated between 1ohm-1kohm.
A kind of 7. method for realizing GPIO functions, it is characterised in that applied to as described in any in claim 1-6 serial
The circuit of GPIO functions is realized on Peripheral Interface Device, specifically includes following steps：
Step S1, the main equipment a predetermined period the high level for starting to export one first scheduled time to maintain described
It is idle condition to select signal wire；
Step S2, described main equipment is defeated in the chip selection signal pin that the main equipment is received in one second scheduled time
Enter, and whether the level for judging to input is low level,
If so, judge to receive GPIO signals；
If it is not, judge not receiving GPIO signals；
Step S3, described main equipment maintains current state to the predetermined period to terminate；
Step S4, return to step S1.
8. the method according to claim 7 for realizing GPIO functions, it is characterised in that the predetermined period is 8 milliseconds.
9. the method according to claim 7 for realizing GPIO functions, it is characterised in that first scheduled time is 3 millis
Second.
10. the method according to claim 7 for realizing GPIO functions, it is characterised in that second scheduled time is 1 milli
Second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710645572.9A CN107480090B (en) | 2017-08-01 | 2017-08-01 | Circuit and method for realizing GPIO function on serial peripheral interface device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710645572.9A CN107480090B (en) | 2017-08-01 | 2017-08-01 | Circuit and method for realizing GPIO function on serial peripheral interface device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107480090A true CN107480090A (en) | 2017-12-15 |
| CN107480090B CN107480090B (en) | 2020-08-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710645572.9A Active CN107480090B (en) | 2017-08-01 | 2017-08-01 | Circuit and method for realizing GPIO function on serial peripheral interface device |
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| CN (1) | CN107480090B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108763139A (en) * | 2018-04-20 | 2018-11-06 | 青岛海信电器股份有限公司 | A kind of control method and device of I2C communications |
| CN110061732A (en) * | 2019-04-25 | 2019-07-26 | 东莞铭普光磁股份有限公司 | Support the level shifting circuit and level conversion method of SPI communication |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
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| CN2532534Y (en) * | 2002-01-31 | 2003-01-22 | 张其善 | Desk type multi-function universal electronic business process machine |
| CN1983222A (en) * | 2005-12-17 | 2007-06-20 | 鸿富锦精密工业（深圳）有限公司 | SPI apparatus telecommunication circuit |
| US20110106979A1 (en) * | 2009-11-05 | 2011-05-05 | Electronics And Telecommunications Research Institute | Data communication system |
| CN105182154A (en) * | 2015-08-25 | 2015-12-23 | 广东欧珀移动通信有限公司 | Universal serial bus interface detection circuit and method |
| CN106569973A (en) * | 2016-10-25 | 2017-04-19 | 深圳市科陆精密仪器有限公司 | Serial peripheral interface multiplexing method and communication system |
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- 2017-08-01 CN CN201710645572.9A patent/CN107480090B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2532534Y (en) * | 2002-01-31 | 2003-01-22 | 张其善 | Desk type multi-function universal electronic business process machine |
| CN1983222A (en) * | 2005-12-17 | 2007-06-20 | 鸿富锦精密工业（深圳）有限公司 | SPI apparatus telecommunication circuit |
| US20110106979A1 (en) * | 2009-11-05 | 2011-05-05 | Electronics And Telecommunications Research Institute | Data communication system |
| CN105182154A (en) * | 2015-08-25 | 2015-12-23 | 广东欧珀移动通信有限公司 | Universal serial bus interface detection circuit and method |
| CN106569973A (en) * | 2016-10-25 | 2017-04-19 | 深圳市科陆精密仪器有限公司 | Serial peripheral interface multiplexing method and communication system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108763139A (en) * | 2018-04-20 | 2018-11-06 | 青岛海信电器股份有限公司 | A kind of control method and device of I2C communications |
| CN110061732A (en) * | 2019-04-25 | 2019-07-26 | 东莞铭普光磁股份有限公司 | Support the level shifting circuit and level conversion method of SPI communication |
| CN110061732B (en) * | 2019-04-25 | 2023-05-26 | 东莞铭普光磁股份有限公司 | Level conversion circuit and level conversion method supporting SPI communication |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
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| Publication number | Publication date |
|---|---|
| CN107480090B (en) | 2020-08-04 |
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