CN220605897U

CN220605897U - Equipment start-up and reset time sequence circuit based on passive device

Info

Publication number: CN220605897U
Application number: CN202322284349.XU
Authority: CN
Inventors: 张林兵; 徐武剑; 罗玲
Original assignee: Wuhan Mobile Star Technology Co ltd
Current assignee: Wuhan Mobile Star Technology Co ltd
Priority date: 2023-08-23
Filing date: 2023-08-23
Publication date: 2024-03-15
Anticipated expiration: 2033-08-23

Abstract

The utility model relates to a device starting and resetting time sequence circuit based on a passive device, which comprises a plurality of resetting module circuits which are sequentially cascaded, wherein the power input end of each resetting module circuit is connected with the working power supply of a corresponding controller of a first-stage resetting module circuit; the reset module circuit is provided with a signal input end and two signal output ends, wherein the signal input end is used for inputting a reset control signal, one signal output end is used for outputting the reset signal according to the input reset control signal, and the other signal output end is connected with the signal input end of the next-stage reset module circuit and used for outputting the reset control signal to the next-stage reset module circuit according to the input reset control signal; the signal input end of the first-stage reset module circuit is also connected with a reset switch in series and then grounded. The circuit of the utility model meets the time sequence requirement in the starting or resetting process of industrial communication equipment and has the advantages of low cost, stability, reliability, high integration level and the like.

Description

Equipment start-up and reset time sequence circuit based on passive device

Technical Field

The utility model relates to the technical field of circuit design, in particular to a device starting and resetting time sequence circuit based on a passive device.

Background

A conventional reset circuit is shown in fig. 1, which does not distinguish the reset timing. The industrial communication equipment consists of MCU, ECU and other active microelectronic devices in different forms. With the continuous development of new microelectronic devices and the increasing abundance of integrated functions, peripheral circuits such as starting, resetting, power supply and distribution, which are required to be matched by the microelectronic devices, are increasingly diversified and complicated. The core of the design of the peripheral circuit for starting and resetting is to design a time sequence circuit which simultaneously meets the requirements of pulse width, level, time delay, slope and the like of various devices.

The current common sequential circuit design method uses programmable active devices such as CPLD, FPGA and the like to realize the sequential circuit, and the method can realize complex sequential logic and flexible and various sequential design software, but has obvious congenital defects: the power supply is additionally provided, so that the complexity of the system is increased, and additional power consumption is brought; the resources of the programmable active device are generally rich, the resource cost of time sequence design is extremely low, and the design cost and the resource utilization rate are not reduced; the same CPLD active device can only provide one level of time sequence signal, and for the equipment of the multi-level device, a plurality of CPLD time sequence circuits are required to be constructed, and the circuit structure is complex. Therefore, in order to overcome the problem of the controller reset time sequence of the multi-controller system, a simpler and flexible reset time sequence circuit needs to be studied.

Disclosure of Invention

Based on the expression, the utility model provides a device starting and resetting time sequence circuit based on a passive device, which meets the time sequence requirement in the starting or resetting process of industrial communication devices through a simpler circuit structure.

The technical scheme for solving the technical problems is as follows: the device starting and resetting time sequence circuit based on the passive device comprises a plurality of resetting module circuits which are sequentially cascaded, wherein the power input end of each resetting module circuit is connected with the working power supply of the corresponding controller of the first-stage resetting module circuit; the reset module circuit is provided with a signal input end and two signal output ends, wherein the signal input end is used for inputting a reset control signal, one signal output end is used for outputting the reset signal according to the input reset control signal, and the other signal output end is connected with the signal input end of the next-stage reset module circuit and used for outputting the reset control signal to the next-stage reset module circuit according to the input reset control signal; the signal input end of the first-stage reset module circuit is also connected with a reset switch in series and then grounded.

Compared with the prior art, the technical scheme of the application has the following beneficial technical effects: the reset time sequence circuit provided by the utility model sequentially resets the controllers through the plurality of reset module circuits which are sequentially cascaded, and can well meet the time sequence requirements in the starting or resetting process of industrial communication equipment.

On the basis of the technical scheme, the utility model can be improved as follows.

Further, the reset module circuit comprises a reset chip, a first pull-up resistor, a current limiting resistor and a reset driving circuit, wherein the positive electrode of the power input end of the reset chip is connected with the working power supply of the corresponding controller of the reset module circuit, the grounding end of the reset chip is grounded, the signal input end of the reset chip is connected with the working power supply of the corresponding controller of the current reset module circuit after being connected with the first pull-up resistor in series, one signal output end of the reset chip is connected with the signal input end of the reset chip in the next-stage reset module circuit and is used for outputting a reset control signal consistent with the current reset module circuit to the next-stage reset module circuit, and the other signal output end of the reset chip is connected with the control end of the reset driving circuit after being connected with the current limiting resistor in series and is used for controlling the reset driving circuit to output an effective reset signal; the reset driving circuit is powered by a reset power supply of the controller corresponding to the current reset module circuit.

The first-stage reset module circuit further comprises a reset switch, and the signal input end of the reset chip in the first-stage reset module circuit is connected with the reset switch in series and then grounded.

After the technical scheme is adopted, the beneficial effects are as follows: when needing to reset, the reset switch in the first-stage reset module circuit is pressed down, the level of the signal input end of the reset chip is pulled down, and as the signal input end is effective in low level, the reset of the controller corresponding to the first-stage reset module circuit can be started by pressing the reset switch; because of the cascade connection between the adjacent reset module circuits, each controller in the system is reset according to the cascade sequence of the reset module circuits. The time sequence circuit is different from common CPLD, FPGA and other active device time sequence circuits, most of the time sequence circuits adopt passive device designs such as resistors, capacitors, inductors and the like, the circuit structure is simpler, and the time sequence requirements in the starting or resetting process of industrial communication equipment can be well met.

The first reset driving circuit is powered by the reset power supply of the controller corresponding to the current reset module circuit, so that the microcontrollers with different power supplies can be reset.

Further, the reset driving circuit comprises a second pull-up resistor and a controllable switch, wherein the current input end of the controllable switch is connected with a reset power supply of the corresponding controller of the reset module circuit after being connected with the second pull-up resistor in series, and the current output end of the controllable switch is grounded; the control end of the controllable switch is connected with the signal output end of the reset chip after being connected with the current limiting resistor in series; the current input end of the controllable switch is used as a reset signal output end, and the reset signal is effective in low level.

After the technical scheme is adopted, the beneficial effects are as follows: the first reset driving circuit is powered by a controller reset power supply corresponding to the current reset module circuit, and the microcontrollers with different power supplies can be reset through the cascade connection relationship among the reset module circuits. The reset control signal output by the reset chip controls the opening and closing of the controllable switch, so that the current input end of the controllable switch is controlled to output an effective reset signal.

As an embodiment parallel to the above embodiment of the reset driving circuit, optionally, the reset driving circuit includes a pull-down resistor and a controllable switch, a current input end of the controllable switch is connected to a reset power supply of a corresponding controller of the reset module circuit, and a current output end of the controllable switch is connected in series with the pull-down resistor and then grounded; the control end of the controllable switch is connected with the signal output end of the reset chip after being connected with the current limiting resistor in series; the current output end of the controllable switch is used as a reset signal output end, and the reset signal is high-level effective.

After the technical scheme is adopted, the beneficial effects are as follows: the operation principle in this embodiment is the same as that in the above embodiment, and the difference is mainly that the reset signal is active high in this embodiment.

Further, the reset module circuit further comprises a filter capacitor, one end of the filter capacitor is connected with a working power supply of the reset module circuit corresponding to the controller, and the other end of the filter capacitor is grounded and used for filtering high-frequency components in the power supply.

Optionally, the reset chip model is EM6325.

Drawings

FIG. 1 is a schematic diagram of a conventional reset circuit;

fig. 2 is a schematic diagram of an industrial ethernet reset circuit with time-sharing power-up and multi-stage reset functions according to an embodiment. (MPU, SWITCH are both low reset)

Fig. 3 is a schematic diagram of an industrial ethernet reset circuit with time-sharing power-up and multi-stage reset functions according to another embodiment. (MPU, SWITCH both high reset)

Fig. 4 is a schematic diagram of an industrial ethernet reset circuit with time-sharing power-up and multi-stage reset functions according to another embodiment. (MPU reset high level and SWITCH reset low level)

Fig. 5 is a schematic diagram of an industrial ethernet reset circuit with time-sharing power-up and multi-stage reset functions according to still another embodiment. (MPU reset to Low level and SWITCH reset to high level)

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. In the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", and the like, if the connected circuits, modules, units, and the like have electrical or data transferred therebetween.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

The following describes in detail the specific embodiments of the reset circuit of the industrial ethernet switch with the functions of time-sharing power-up and multi-stage reset according to the present utility model with reference to the accompanying drawings.

Taking a common card rail type industrial Ethernet SWITCH as an example, a circuit board of the common card rail type industrial Ethernet SWITCH is generally divided into two parts, one part is a SWITCH circuit board responsible for communication, the other part is an MPU circuit board controlling the operation of the SWITCH, and the two controllers generally have different power supply sources, so that the reset level is different, and the communication rate is very high and can reach 1Gb/S, so that the interference is serious compared with the MPU circuit board.

Fig. 2 is a schematic diagram of the circuit structure of the present utility model using the reset chip EM6325. The model of the reset chips U1 and U2 is EM6325, the reset chips are packaged into SOT23-5, the size is small, the reset chips are very suitable for circuit application with high integration level, the reset chips have the functions of manual reset, high-low level reset, power supply monitoring and the like, and the microcontroller application with different power supplies and reset levels can be met.

As shown in fig. 2, the controller designed in this embodiment is an MPU and a SWITCH, the working power supply of the MPU is vcc_mpu, the corresponding RESET power supply is vcc_mpu_reset, the working power supply of the SWITCH is vcc_switch, and the corresponding RESET power supply is vcc_switch_reset. Because the SWITCH receives the control of the MPU, the working power supplies of the two reset module circuits adopt VCC_MPU.

As shown in fig. 2, the circuit configuration of the present embodiment is as follows.

The first-stage RESET module circuit is an MPU RESET circuit and comprises a RESET chip U1, a first pull-up resistor R1, a current limiting resistor R3, a RESET switch S1 and a RESET driving circuit, wherein the positive electrode VDD of the power supply input end of the RESET chip U1 is connected with the working power supply VCC_MPU of the controller MPU, the grounding end GND of the RESET chip U1 is grounded, the signal input end MRB (low level effective) of the RESET chip U1 is connected with the working power supply VCC_MPU of the controller MPU after being connected with the first pull-up resistor R1 in series, one signal output end RESETB (low level effective) of the RESET chip U1 is used for being connected with the signal input end MRB of the RESET chip U2 in the second-stage RESET module circuit and outputting a RESET control signal consistent with the current RESET module circuit, and the other signal output end RESET (high level effective) of the RESET chip U1 is connected with the control end of the RESET driving circuit after being connected with the current limiting resistor R3 in series and used for controlling the RESET driving circuit to output an effective RESET signal; the signal input end MRB of the reset chip U1 in the first-stage reset module circuit is connected with the reset switch S1 in series and then grounded.

The RESET driving circuit of the first-stage RESET module circuit comprises a second pull-up resistor R4 and a controllable switch Q1 (a triode which can work in a saturated state can be adopted), wherein the current input end of the controllable switch Q1 is connected with a RESET power supply VCC_MPU_RESET of the controller MPU after being connected with the second pull-up resistor R4 in series, and the current output end of the controllable switch Q1 is grounded; the control end of the controllable switch Q1 is connected with a current limiting resistor R3 in series and then is connected with a signal output end RESET of a RESET chip U1; the current input end of the controllable switch Q1 is used as a reset signal output end of the controller MPU, and the reset signal is effective at low level.

The second-stage RESET module circuit is a SWITCH RESET circuit and comprises a RESET chip U2, a first pull-up resistor R2, a current-limiting resistor R5 and a second RESET driving circuit, wherein the positive electrode VDD of the power supply input end of the RESET chip U2 is connected with the working power supply of the controller MPU, the grounding end GND of the RESET chip U2 is grounded, the signal input end MRB of the RESET chip U2 is connected with the working power supply of the controller MPU after being connected with the first pull-up resistor R2 in series, one signal output end RESETB (low level effective) of the RESET chip U1 is used for being connected with the signal input end MRB of the RESET chip in the next-stage RESET module circuit and is used for outputting a RESET control signal consistent with the first RESET module circuit to the second-stage RESET module circuit, and the other signal output end RESET of the RESET chip U2 is connected with the control end of the second RESET driving circuit after being connected with the current-limiting resistor R3 in series and is used for controlling the second RESET driving circuit to output an effective RESET signal;

similarly, the second RESET driving circuit of the second-stage RESET module circuit comprises a second pull-up resistor R6 and a controllable SWITCH Q2 (a triode working in a saturated state can be adopted), the current input end of the controllable SWITCH Q2 is connected in series with the second pull-up resistor R6 and then is connected with a RESET power supply VCC_SWITCH_RESET of a controller SWITCH, and the current output end of the controllable SWITCH Q2 is grounded; the control end of the controllable switch Q2 is connected with a current limiting resistor R6 in series and then is connected with a signal output end RESET of a RESET chip U2; the current input end of the controllable SWITCH Q2 is used as the reset signal output end of the controller SWITCH, and the reset signal is effective at low level.

The working principle of the embodiment is as follows:

the reset time sequence circuit is connected with two controllers, one is a master controller MPU and the other is a slave controller SWITCH, and the MRB pin of the reset chip U1 inputs a level from high to low at the moment when the control circuit is powered on or the reset SWITCH S1 is pressed down. When the MRB pin of the RESET chip U1 inputs a low level, the RESETB pin of the RESET chip U1 keeps outputting a low level to the MRB pin of the RESET chip U2, and the RESET pin keeps outputting a high level, at this time, the triode Q1 is conducted, and since the RESETB pin of the RESET chip U1 is connected with the MRB pin of the RESET chip U2, the RESET pin of the RESET chip U2 keeps outputting a high level later, the triode Q2 is conducted, and thus the MPU and the SWITCH in the control circuit start resetting successively. When the RESET is completed, the MRB pin of the RESET chip U1 inputs a high level, the RESETB pin of the RESET chip U1 keeps outputting a high level, the RESET pin keeps outputting a low level, the triode Q1 is cut off, meanwhile, the MRB pin of U2 also inputs a high level, the RESET pin of U2 keeps outputting a low level, the triode Q2 is cut off, and the MPU and the SWITCH complete RESET successively. The vcc_mpu is a power supply of the MPU, the vcc_mpu_reset is a power supply of an MPU RESET pin, and the vcc_switch_reset is a power supply of a SWITCH RESET pin (because of the continuous development of the microcontroller technology, the advanced microcontrollers generally have several groups of different power supplies at present, and the IO port power supply of the microcontroller is likely not the same group of power supplies as the RESET port of the microcontroller), so that the microcontrollers with different power supplies can be RESET.

More specifically, the main components of the reset timing circuit in this embodiment are composed of reset chips U1 and U2, a touch reset switch S1, transistors Q1 and Q2, filter capacitors C1 and C2, and resistors R1, R2, R3, R4, R5, and R6. In implementation, the capacitors C1 and C2 are ceramic capacitors, which can filter out high-frequency components in the power supply, the resistors R1 and R2 are pull-up resistors, which can keep the MRB pin in a high level state all the time under the condition of no input signal, so that the reset chips U1 and U2 can not reset without any fault, the microcontroller can be ensured to normally operate, meanwhile, the R1 has a protection function, the ground short circuit of the power supply can be prevented at the moment of closing the S1, the resistors R3 and R5 are limiting resistors, the output currents of the reset chips U1 and U2 can be prevented from being excessively large to damage the triodes Q1 and Q2, the resistors R4 and R6 have two functions, namely, the pull-up function is realized, the reset pin of the microcontroller is kept in a high level state under the condition that the triodes are cut off, the normal operation of the microcontroller is ensured, the protection function is realized, the triodes are prevented from being in a power supply and ground short circuit under the conducting state, and the triodes Q1 and Q2 play the role of an electronic switch, and the reset operation can be performed on the microcontroller during power-up and manual reset.

The Ethernet reset circuit based on the utility model can reset according to the priority of the microcontroller, can reset the microprocessors with different power supply systems, and can reset the microcontrollers with different reset levels, and has the advantages of low cost, stability, reliability, high integration level and the like, and has good popularization value.

In addition, as shown in fig. 3, 4 and 5, the reset circuit can be slightly modified to reset microcontrollers with various reset level requirements, and if more microcontrollers are arranged in the circuit, the circuit can be cascaded backwards, so that the flexibility is high. For example, fig. 3 is a schematic diagram of an industrial ethernet reset circuit with a time-sharing power-up and multi-level reset function (both MPU and SWITCH are high-level reset), fig. 4 is a schematic diagram of an industrial ethernet reset circuit with a time-sharing power-up and multi-level reset function (both MPU are high-level reset and SWITCH are low-level reset), and fig. 5 is a schematic diagram of an industrial ethernet reset circuit with a time-sharing power-up and multi-level reset function (both MPU are low-level reset and SWITCH are high-level reset).

When the high level reset shown in fig. 2 is changed to the low level reset, the positions of the resistors R4 and R6 can be changed to switch from the pull-up resistor to the pull-down resistor. Taking fig. 3 as an example distance for illustration, the reset driving circuit is specifically as follows:

the reset driving circuit comprises a pull-down resistor R4 and a controllable switch Q1, wherein the current input end of the controllable switch Q1 is connected with a reset power supply of a corresponding controller of the reset module circuit, and the current output end of the controllable switch Q1 is connected with the pull-down resistor R4 in series and then grounded; the control end of the controllable switch Q1 is connected with a current limiting resistor R3 in series and then is connected with a signal output end RESET of a RESET chip U1; the current output end of the controllable switch Q1 is used as a reset signal output end, and the reset signal is high-level effective.

By slightly modifying the reset driving circuit, the micro-controller with various reset level requirements can be reset, and if more micro-controllers exist in the circuit, the circuit can be further cascaded by adopting more reset module circuits, so that the flexibility is high.

The Ethernet reset circuit provided by the utility model can reset the micro-processor with different power supply systems according to the priority of the micro-processor, and also can reset the micro-processor with different reset levels, and has the advantages of low cost, stability, reliability, high integration level and the like, and has good popularization value.

The foregoing description of the preferred embodiments of the utility model is not intended to limit the utility model to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the utility model are intended to be included within the scope of the utility model.

Claims

1. The device starting and resetting time sequence circuit based on the passive device is characterized by comprising a plurality of resetting module circuits which are sequentially cascaded, wherein the power input end of each resetting module circuit is connected with the working power supply of the corresponding controller of the first-stage resetting module circuit; the reset module circuit is provided with a signal input end and two signal output ends, wherein the signal input end is used for inputting a reset control signal, one signal output end is used for outputting the reset signal according to the input reset control signal, and the other signal output end is connected with the signal input end of the next-stage reset module circuit and used for outputting the reset control signal to the next-stage reset module circuit according to the input reset control signal; the signal input end of the first-stage reset module circuit is also connected with a reset switch in series and then grounded.

2. The device starting and resetting time sequence circuit based on the passive device as claimed in claim 1, wherein the resetting module circuit comprises a resetting chip, a first pull-up resistor, a current limiting resistor and a resetting driving circuit, wherein the positive electrode of the power input end of the resetting chip is connected with the working power supply of the corresponding controller of the resetting module circuit, the grounding end of the resetting chip is grounded, the signal input end of the resetting chip is connected with the working power supply of the corresponding controller of the current resetting module circuit after being connected with the first pull-up resistor in series, one signal output end of the resetting chip is used for being connected with the signal input end of the resetting chip in the next-stage resetting module circuit, is used for outputting a resetting control signal consistent with the current resetting module circuit to the next-stage resetting module circuit, and the other signal output end of the resetting chip is connected with the control end of the resetting driving circuit after being connected with the current limiting resistor in series, and is used for controlling the resetting driving circuit to output an effective resetting signal;

3. The device starting and resetting time sequence circuit based on the passive device as claimed in claim 2, wherein the resetting driving circuit comprises a second pull-up resistor and a controllable switch, the current input end of the controllable switch is connected with the resetting power supply of the corresponding controller of the resetting module circuit after being connected with the second pull-up resistor in series, and the current output end of the controllable switch is grounded; the control end of the controllable switch is connected with the signal output end of the reset chip after being connected with the current limiting resistor in series; the current input end of the controllable switch is used as a reset signal output end, and the reset signal is effective in low level.

4. The device starting and resetting time sequence circuit based on the passive device as claimed in claim 2, wherein the resetting driving circuit comprises a pull-down resistor and a controllable switch, the current input end of the controllable switch is connected with a resetting power supply of the corresponding controller of the resetting module circuit, and the current output end of the controllable switch is connected with the pull-down resistor in series and then grounded; the control end of the controllable switch is connected with the signal output end of the reset chip after being connected with the current limiting resistor in series; the current output end of the controllable switch is used as a reset signal output end, and the reset signal is high-level effective.

5. The device start-up and reset timing circuit based on a passive device according to any one of claims 2 to 4, wherein the reset module circuit further comprises a filter capacitor, one end of the filter capacitor is connected to a working power supply of the reset module circuit corresponding to the controller, and the other end of the filter capacitor is grounded and used for filtering out high-frequency components in the power supply.

6. The passive device based equipment start-up and reset timing circuit of claim 2, wherein the reset chip model is EM6325.