CN108445800B - A digital PCU power system - Google Patents

Abstract

The invention discloses an digital PCU power supply system which comprises at least three FPGA controllers working independently, wherein any FPGA controllers are mainboard FPGA control units, any FPGA controllers in the other two FPGA controllers are used as slave board shunt FPGA controllers, another FPGA controllers are used as slave board charge and discharge FPGA controllers, and the mainboard FPGA control units, the slave board shunt FPGA controllers and the slave board charge and discharge FPGA controllers are respectively connected with an internal data bus SPI through SPI communication modules arranged on the mainboard FPGA control units, the slave board shunt FPGA controllers and the slave board charge and discharge FPGA controllers, so that data interaction is directly carried out among the mainboard FPGA control units, the slave board shunt FPGA controllers and the slave board charge and discharge FPGA controllers.

Description

A digital PCU power system

technical field

The invention relates to the technical field of satellite power supply controllers, in particular to a digital PCU power supply system.

Background technique

Power system is an important part of power management in satellite system. High frequency, high efficiency, low voltage and standardization are the main development trends of switching power supply.

In the field of aerospace industry, the improvement of power system plays a crucial role in improving the performance of spacecraft and prolonging its working life. With the optimization of spacecraft performance, the diversification of orbital operations and the expansion of loads, higher requirements are put forward for the management configuration, fault detection and protection of the spacecraft power system. The power supply system not only needs to meet the output voltage of different levels, but also requires the output voltage to be adjustable within a certain range, and has complex protection and management logic.

At present, the power devices used in the power supply system are more expensive, and their control circuits are more complicated. In addition, the power load is generally a large number of highly integrated devices, and these devices generally withstand electricity, heat, and shock. poor.

Because the protection of the power system should take into account the safety of itself and the load. Therefore, in the prior art, the above purpose is achieved by adding a protection circuit in the power supply system, but this will inevitably lead to the increase of electronic devices in the power supply system, and the added electronic devices will affect the reliability of the power supply system. sex. The current analog power controller is difficult to meet the changes in the application requirements of the load, resulting in a large and complex power system or a long custom production cycle.

The system control architecture used in the aerospace power system field today is an integrated architecture of "analog control + digital management". A large number of discrete devices are used for parameter setting, and the conversion of wide voltage range input cannot be taken into account at the same time. Change the above parameter settings.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a digital PCU power supply system, which adopts the three-domain control framework mode of "main board + slave board": the main board and the slave board are both independent working units, and the master and slave boards have their own FPGA chips respectively. Perform its duties; the slave board is controlled by the main board, and the slave board feeds back the working status data to the main board, so as to achieve the full-line control of the main board to the slave board. Therefore, the digital PCU power supply system can be configured with the characteristics of programmable output, good dynamic response and high control accuracy, and intelligent control of power management independently.

In order to achieve the above object, the present invention is realized through the following technical solutions:

A digital PCU power supply system, comprising: at least three FPGA controllers working independently, wherein any one of the FPGA controllers is a motherboard FPGA control unit; among the remaining two FPGA controllers, any one of the FPGA controllers As the shunting FPGA controller from the board, another described FPGA controller serves as the FPGA controller for charging and discharging from the board; the main board FPGA control unit, the shunting FPGA controller from the board and the FPGA controller for charging and discharging from the board are respectively provided with The SPI communication module is connected with the internal data bus SPI, so that data interaction is directly performed between the main board FPGA control unit, the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller.

Preferably, the mainboard FPGA control unit collects the bus voltage, and compares the bus voltage with the preset bus voltage to output the MEA signal; the mainboard FPGA control unit collects the voltage and current of the battery, and compares the voltage and current of the battery with the preset voltage and current. The voltage and current of the battery are compared to output the BEA signal; the sub-board shunt FPGA controller receives the MEA signal, compares it with the preset working range, judges the working mode of the power supply system, and according to the working mode Decide whether to perform a shunt operation. The sub-board shunt FPGA controller receives the MEA signal, compares it with a preset working range, determines the working mode in which the power supply system is located, and decides whether to perform the shunt operation according to the working mode.

The slave board charge and discharge FPGA controller receives the MEA and BEA signals, compares the MEA signal with a preset working range, determines the working mode of the power supply system, and determines the working mode according to the working mode and the The BEA signal determines whether to charge or discharge the battery.

Preferably, the mainboard FPGA control unit includes: an ADC interface program control module, a MEA controller, a BEA controller, a system timing control module, a fault monitoring and processing protection module, and an SPI communication module.

Preferably, the mainboard FPGA control unit is provided with an external communication interface, which is connected to a host computer located outside the digital PCU power supply system, and the host computer is used to configure the mainboard FPGA control unit with the host computer through the external communication interface. The controller parameters that match the digital PCU power system described above.

Preferably, the slave board charging and discharging FPGA controller includes: a BCR charging module, a BDR discharging module, a system timing control module, and a fault and state monitoring module; the BCR charging module and the BDR discharging module respectively communicate with the user through the PWM modulation interface module. It is connected to the BCDR driver that drives the BCR charging module and the BDR discharging module to work.

Preferably, the sub-board shunt FPGA controller includes: a system timing control module, an SR control unit, and an SR four-stage frequency-limited and current-shunt control module, and the SR four-stage frequency-limited and current-shunt control module is grounded.

Preferably, the working mode includes: a three-domain working mode of a charging domain, a discharging domain and a shunt domain; a hysteresis region is provided between the charging domain and the discharging domain, and at this time, the slave board shunts the FPGA controller and the slave board The working state of the charge and discharge FPGA controller remains unchanged.

Preferably, the SR four-stage frequency limiting current shunt control module includes four shunts, and the SR four-stage frequency limiting current shunt control module is used to limit the switching frequency of each of the shunts and the opening and closing of switches.

Compared with the prior art, the present invention has the following advantages:

The FPGA provided in the present invention is a power system control chip, which realizes digital PCU power system management, multi-channel control loop algorithm and pulse width modulation (PWM) multi-channel drive output by means of programmable control.

The present invention is also provided with an internal data SPI bus, which is used for direct data interaction between the main board FPGA control unit, the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller, thereby realizing the integrated management of the digital PCU power supply system. and control.

The main board FPGA control unit is responsible for the control and scheduling of the entire digital PCU power supply system, collecting the bus voltage and battery voltage and current of the entire digital PCU power supply system; responsible for the generation and distribution of MEA and BEA signals. The digital PCU power supply system adopts a unified MEA and BEA control. The Slave Board Shunt (SR) FPGA controller and the Slave Board Charge and Discharge (BCDR) FPGA controller respectively implement charge and discharge loop control and shunt loop control, and are integrated in each sub-function module, responsible for the control, detection and control of the function module. protection, etc. The digital PCU power supply system of the present invention can be decomposed into modular function control units, which can realize the universal design of each function module.

The digital PCU power supply system proposed by the invention has high reliability and good portability, and can be adapted to power supply systems of different power levels.

Description of drawings

Fig. 1 is a kind of digital PCU power supply system framework block diagram of the present invention;

2 is a schematic diagram of a three-domain control mode of a digital PCU power supply system of the present invention;

3 is a schematic diagram of the main structure of the FPGA control unit of a digital PCU power supply system of the present invention;

4 is a schematic structural diagram of the main components of a slave-board charge and discharge FPGA controller of a digital PCU power supply system of the present invention;

5 is a schematic structural diagram of the main components of a sub-board shunt FPGA controller of a digital PCU power supply system of the present invention;

6 is a schematic diagram of a digital PCU power supply system of the present invention that enables communication between the FPGA control unit, the slave board charge and discharge FPGA controller, and the slave board shunt FPGA controller through the SPI internal bus.

Detailed ways

The present invention will be further elaborated below by describing a preferred specific embodiment in detail with reference to the accompanying drawings.

As shown in FIG. 1 , a digital PCU power supply system of the present invention includes: at least three FPGA controllers, any one of which is a mainboard FPGA control unit, which is connected to a host computer. Among the other two FPGA controllers, one is used as the shunt FPGA controller from the board, and the other is used as the FPGA controller for charging and discharging from the board. The main board FPGA control unit, the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller perform data interaction through the internal data bus SPI.

The mainboard FPGA control unit is responsible for the control and scheduling of the whole machine, is responsible for the bus voltage acquisition, battery voltage and current acquisition of the entire digital PCU power system, and generates MEA and BEA signals according to the above bus voltage and battery voltage and current to the slave board. Shunt the FPGA controller and charge and discharge the FPGA controller output from the board. The sub-board shunt FPGA controller and the sub-board charging and discharging FPGA controller are used to perform power conversion on the digital PCU power system according to the received MEA and BEA signals.

In this embodiment, power is supplied to the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller through the solar array, the slave board charge and discharge FPGA controller is also connected to the battery, and the slave board charge and discharge FPGA control The output of the device is the bus.

As shown in Figure 3, the mainboard FPGA control unit further comprises: ADC module or ADC interface program control module, MEA controller, BEA controller, for controlling the mainboard FPGA control unit, shunt FPGA controller from the board and slave The system timing control module, fault monitoring and processing protection module, SPI communication module and external communication interface for the synchronous operation of the board charge and discharge FPGA controller.

The ADC module is used to collect the bus voltage and battery voltage and current of the entire digital PCU power system. The MEA controller and the BEA controller are respectively connected to the ADC module. The MEA controller is based on the collected bus voltage and preset values. A difference operation is performed on a predetermined predetermined voltage, and the result of the operation is amplified to obtain the MEA signal. The BEA controller performs a difference operation according to the collected battery current or voltage and a preset predetermined current or voltage, and amplifies the operation result to obtain a BEA signal. The MEA controller outputs the MEA signal to the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller respectively. The BEA controller outputs the BEA signal to the slave board charge and discharge FPGA controller. Thereby, the signal reference of charging and discharging is provided for the charge and discharge FPGA controller of the slave board, and the working mode reference is provided for the shunt FPGA controller of the slave board. The mainboard FPGA control unit is connected with the upper computer through the external communication interface.

The prominent feature of the digital PCU power supply system is that the control parameters are programmable. The programmable output of the power stage parameters of the power supply system is a huge advantage of the digital PCU power supply system. The external communication interface is the controller parameter configuration interface, which is used for external configuration through the host computer. The corresponding controller parameters maximize the configurability and high adaptability of the control system of the digital PCU power system.

As shown in FIG. 4 , the slave board charge and discharge FPGA controller is used to realize the charge and discharge function of the digital PCU power supply system, which further includes: an SPI communication module, a BCR charging module with a PWM modulation interface module, and a PWM modulation interface The module's BDR discharge module, system timing control module and fault and status monitoring module. After receiving the above-mentioned MEA and BEA signals, the slave board charge and discharge FPGA controller judges the signals, and obtains the current working mode of the system according to the MEA signal. Then the BEA signal is used to control the BCR charging module or the BDR discharging module to charge or discharge the battery according to the working mode of the battery system.

As shown in FIG. 5 , the sub-board shunt FPGA controller has an SR four-level shunt function, which further includes: an SPI communication module, a system timing control module, an SR control unit, and an SR four-level limiter using "bang-bang control" Frequency shunt control module. The SR four-stage frequency limiting current shunt control module is grounded. After receiving the above-mentioned MEA signal, the sub-board shunt FPGA controller and the sub-board charging and discharging FPGA controller judge the signal, and decide whether to perform shunt work according to the judgment result.

In this embodiment, as shown in FIG. 2 , the three-domain control framework mode of the present invention includes: a charging domain, a discharging domain, and a three-domain working mode of a current-shunt domain.

When the MEA signal is in the bus voltage range of 29.3V to 29.8V, the battery system operating mode is the shunt domain; at this time, the SR four-stage frequency-limited shunt control module of the slave-board shunt FPGA controller performs a shunt operation, The SR four-stage frequency limiting shunt control module controls the four shunts to perform the ground shunt operation. When the solar array power generation capacity is the highest, it can control all the four shunts to open the ground shunt. When it is not the highest, according to the current For diversion requirements, any one or two or three diverters of the four diverters can be controlled to perform ground diversion work. The slave board charge and discharge FPGA controller obtains according to the MEA signal that the working mode of the battery system is the shunt domain. At this time, the slave board charge and discharge FPGA controller controls the BCR charging module to charge the battery through the received BEA signal. .

When the MEA signal is in the bus voltage range of 29.2V to 29.3V, the battery system operating mode is the second hysteresis zone 2; at this time, the SR four-stage frequency limiting current shunt control module of the slave board shunt FPGA controller continues When the diversion operation is performed, at this time, the power generation capacity of the solar array is reduced. According to the current diversion demand, any one or two or three diverters in the four diverters can be controlled to perform the diversion work to the ground. The slave board charge and discharge FPGA controller obtains that the battery system operating mode is the second hysteresis zone 2 according to the MEA signal. At this time, the slave board charge and discharge FPGA controller continues to control the BCR charging module pair through the received BEA signal. The battery is charged.

When the MEA signal is 29.2V, the slave board charge and discharge FPGA controller controls the BCR charging module to reduce the charging current of the battery through the received BEA signal.

When the MEA signal is in the bus voltage range of 28.9V to 29.8V, the battery system operating mode is the charging domain.

When the MEA signal is in the bus voltage range of 28.8V to 28.9V, the battery system operating mode is the first hysteresis zone 1; at this time, the SR four-stage frequency limiting current shunt control module of the slave board shunt FPGA controller continues When the diversion operation is performed, at this time, the power generation capacity of the solar array continues to decrease. According to the current diversion demand, any one or two or three diverters among the four diverters can be controlled to perform the diversion work to the ground. The slave board charge and discharge FPGA controller obtains according to the MEA signal that the operating mode of the battery system is the first hysteresis zone 1. At this time, the slave board charge and discharge FPGA controller continues to control the BCR charging module pair through the received BEA signal. The battery performs an operation to reduce the charging current.

When the MEA signal is in the bus voltage range of 28.2V to 28.8V, the battery system operating mode is the discharge domain. At this time, the SR four-stage frequency limiting current-shunt control module of the slave-board shunt FPGA controller continues to stop performing the shunt operation. The slave board charge and discharge FPGA controller obtains according to the MEA signal that the working mode of the battery system is the discharge domain. At this time, the slave board charge and discharge FPGA controller continues to control the BDR discharge module through the received BEA signal to discharge the battery operate.

To sum up, the sub-board shunting FPGA controller and the sub-board charging and discharging FPGA controller respectively receive the MEA\BEA signal and the voltage and current signals provided by the mainboard FPGA control unit, and work through the three domains of the charging domain, the discharging domain and the diverting domain. After the mode is judged, it will enter the corresponding working mode to work. Ensure that the overall normal operation of the digital PCU power supply system.

The mainboard FPGA control unit is responsible for the control and scheduling of the above-mentioned power supply system, and performs full-line control of the slave board shunt FPGA controller and the slave board charge and discharge FPGA controller, so as to realize the integrated control and management of the digital PCU power supply system. The sub-board shunting FPGA controller and the sub-board charging and discharging FPGA controller respectively perform work judgment according to the range of the MEA signal sent by the main board combined with the set working range, and work in the three domains. In order to prevent the PCU from constantly beating back and forth in the adjacent working domains due to the disturbance of the MEA signal, which reduces the stability and reliability of the entire system, we introduce a hysteresis zone between the two adjacent domains to reduce interference, etc. The impact of other unstable factors on system performance.

In this embodiment, the above-mentioned shunting FPGA controller from the board adopts the hysteresis switch control method. Mainly according to the range of the MEA signal, the upper and lower limit digital comparators are set for the control of each channel to form a bang-bang control form. The limit value and the lower limit value correspond to the turn-on and turn-off of the power shunt open tube respectively, and its switching frequency varies with the power supply state. Compared with the pulse width modulation circuit, it has the advantages of less electronic components and simple circuit.

The SR four-stage frequency-limiting current-shunt control module of the FPGA controller that shunts from the board is used to limit the switching frequency to reduce the above effect and enhance the reliability of the system. The switching frequency is limited. When the hysteresis loop width is improperly set or the MEA signal fluctuation frequency and amplitude are high, the shunt switching frequency will be too high, which will easily damage the electronic power switching devices and cause large system heat consumption.

As shown in Figure 6, the digital PCU power supply system adopts the architecture mode of "main board + slave board". The internal data bus is an indispensable part of loop control, and the real-time requirements for data transmission are relatively high. The internal data bus SPI is a high-speed, full-duplex, synchronous communication bus, and it only occupies four lines on the pins of the chip, which saves the pins of the chip and saves space for the layout of the PCB. The main features of the internal data bus SPI are: can send and receive serial data at the same time; the clock frequency is programmable; send end, interrupt flag; its transmission rate can reach tens of megahertz, which can effectively reduce the communication delay and improve the response speed of the control loop . In addition, in terms of software implementation, the SPI bus program is simple and easy to implement, which reduces the workload and debugging time of engineers, and has high engineering application value.

While the content of the present invention has been described in detail by way of the above preferred embodiments, it should be appreciated that the above description should not be construed as limiting the present invention. Various modifications and alternatives to the present invention will be apparent to those skilled in the art upon reading the foregoing. Accordingly, the scope of protection of the present invention should be defined by the appended claims.

Claims (6)

1. The digital PCU power supply system is characterized by comprising at least three independently working FPGA controllers, wherein FPGA controllers are mainboard FPGA control units, and of the rest two FPGA controllers, FPGA controllers are slave board shunt FPGA controllers and FPGA controllers are slave board charge and discharge FPGA controllers;

   the main board FPGA control unit acquires bus voltage and compares the bus voltage with preset bus voltage to output an MEA signal; the main board FPGA control unit collects the voltage and current of the storage battery and compares the voltage and current of the storage battery with the voltage and current of a preset storage battery to output a BEA signal; the slave board shunting FPGA controller receives the MEA signal, compares the MEA signal with a preset working range, judges the working mode of the power supply system, and determines whether to carry out shunting operation according to the working mode;

   the slave plate charge-discharge FPGA controller receives the MEA and BEA signals, compares the MEA signals with a preset working range, judges the working mode of the power supply system, and determines to charge or discharge a storage battery according to the working mode and the BEA signals;

   the working modes comprise: a charging domain, a discharging domain and a shunting domain work modes; and a hysteresis region is arranged between the charging domain and the discharging domain, and at the moment, the working states of the slave plate shunt FPGA controller and the slave plate charging and discharging FPGA controller are kept unchanged.
2. 2. The digital PCU power supply system according to claim 1,

   the mainboard FPGA control unit comprises: the system comprises an ADC interface program control module, an MEA controller, a BEA controller, a system time sequence control module, a fault monitoring and processing protection module and an SPI communication module.
3. 3. Digital PCU power supply system according to claim 1 or 2,

   the main board FPGA control unit is provided with an external communication interface and is connected with an upper computer positioned outside the digital PCU power supply system, and the upper computer is used for configuring controller parameters matched with the digital PCU power supply system for the main board FPGA control unit through the external communication interface.
4. 4. The digital PCU power supply system according to claim 1,

   the slave plate charging and discharging FPGA controller comprises: the system comprises a BCR charging module, a BDR discharging module, a system time sequence control module and a fault and state monitoring module; the BCR charging module and the BDR discharging module are respectively connected with a BCDR driver used for driving the BCR charging module and the BDR discharging module to work through the PWM modulation interface module.
5. 5. The digital PCU power supply system according to claim 1,

   the slave shunting FPGA controller comprises: the system comprises a system time sequence control module, an SR control unit and an SR four-level frequency-limiting flow control module, wherein the SR four-level frequency-limiting flow control module is grounded.
6. 6. The digital PCU power supply system according to claim 5,

   the SR four-stage frequency-limiting flow control module comprises four current dividers, and is used for limiting the switching frequency and the switching of the switches of the current dividers.

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