CN106569973A - Serial peripheral interface multiplexing method and communication system - Google Patents
Serial peripheral interface multiplexing method and communication system Download PDFInfo
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- CN106569973A CN106569973A CN201610938535.2A CN201610938535A CN106569973A CN 106569973 A CN106569973 A CN 106569973A CN 201610938535 A CN201610938535 A CN 201610938535A CN 106569973 A CN106569973 A CN 106569973A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention relates to a serial peripheral interface multiplexing method. The serial peripheral interface multiplexing method is suitable for the occasion that a host with serial peripheral interfaces is connected with more than two peripherals through the serial peripheral interfaces so that data can be transmitted between the host and the peripherals. The serial peripheral interface multiplexing method is characterized by: by means of a PWM (Pulse Width Modulation) output mode of an MCU timer, respectively outputting the waveform of the preset phase difference and the duty ratio within a PWM cycle, wherein the quantity of the preset phase difference and the duty ratio is determined according to the quantity of the connected peripherals; by means of a patch selection signal line, outputting the waveform to enablement pins of the corresponding peripherals; and strobing the corresponding peripherals, and within each peripheral strobing time, performing data transmission between the host and the corresponding peripherals. The serial peripheral interface multiplexing method does not demand participation of MCU software, can realize an application with high speed and multi SPIs through an SPI multiplexing technology which controls patch selection signals through hardware, and provides a solution for realizing multiplexing of SPI when some application occasion cannot control patch selection through software. The invention also relates to a communication system. The communication system can realize data transmission through the SPI multiplexing method.
Description
Technical field
The present invention relates to technical field of data transmission, more particularly to a kind of Serial Peripheral Interface (SPI) multiplexing method and communication system
System.
Background technology
SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) is a kind of synchronous serial Peripheral Interface,
Main frame can be made to be communicated with exchanging information with various ancillary equipment by serial mode.The interface generally uses 4 lines：String
Row clock line (SCLK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and low electricity
Equal effective slave selection line CS.SPI interface is with its superior performance, few holding wire (most 4 lines, minimum 2 lines)
It is widely used in various occasions.In point-to-point communication, SPI interface need not be addressed operation, and logical for full duplex
Letter, it appears simple efficient.In multiple systems from device, each needs independent enable signal, traditional method from device
In, each enable signal from device is controlled by software, it is easy to realize the multiplexing of SPI.But, software controls making for slave
Energy signal realizes that the mode of SPI multiplexings cannot meet demand in some occasions, such as requires to enable slave the control speed of signal
During degree is less than the application of 1uS, just cannot be realized by software control.
The content of the invention
Based on this, it is necessary to cannot select by software control sheet for some application scenarios, the problem of SPI multiplexings is realized,
A kind of Serial Peripheral Interface (SPI) multiplexing method and communication system are provided.
A kind of Serial Peripheral Interface (SPI) multiplexing method, it is adaptable to which the main frame with Serial Peripheral Interface (SPI) passes through Serial Peripheral Interface (SPI)
Connect plural peripheral hardware, with the transmission data between main frame and peripheral hardware, including：
The intervalometer of main frame is set to into pulse width modulation output mode, and the week of pulse width modulating signal is set
Phase；
According to the peripheral hardware quantity of connection, it is determined that the quantity of the pulse width modulating signal of output, each pulse width modulation
The phase contrast of the adjacent pulse width modulating signal of the dutycycle and each two of signal；
The original levels and initial phase of each pulse width modulating signal are set, start the pulse width modulation of intervalometer
Output mode；
Each pulse width modulating signal is exported by chip selection signal line respectively to the enable pin of correspondence peripheral hardware；
According to the original levels and initial phase of each pulse width modulating signal, believe in each pulse width modulation
Number low level time in, the main frame and it is described correspondence peripheral hardware carry out data transmission.
Wherein in one embodiment, the quantity of the pulse width modulating signal is equal to the peripheral hardware quantity of the connection.
Wherein in one embodiment, the dutycycle computing formula of each pulse width modulating signal is
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection.
Wherein in one embodiment, the phase difference calculating formula of the adjacent pulse width modulating signal of each two is
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware number of connection
Amount.
Wherein in one embodiment, the original levels and initial phase of each pulse width modulating signal described in the basis
Position, in the low level time of each pulse width modulating signal, the main frame and the correspondence peripheral hardware carry out data transmission, and wrap
Include：
In the low level time of each pulse width modulating signal, the chip selection signal line of the main frame exports low electricity
Put down to the enable pin of the correspondence peripheral hardware, gate the correspondence peripheral hardware；
In the correspondence peripheral hardware gating time, the main frame and the correspondence peripheral hardware carry out data transmission.
A kind of communication system, including main frame and by Serial Peripheral Interface (SPI) be connected with the main frame it is plural outer
If the main frame includes intervalometer,
The intervalometer is configured to pulse width modulation output mode, exports under the pulse width modulation output mode
The phase place of the adjacent pulse width modulating signal of the quantity of signal, the dutycycle of each pulse width modulating signal and each two
Difference is determined according to the peripheral hardware quantity of connection；
The main frame is configured to for each pulse width modulating signal to export outer to correspondence by chip selection signal line respectively
If enable pin the original levels and initial phase according to each pulse width modulating signal, in each pulse width
In the low level time of modulated signal, carry out data transmission with the corresponding peripheral hardware.
Wherein in one embodiment, the quantity of the pulse width modulating signal of the output is equal to the peripheral hardware of the connection
Quantity.
Wherein in one embodiment, the computing formula of the dutycycle of each pulse width modulating signal is
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection.
Wherein in one embodiment, the phase difference calculating formula of the adjacent pulse width modulating signal of each two is
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware number of connection
Amount.
Above-mentioned Serial Peripheral Interface (SPI) multiplexing method and communication system, by PWM (the Pulse Width of MCU intervalometers
Modulation, pulse width modulation) output mode, export true by connected peripheral hardware quantity respectively in a PWM cycle
The preset phase difference and the waveform of dutycycle of fixed number amount, is exported by chip selection signal line to the enable pin of correspondence peripheral hardware, gating
Corresponding peripheral hardware, in each peripheral hardware gating time, the main frame and the correspondence peripheral hardware carry out data transmission.It is fixed being provided with
When the PWM output modes of device, under PWM mode after the parameter such as phase contrast and dutycycle of waveform, remaining step is all that hardware is automatic
Complete, participate in without the need for MCU softwares.By the SPI multiplex techniques of hardware controls chip selection signal, realize at a high speed, many SPI should
With, be that some application scenarios cannot be selected by software control sheet, realize SPI multiplexing provide solution.
Description of the drawings
Fig. 1 is the multiplexing method flow chart of Serial Peripheral Interface (SPI) in one embodiment；
Fig. 2 is Serial Peripheral Interface (SPI) multiplexing method flow chart in another embodiment；
Fig. 3 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in one embodiment；
Fig. 4 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in another embodiment；
Fig. 5 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in further embodiment；
Fig. 6 is the structural representation of communication system in one embodiment.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is a part of embodiment of the invention, rather than the embodiment of whole.Based on this
Embodiment in bright, the every other enforcement obtained under the premise of creative work is not made by those of ordinary skill in the art
Example, belongs to the scope of protection of the invention.
As shown in figure 1, in one embodiment, there is provided a kind of multiplexing method of Serial Peripheral Interface (SPI), the method include：
Step S100：The intervalometer of main frame is set to into pulse width modulation output mode, and pulse width modulation is set
The cycle of signal.
Wherein, pulse width modulation (Pulse Width Modulation, PWM) is a kind of analog signal level to be carried out
Digitally coded method.Using the equal spike train of each pulse width as PWM waveform, by the cycle for changing spike train
The width or dutycycle that with frequency modulation, can change pulse can make voltage and frequency coordination using suitable control method with pressure regulation
Change.The purpose of control charging current can be reached by the cycle of adjustment PWM, the dutycycle of PWM.
Step S110：According to the peripheral hardware quantity of connection, it is determined that the quantity of the pulse width modulating signal of output, each pulse
The phase contrast of the adjacent pulse width modulating signal of the dutycycle and each two of bandwidth modulation signals.
Wherein, the peripheral hardware quantity according to connection, it is determined that the parameter of corresponding pulse-width-modulated mode, including pulse width
The adjacent pulse width modulation letter of the output quantity of modulated signal, the dutycycle of each pulse width modulating signal and each two
Number phase contrast.The setting of above-mentioned parameter so that pulse width modulating signal is corresponding with the peripheral hardware of connection, and different parameters set
It is fixed, it is possible to achieve different multiplexing effects.
Step S120：The original levels and initial phase of each pulse width modulating signal are set, start the arteries and veins of intervalometer
Rush width modulated output mode.
Wherein, the original levels and initial phase of each pulse width modulating signal determine corresponding peripheral data
The sequencing of transmission, after the completion of above-mentioned parameter is respectively provided with, starts the pulse width modulation output mode of intervalometer, follow-up to walk
Suddenly can be automatically performed by hardware, without the need for the participation of micro-control unit software.
Step S130：Each pulse width modulating signal is exported by chip selection signal line respectively to the enable of correspondence peripheral hardware
Pin.
Wherein, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus system is a kind of synchronous
Serial Peripheral Interface (SPI), it can make MCU be communicated in a serial fashion with exchanging information with various ancillary equipment.The interface is general
Using 4 lines：Serial time clock line (SCLK), main frame input/slave output data line MISO, main frame output/slave input data
Peripheral hardware selection line CS of line MOSI and Low level effective.By peripheral hardware selection line CS, each pulse width modulating signal is distinguished
Export to the enable pin of correspondence peripheral hardware.
Step S140：According to the original levels and initial phase of each pulse width modulating signal, in each pulse
In the low level time of bandwidth modulation signals, the main frame and the correspondence peripheral hardware carry out data transmission.
Wherein, after the enable interface in each peripheral hardware is connected to corresponding peripheral hardware selection line CS of main frame, the peripheral hardware of main frame
Selection line CS output pulse width modulation waveform, the relevant parameter of the waveform is pre-set, according to pulse width modulation
Waveform, in the low level time of each waveform, main frame carries out data exchange with the corresponding peripheral hardware, realizes data transfer.
As shown in Fig. 2 in one embodiment, step S140 includes：
Step S142：In the low level time of each pulse width modulating signal, the chip selection signal of the main frame
Line exports the enable pin of low level to the correspondence peripheral hardware, gates the correspondence peripheral hardware；
Step S144：In the correspondence peripheral hardware gating time, the main frame and the correspondence peripheral hardware carry out data transmission.
Wherein, the enable signal of peripheral hardware is Low level effective, in the low level time of each pulse width modulating signal,
Peripheral hardware corresponding with the pulse-modulated signal is strobed, and now, main frame is carried out data transmission with the peripheral hardware, and lasts till pulse width
Till degree signal is changed into high level.After the pulse width modulating signal is changed into high level, Selection of chiller and another pulse width
Degree modulated signal carries out data transmission for low level peripheral hardware, so as to realize that the data between a main frame and multiple peripheral hardwares are handed over
Change, that is, the multiplexing of SPI.
As shown in figure 3, being waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of intervalometer
The quantity of the pulse width modulating signal of output mode output is equal to the peripheral hardware quantity of connection, now, each pulse width modulation
The dutycycle of signal can be calculated by following formula
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection；Each two pulse
The phase contrast of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware number of connection
Amount.From above-mentioned computing formula：When the quantity of pulse width modulating signal is equal to the peripheral hardware quantity of the connection, at one
In PWM cycle, the data of main frame are divided into into n deciles (n represents peripheral hardware quantity and more than or equal to 2), in the low of each pwm signal
In level time, main frame peripheral hardware corresponding with pwm signal carries out data exchange, n parts data transfer is outer to n so as to realize
If realizing the multiplexing of SPI.
As shown in figure 4, being waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of intervalometer
The quantity of the pulse width modulating signal of output mode output is equal to the peripheral hardware quantity of connection, but dutycycle is less thanNow,
Assume that the dutycycle of each pulse width modulating signal can be calculated by following formula
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection；Each two pulse
The phase contrast of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware number of connection
Amount.From above-mentioned computing formula：When the quantity of pulse width modulating signal is equal to the peripheral hardware quantity of the connection, keep every
The phase contrast of two pulse width modulating signals is constant, and dutycycle is changed intoNow, the transmission of data is changed into discontinuous
, i.e., occur between the adjacent peripheral hardware of each twoThe data-transmission interruptions of individual duty cycle time, if in this break period
Data are invalid data, then the screening of data can be realized by data-transmission interruptions, valid data are transmitted, and invalid number
According to by Transmission, it is not transmitted, so as to realize the maximization of data transmission quality, it is ensured that the data that peripheral hardware is received are equal
For valid data.
As shown in figure 5, being waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of intervalometer
Peripheral hardware quantity of the quantity of the pulse width modulating signal of output mode output more than connection, now, it is assumed that connection peripheral hardware quantity
For n, the quantity of the pulse width modulating signal of output is 2n, then the dutycycle of each pulse width modulating signal can be by following public affairs
Formula is calculated
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection；Each two pulse
The phase contrast of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware number of connection
Amount.From above-mentioned computing formula：As the dutycycle of each pulse width modulating signal is changed intoEach two pulse width
The phase difference variable of modulated signal isNow, the first half of a PWM cycle carries out data transmission, latter half data
Transmission, by the data transfer mode, can be in the biography of two cycle data transfer intermediate formation, 1/2nd PWM cycles
Defeated interruption, it is achieved thereby that the time delay of two cycle intermediate data transmission, likewise, being also capable of achieving the screening of data.
As shown in fig. 6, in one embodiment, there is provided a kind of communication system, the communication system include：Main frame 10 and logical
(quantity of the peripheral hardware is two or more, in the present embodiment to cross the peripheral hardware 20,30 and 40 that Serial Peripheral Interface (SPI) is connected with main frame 10
By taking three peripheral hardwares as an example), main frame 10 includes intervalometer 100,
Intervalometer 100 is configured to pulse width modulation output mode, exports under the pulse width modulation output mode
The phase place of the adjacent pulse width modulating signal of the quantity of signal, the dutycycle of each pulse width modulating signal and each two
Difference is determined according to the peripheral hardware quantity of connection；
Main frame 10 is configured to export to correspondence peripheral hardware each pulse width modulating signal respectively by chip selection signal line
Enable pin the original levels and initial phase according to each pulse width modulating signal, adjust in each pulse width
In the low level time of signal processed, carry out data transmission with the corresponding peripheral hardware.
In one embodiment, the number of the pulse width modulating signal of the pulse width modulation output mode output of intervalometer
Peripheral hardware quantity of the amount equal to connection, now, by formulaWithIt is calculated each pulse width modulation
Dutycycle η of signal is 66.67%；Phase difference φ of each two pulse width modulating signal is 120 °.Therefore, at one
In PWM cycle, the data of main frame are divided into into 3 deciles, it is assumed that corresponding to IO1 PWM output signal original levels be low level,
Initial phase is 0, and data transfer waveform schematic diagram is as shown in Figure 3.1/3rd cycle before PWM cycle, pwm signal gating
Peripheral hardware 20, main frame 10 are carried out data transmission with peripheral hardware 20；In 1/3rd cycle of centre of PWM cycle, pwm signal gating peripheral hardware
30, main frame 10 is carried out data transmission with peripheral hardware 30；In rear 1/3rd cycle of PWM cycle, pwm signal gating peripheral hardware 40 is main
Machine 10 is carried out data transmission with peripheral hardware 40.After a PWM cycle, in the cycle, the data of the transmission of main frame 10 are just respectively allocated to
In three peripheral hardwares 20,30 and 40, so as to the multiplexing of data transfer is realized by SPI interface.Accordingly, scalable dutycycle reaches
To functions such as data screening, transmission delays, concrete grammar is explained in the embodiment of Serial Peripheral Interface (SPI) multiplexing method
State, here is omitted.
Above-mentioned Serial Peripheral Interface (SPI) multiplexing method and communication system, by the PWM output modes of MCU intervalometers, at one
The output preset phase corresponding with peripheral hardware quantity is connected be poor respectively in PWM cycle and the waveform of dutycycle, by chip selection signal
Line is exported to the enable pin of correspondence peripheral hardware, gates corresponding peripheral hardware, in each peripheral hardware gating time, the main frame and described
Correspondence peripheral hardware carries out data transmission.The phase contrast and duty of waveform in the case where the PWM output modes of intervalometer, PWM mode is provided with
Than etc. after parameter, remaining step is all that hardware is automatically performed, and is participated in without the need for MCU softwares.By the SPI of hardware controls chip selection signal
Multiplex technique, realizes high speed, the application of many SPI, is that some application scenarios cannot be selected by software control sheet, realizes SPI's
Multiplexing is there is provided solution.Further, by arranging different dutycycles, it is possible to achieve data screening, data transfer prolong
When etc. function so that the transmission of data is more accurate.
Each technical characteristic of embodiment described above arbitrarily can be combined, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more concrete and detailed, but and
Therefore can not be construed as limiting the scope of the patent.It should be pointed out that for one of ordinary skill in the art comes
Say, without departing from the inventive concept of the premise, some deformations and improvement can also be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be defined by claims.
Claims (9)
1. a kind of Serial Peripheral Interface (SPI) multiplexing method, it is adaptable to which the main frame with Serial Peripheral Interface (SPI) is connected by Serial Peripheral Interface (SPI)
Plural peripheral hardware is connect, with the transmission data between main frame and peripheral hardware, it is characterised in that include：
The intervalometer of main frame is set to into pulse width modulation output mode, and the cycle of pulse width modulating signal is set；
According to the peripheral hardware quantity of connection, it is determined that the quantity of the pulse width modulating signal of output, each pulse width modulating signal
Dutycycle and the adjacent pulse width modulating signal of each two phase contrast；
The original levels and initial phase of each pulse width modulating signal are set, start the pulse width modulation output of intervalometer
Pattern；
Each pulse width modulating signal is exported by chip selection signal line respectively to the enable pin of correspondence peripheral hardware；
According to the original levels and initial phase of each pulse width modulating signal, in each pulse width modulating signal
In low level time, the main frame and the correspondence peripheral hardware carry out data transmission.
2. Serial Peripheral Interface (SPI) multiplexing method according to claim 1, it is characterised in that the pulse width modulating signal
Quantity be equal to the connection peripheral hardware quantity.
3. Serial Peripheral Interface (SPI) multiplexing method according to claim 2, it is characterised in that each pulse width modulating signal
Dutycycle computing formula be
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection.
4. Serial Peripheral Interface (SPI) multiplexing method according to claim 3, it is characterised in that the adjacent pulse width of each two
The phase difference calculating formula of modulated signal is
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware quantity of connection.
5. Serial Peripheral Interface (SPI) multiplexing method according to claim 1, it is characterised in that each pulse described in the basis
The original levels and initial phase of bandwidth modulation signals, in the low level time of each pulse width modulating signal, the master
Machine and the correspondence peripheral hardware carry out data transmission, including：
In the low level time of each pulse width modulating signal, the chip selection signal line output low level of the main frame is extremely
The enable pin of the correspondence peripheral hardware, gates the correspondence peripheral hardware；
In the correspondence peripheral hardware gating time, the main frame and the correspondence peripheral hardware carry out data transmission.
6. a kind of communication system, including main frame and the plural peripheral hardware being connected with the main frame by Serial Peripheral Interface (SPI),
The main frame includes intervalometer,
The intervalometer is configured to pulse width modulation output mode, output signal under the pulse width modulation output mode
Quantity, the phase contrast root of the adjacent pulse width modulating signal of the dutycycle of each pulse width modulating signal and each two
Determine according to the peripheral hardware quantity of connection；
The main frame is configured to export to correspondence peripheral hardware each pulse width modulating signal respectively by chip selection signal line
Pin the original levels and initial phase according to each pulse width modulating signal are enabled, in each pulse width modulation
In the low level time of signal, carry out data transmission with the corresponding peripheral hardware.
7. communication system according to claim 6, it is characterised in that：The quantity of the pulse width modulating signal of the output
Equal to the peripheral hardware quantity of the connection.
8. communication system according to claim 7, it is characterised in that the meter of the dutycycle of each pulse width modulating signal
Calculating formula is
Wherein, η represents the dutycycle of each pulse width modulating signal, and n represents the peripheral hardware quantity of connection.
9. communication system according to claim 8, it is characterised in that the phase of the adjacent pulse width modulating signal of each two
The computing formula of potential difference is
Wherein, Δ φ represents the phase contrast of the adjacent pulse width modulating signal of each two, and n represents the peripheral hardware quantity of connection.
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| CN107480090A (en) * | 2017-08-01 | 2017-12-15 | 晶晨半导体(上海)股份有限公司 | A kind of circuit and method that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment |
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| CN107480090A (en) * | 2017-08-01 | 2017-12-15 | 晶晨半导体(上海)股份有限公司 | A kind of circuit and method that GPIO functions are realized in Serial Peripheral Interface (SPI) equipment |
| CN107480090B (en) * | 2017-08-01 | 2020-08-04 | 晶晨半导体(上海)股份有限公司 | Circuit and method for realizing GPIO function on serial peripheral interface device |
| CN107967227A (en) * | 2017-12-22 | 2018-04-27 | 苏州国芯科技有限公司 | A kind of communication means and SPI hosts, SPI slaves based on SPI |
| WO2020220798A1 (en) * | 2019-04-30 | 2020-11-05 | 京东方科技集团股份有限公司 | Control chip, control chip-based control method, and system |
| CN110471865A (en) * | 2019-08-15 | 2019-11-19 | 绵阳市维博电子有限责任公司 | A method of simulation SPI communication realizes that controller is communicated with driver |
| CN110471865B (en) * | 2019-08-15 | 2021-04-02 | 绵阳市维博电子有限责任公司 | Method for realizing communication between controller and driver by simulating SPI communication |
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