WO2020220798A1

WO2020220798A1 - Control chip, control chip-based control method, and system

Info

Publication number: WO2020220798A1
Application number: PCT/CN2020/075850
Authority: WO
Inventors: 容其贵; 赵留帅
Original assignee: 京东方科技集团股份有限公司; 高创(苏州)电子有限公司
Priority date: 2019-04-30
Filing date: 2020-02-19
Publication date: 2020-11-05
Also published as: CN110083572A

Abstract

The present disclosure relates to a control chip, a control chip-based control method, a system, and a non-volatile computer readable storage medium. The control chip comprises one or more SPIs, the SPIs having a plurality of chip signal lines which can realize different functions, and each chip signal line being connected to device signal lines, having corresponding functions, of a plurality of devices; and the control chip is configured to operate a target device by activating signal connections between the chip signal lines of the SPIs and the device signal lines of the target device, the target device being one of the plurality of devices.

Description

Control chip, control method and system based on control chip

Cross references to related applications

This application is based on the application whose CN application number is 201910359405.7 and the application date is April 30, 2019, and claims its priority. The disclosure of the CN application is hereby incorporated into this application as a whole.

Technical field

The present disclosure relates to the field of control technology, and in particular to a control chip, a control method based on a control chip, a control system, and a non-volatile computer-readable storage medium.

Background technique

Control chips such as MCU (Microcontroller Unit) and SoC (System on Chip) can be connected to different devices with SPI through SPI (Serial Peripheral Interface). In the related art, when the control chip needs to connect multiple devices with SPI, there needs to be multiple corresponding SPIs, which are connected to multiple devices in a one-to-one correspondence.

Summary of the invention

According to some embodiments of the present disclosure, there is provided a control chip, including one or more SPIs, where the SPI has multiple chip signal lines capable of realizing different functions, and each of the chip signal lines and multiple devices have The device signal line of the corresponding function is connected; the control chip is configured to operate the target device by activating the signal connection of each chip signal line of the SPI and each device signal line of the target device, and the target device is One of the multiple devices.

In some embodiments, the control chip further includes a plurality of selection interfaces, the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one, and the selection signal lines are used to transmit pairs Selecting signals of the multiple devices so that the control chip selects the target device through the selection signals.

In some embodiments, the device is a device with SPI; the function includes at least one of a read function, a write function, or a clock function.

In some embodiments, the control chip includes an SPI; the multiple devices are connected to the control chip through the SPI.

In some embodiments, the signal communication between each chip signal line for activating the SPI and each device signal line of the target device includes: activating each of the SPI by setting the selection signal of the target device to be valid. The chip signal line is connected with the signal of each device signal line of the target device; each chip of the SPI is disconnected by setting the selection signal of the other devices in the plurality of devices except the target device to be invalid The signal line communicates with the signal of each device signal line of the other device.

According to other embodiments of the present disclosure, a control method based on a control chip is provided, which is executed by a processor. The control chip includes one or more SPIs, where the SPI has multiple chip signal lines that can implement different functions. Each of the chip signal lines is connected to the device signal lines of the multiple devices with corresponding functions; the control method includes: the processor activates the signal lines between each chip signal line and each device signal line of the target device. The signal is connected to operate the target device, and the target device is one of the multiple devices.

In some embodiments, the control chip includes a plurality of selection interfaces, and the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one; the control method further includes: passing the selection signal The line sends a selection signal of the plurality of devices to the selection signal line of the device connected thereto, so as to select the target device through the selection signal.

In some embodiments, the function includes at least one of a read function, a write function, or a clock function.

In some embodiments, the control chip includes an SPI, and the multiple devices access the control chip through the SPI.

In some embodiments, activating the signal communication between each chip signal line and each device signal line of the target device includes: activating each chip signal of the SPI by setting the selection signal of the target device to be valid. The signal line is connected with the signal of each device signal line of the target device; the selection signals of other devices in the plurality of devices except the target device are set to be invalid to disconnect the signal lines of each chip of the SPI The signal of each device signal line of the other device is connected.

According to still other embodiments of the present disclosure, there is provided a control chip including one or more SPIs, wherein the SPI has a plurality of chip signal lines capable of realizing different functions, and each of the chip signal lines and the plurality of devices The control chip further includes: a memory; and a processor coupled to the memory, and the processor is configured to execute the following based on instructions stored in the memory device Step: Operate the target device by activating the signal connection between each chip signal line and each device signal line of the target device, and the target device is one of the multiple devices.

In some embodiments, the control chip further includes a plurality of selection interfaces, and the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one; the processor is configured to be stored based on The instructions in the memory device execute the following steps: send selection signals for the plurality of devices to the selection signal lines of the devices connected to the selection signal line to select the target device through the selection signal .

According to still other embodiments of the present disclosure, there is provided a non-volatile computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the control method as described in any of the foregoing embodiments is implemented.

According to still other embodiments of the present disclosure, a control system is provided, including: a plurality of devices having a plurality of device signal lines capable of realizing different functions, each of the device signal lines and a chip with corresponding functions of the control chip Signal line connection; the control chip described in any of the above embodiments.

Through the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, other features and advantages of the present disclosure will become clear.

Description of the drawings

The drawings described here are used to provide a further understanding of the present disclosure and constitute a part of the present application. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure, and do not constitute an improper limitation of the present disclosure. In the attached picture:

Fig. 1 shows a block diagram of a control chip according to an embodiment of the present disclosure;

Figure 2 shows a block diagram of a control chip according to another embodiment of the present disclosure;

Figure 3 shows a block diagram of a control system according to an embodiment of the present disclosure;

Fig. 4 shows a flowchart of a control method based on a control chip according to an embodiment of the present disclosure;

Fig. 5 shows a block diagram of a control chip according to another embodiment of the present disclosure;

Fig. 6 shows a block diagram of a control chip according to still another embodiment of the present disclosure.

It should be understood that the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportional relationship. In addition, the same or similar reference numerals indicate the same or similar components.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative, and in no way serves as any limitation to the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

Unless specifically stated otherwise, the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn in accordance with actual proportional relationships. The technologies, methods, and equipment known to those of ordinary skill in the relevant fields may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be regarded as part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiment may have different values. It should be noted that similar reference numerals and letters indicate similar items in the following drawings, so once a certain item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

Fig. 1 shows a block diagram of a control chip according to an embodiment of the present disclosure.

As shown in Figure 1, the chip 1 includes one or more interfaces 11, the interface 11 has multiple chip signal lines that can realize different functions, and each chip signal line is connected to the device 21, device 22 and other devices with corresponding functions. Device signal line connection. For example, the chip 1 may be a control chip, the interface 11 may be SPI, and the device may be a device with SPI.

In some embodiments, the bus of the interface 11 includes a signal line 111, a signal line 112, and a signal line 113 with different functions. The device 21 has a signal line 211, a signal line 212, and a signal line 213 with different functions. The device 22 has a signal line 221, a signal line 222, and a signal line 223 with different functions.

For example, the signal line 111 of the interface 11 and the signal line 211 of the device 21 and the signal line 221 of the device 22 have the same functions (such as read function, write function, clock function, etc.). Both the signal line 211 and the signal line 221 can be connected to the chip 1 through the signal line 111 to achieve corresponding functions. Similarly, the signal line 212 and the signal line 222 with the same function can be connected to the chip 1 through the signal line 112; the signal line 213 and the signal line 223 with the same function can be connected to the chip 1 through the signal line 113.

The chip 1 activates the connection (signal connection) between each chip signal line of the interface 11 and the target device (devices connected with the interface signal) of the multiple devices to operate the target device.

For example, the chip 1 wants to perform operations (such as read and write operations) on the device 21, that is, the device 21 is a target device. The selection signal of the device 21 can be set to be valid, and the connection of the signal line 111, the signal line 112, the signal line 113 and the signal line 211, the signal line 212, and the signal line 213 can be activated respectively.

In some embodiments, the chip 1 can connect each chip signal line of the interface with each device signal line of the target device by setting the selection signal of the target device to be valid. The chip 1 can set the selection signals of other devices among the multiple devices to be invalid except for the target device to disconnect the signal lines of each chip of the interface 11 and the signal lines of other devices.

For example, if the device 21 is a target device, the chip 1 can set the selection signal of the device 22 to be invalid, and disconnect the

signal lines

111, 112, and 113 from the

signal lines

221, 222, and 223.

In some embodiments, the chip 1 has an interface 11, and all devices that the chip 1 wants to operate are connected to the chip 1 through the interface 11.

In the above embodiment, the chip 1 can simultaneously mount multiple devices through one interface 11. Compared with related technologies, the number of signal lines of the chip is reduced, and the system complexity is reduced.

In some embodiments, the chip of the present disclosure may be configured through the embodiment of FIG. 2.

Fig. 2 shows a block diagram of a chip according to another embodiment of the present disclosure.

As shown in Fig. 2, compared with Fig. 1, the chip 1'also includes a plurality of selection interfaces, such as a selection interface 12 and a selection interface 13. The multiple selection interfaces are respectively connected to the selection signal lines of multiple devices one-to-one. The selection signal line is used to transmit selection signals for multiple devices, so that the chip selects the target device through the selection signal.

For example, the signal line 214 of the device 21 is a selection signal line, and the selection interface 12 of the chip 1'is connected to the signal line 214 through the signal line 121. The signal line 224 of the device 22 is a selection signal line, and the selection interface 13 of the chip 1'is connected to the signal line 224 through the signal line 131.

In some embodiments, the chip 1'is the master, the

devices

21 and 22 are the slaves, and the interface 11 may be SPI. The signal line 111 of the interface 11 can be a MISO (Master Output Slave Input) signal line, and the signal line 112 can be a MOSI (Master Input Slave Output) signal line. The signal line 113 can be SCK (Synchronous Clock) signal line. Each signal line of the interface 11 is connected to the MISO signal line, MOSI signal line and SCK signal line corresponding to the device 21 and the device 22 respectively.

In some embodiments, the selection interface 12 and the selection interface 13 may be IO (Input Output) interfaces, and the signal line 121 and the signal line 131 may be the SS (Slave Select, slave selection) signal line of the chip 1'or CS (Chip Select) signal line. The signal line 121 and the signal line 131 are respectively connected to the SS signal line or the CS signal line corresponding to the device 21 and the device 22.

In some embodiments, the three signal lines MISO, MOSI, and SCK of all devices are connected to the corresponding functional signal lines of SPI. All devices are connected to the control chip via SPI. The SS or CS signal line of each device is individually connected to the different IO interfaces of the control chip as the selection signal line. When the chip needs to access a specific device, make the selection signal of the device valid and invalid the selection signals of other devices. In this way, the chip can access the device normally when other devices do not respond.

In the above embodiment, the chip can be connected to multiple devices through one SPI, and adding one device only needs to add one selection signal line. In this way, when multiple devices need to be connected, signal lines can be saved, and no additional chips need to be added, thereby reducing the complexity of the system, reducing the amount of software code, and reducing the cost.

Fig. 3 shows a block diagram of a control system according to an embodiment of the present disclosure.

As shown in FIG. 3, the control system 3 includes a plurality of devices (device 32, device 33, etc.), and the chip 31 in any of the above embodiments. The chip 31 can operate multiple devices.

Fig. 4 shows a flowchart of a control method based on a control chip according to an embodiment of the present disclosure.

As shown in FIG. 4, the method includes: step 410, activating the connection of the target device with the signal line of the chip; and step 420, operating the target device. For example, the method can be executed by a processor.

In step 410, the connection between each chip signal line and each device signal line of the target device is activated. For example, the chip (control chip) includes one or more interfaces (SPI), and the SPI has multiple chip signal lines that can implement different functions. Each chip signal line is connected to a device signal line of a plurality of devices with corresponding functions.

In some embodiments, the chip includes multiple selection interfaces, which are respectively connected to the selection signal lines of multiple devices one-to-one. The chip transmits selection signals to multiple devices through the selection signal line. The chip determines the target device through the selection signal.

In some embodiments, the selection signal of the target device is set to be valid to connect the signal lines of each chip of the SPI and the signal lines of each device of the target device (signal connection); The selection signals of other devices are set to invalid to disconnect the signal lines of each chip of the SPI and the signal lines of each device of other devices.

In some embodiments, the chip includes an SPI, and all devices connect to the chip through the SPI.

In step 420, the target device is operated.

Fig. 5 shows a block diagram of a control chip according to another embodiment of the present disclosure.

As shown in FIG. 5, the control chip 5 of this embodiment includes one or more SPI 53. SPI 53 has multiple chip signal lines that can realize different functions. Each chip signal line is connected to the device signal line of multiple devices with corresponding functions.

The memory 51 and a processor 52 coupled to the memory 51 are configured to execute the control method in any embodiment of the present disclosure based on instructions stored in the memory 51.

Among them, the memory 51 may include, for example, a system memory, a fixed non-volatile storage medium, and the like. The system memory stores, for example, an operating system, an application program, a boot loader (Boot Loader), a database, and other programs.

In some embodiments, the processor 52 is configured to perform the following steps based on the instructions stored in the memory device: by activating the signal connection between each chip signal line and each device signal line of the target device to perform the target device Operation, the target device is one of multiple devices. For example, the function includes at least one of a read function, a write function, or a clock function.

For example, by setting the selection signal of the target device to be active, the signal connection of each chip signal line of the SPI 53 and each device signal line of the target device is activated; by selecting a device other than the target device among multiple devices The signal is set to invalid to disconnect the signal connection between the signal lines of each chip of SPI53 and the signal lines of other devices.

In some embodiments, the control chip 5 further includes multiple selection interfaces, and the multiple selection interfaces are respectively connected to the selection signal lines of multiple devices one-to-one. The processor 52 is configured to perform the following steps based on the instructions stored in the memory device: send selection signals for multiple devices to the selection signal line of the device connected to the selection signal line to select the target device through the selection signal.

In some embodiments, the control chip 5 includes an SPI 53; multiple devices access the control chip through the SPI 53.

According to still other embodiments of the present disclosure, there is provided a control system including: a plurality of devices having a plurality of device signal lines capable of realizing different functions, and each device signal line is connected to a chip signal line with a corresponding function of the control chip ; The control chip described in any of the above embodiments.

As shown in FIG. 6, the control device 6 of this embodiment includes: a memory 610 and a processor 620 coupled to the memory 610. The processor 620 is configured to execute any one of the foregoing embodiments based on instructions stored in the memory 610. Control methods in.

The memory 610 may include, for example, a system memory, a fixed non-volatile storage medium, and the like. The system memory, for example, stores an operating system, an application program, a boot loader (Boot Loader), and other programs.

The control device 6 may also include an input and output interface 630, a network interface 640, a storage interface 650, and the like. These

interfaces

630, 640, 650, and the memory 610 and the processor 620 may be connected via a bus 660, for example. Among them, the input and output interface 630 provides connection interfaces for input and output devices such as a display, a mouse, a keyboard, and a touch screen. The network interface 640 provides a connection interface for various networked devices. The storage interface 650 provides a connection interface for external storage devices such as SD cards and U disks.

Those skilled in the art should understand that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable non-transitory storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. .

So far, the control chip, the control method based on the control chip, the control system, and the non-volatile computer-readable storage medium according to the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

The method and system of the present disclosure may be implemented in many ways. For example, the method and system of the present disclosure can be implemented by software, hardware, firmware or any combination of software, hardware, and firmware. The above-mentioned order of the steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless specifically stated otherwise. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, and these programs include machine-readable instructions for implementing the method according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

A control chip including one or more serial peripheral interfaces SPI, among which,

The SPI has multiple chip signal lines that can realize different functions, and each of the chip signal lines is connected to a device signal line with corresponding functions of multiple devices;

The control chip is configured to operate the target device by activating the signal communication of each chip signal line of the SPI and each device signal line of the target device, and the target device is one of the multiple devices .
The control chip according to claim 1, further comprising:

A plurality of selection interfaces, the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one, and the selection signal lines are used to transmit selection signals to the plurality of devices so that the control chip The target device is selected by the selection signal.
The control chip according to claim 1, wherein:

The device is a device with SPI;

The function includes at least one of a read function, a write function, or a clock function.
The control chip according to any one of claims 1-3, wherein:

The control chip includes an SPI;

The multiple devices access the control chip through the SPI.
The control chip according to any one of claims 1-3, wherein the signal communication between each chip signal line that activates the SPI and each device signal line of the target device comprises:

By setting the selection signal of the target device to be active, the signal connection of each chip signal line of the SPI and each device signal line of the target device is activated;

The signal connection of each chip signal line of the SPI and each device signal line of the other device is disconnected by setting the selection signals of the other devices except the target device in the plurality of devices to be invalid.
A control method based on a control chip, which is executed by a processor. The control chip includes one or more serial peripheral interfaces SPI, where the SPI has multiple chip signal lines that can realize different functions, and each chip The signal line is connected to the signal line of a plurality of devices with corresponding functions;

The control method includes: the processor operates the target device by activating signal communication between each chip signal line and each device signal line of the target device, and the target device is one of the plurality of devices. one of.
The control method according to claim 6, wherein:

The control chip includes a plurality of selection interfaces, and the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one;

The control method further includes:

The selection signal for the plurality of devices is sent to the selection signal line of the device connected thereto through the selection signal line, so as to select the target device by the selection signal.
The control method according to claim 6, wherein:

The function includes at least one of a read function, a write function, or a clock function.
8. The control method according to any one of claims 6-8, wherein said activating signal communication between each chip signal line and each device signal line of the target device comprises:

By setting the selection signal of the target device to be active, the signal connection of each chip signal line of the SPI and each device signal line of the target device is activated;

The selection signals of the other devices among the plurality of devices except the target device are set to be invalid, so as to disconnect the signal communication between the chip signal lines of the SPI and the signal lines of the other devices.
A control chip includes one or more serial peripheral interfaces SPI, where the SPI has multiple chip signal lines capable of realizing different functions, and each of the chip signal lines is connected to a device signal of a plurality of devices with corresponding functions Wire connection

The control chip also includes:

Memory; and

A processor coupled to the memory, and the processor is configured to perform the following steps based on instructions stored in the memory device:

The target device is operated by activating the signal connection between each chip signal line and each device signal line of the target device, and the target device is one of the plurality of devices.
The control chip according to claim 10, further comprising a plurality of selection interfaces, the plurality of selection interfaces are respectively connected to the selection signal lines of the plurality of devices one-to-one;

The processor is configured to perform the following steps based on the instructions stored in the memory device:

The selection signal for the plurality of devices is sent to the selection signal line of the device connected thereto through the selection signal line, so as to select the target device by the selection signal.
The control chip according to claim 10, wherein:

The function includes at least one of a read function, a write function, or a clock function.
The control chip according to any one of claims 10-12, wherein:

The control chip includes an SPI;

The multiple devices access the control chip through the SPI.
The control chip according to any one of claims 10-12, wherein the signal communication between each chip signal line that activates the SPI and each device signal line of the target device comprises:

By setting the selection signal of the target device to be valid, the signal connection of each chip signal line of the SPI and each device signal line of the target device is activated;

The signal connection of each chip signal line of the SPI and each device signal line of the other device is disconnected by setting the selection signals of the other devices except the target device in the plurality of devices to be invalid.
A non-volatile computer-readable storage medium with a computer program stored thereon, which when executed by a processor realizes the control method according to any one of claims 6-9.
A control system including:

The control chip according to any one of claims 1-5 and 10-14;

The multiple devices have multiple device signal lines capable of realizing different functions, and each of the device signal lines is connected to a chip signal line with corresponding functions of the control chip.