TWI678624B - Modularized computer system and computing core board thereof - Google Patents
Modularized computer system and computing core board thereof Download PDFInfo
- Publication number
- TWI678624B TWI678624B TW107118824A TW107118824A TWI678624B TW I678624 B TWI678624 B TW I678624B TW 107118824 A TW107118824 A TW 107118824A TW 107118824 A TW107118824 A TW 107118824A TW I678624 B TWI678624 B TW I678624B
- Authority
- TW
- Taiwan
- Prior art keywords
- input
- connection interface
- output
- interface
- board
- Prior art date
Links
Landscapes
- Stored Programmes (AREA)
Abstract
一種模組化計算機系統,包含輸入輸出板及運算核心板。輸入輸出板包含:第一連接介面以及至少一輸入輸出周邊電路。各輸入輸出周邊電路連接於第一連接介面。運算核心板包含:第二連接介面、記憶單元、儲存單元以及處理單元。第二連接介面供輸入輸出板的第一連接介面連接。記憶單元記錄對應輸入輸出周邊電路的類型資訊。儲存單元儲存有複數預備韌體。處理單元連接記憶單元、儲存單元與第二連接介面。處理單元自記憶單元取得類型資訊,並根據類型資訊於預備韌體中取得相符者做為驅動韌體。處理單元執行驅動韌體以控制輸入輸出周邊電路。A modular computer system includes an input-output board and a computing core board. The input-output board includes: a first connection interface and at least one input-output peripheral circuit. Each input-output peripheral circuit is connected to the first connection interface. The computing core board includes: a second connection interface, a memory unit, a storage unit, and a processing unit. The second connection interface is used for connecting the first connection interface of the input-output board. The memory unit records the type information of the corresponding input and output peripheral circuits. The storage unit stores a plurality of prepared firmware. The processing unit is connected to the memory unit, the storage unit and the second connection interface. The processing unit obtains type information from the memory unit, and obtains a match from the prepared firmware according to the type information as the driving firmware. The processing unit executes driving firmware to control input and output peripheral circuits.
Description
本發明是關於一種計算機系統,特別是指一種模組化計算機系統及其運算核心板。The invention relates to a computer system, in particular to a modular computer system and a computing core board thereof.
目前,為了因應多數使用者的需求,一般廠商製造應用系統時會以運算核心板搭配輸入輸出板方式來設計。然而,欲更新或升級應用系統時,有時必須對應升級運算核心板,藉此能更換為效能更佳的處理器。At present, in order to meet the needs of most users, general manufacturers will design the computing core board with input and output boards when manufacturing application systems. However, when you want to update or upgrade the application system, sometimes you must upgrade the computing core board accordingly, so that you can replace it with a more efficient processor.
然而,通常同類型的運算核心板可以應用於多種類的輸入輸出板。也就是說,相同的運算核心板可以與不同類型的輸入輸出板搭配而構成應用系統。因此,欲使用不同的輸入輸出板時,必須在運算核心板安裝對應的韌體,造成使用者常常不曉得至哪裡取得正確的韌體,也不知道如何安裝韌體等困擾。However, usually the same type of computing core board can be applied to multiple types of input and output boards. That is, the same computing core board can be combined with different types of input and output boards to form an application system. Therefore, when you want to use different I / O boards, you must install the corresponding firmware on the computing core board, which causes users to not know where to obtain the correct firmware, and how to install the firmware.
鑑於上述,本發明實施例是提供一種模組化計算機系統,模組化計算機系統包含輸入輸出板及運算核心板。In view of the foregoing, an embodiment of the present invention provides a modular computer system. The modular computer system includes an input-output board and a computing core board.
輸入輸出板包含:第一連接介面以及至少一輸入輸出周邊電路。各輸入輸出周邊電路連接於第一連接介面。運算核心板包含:第二連接介面、記憶單元、儲存單元以及處理單元。第二連接介面供輸入輸出板的第一連接介面對應連接。記憶單元記錄對應輸入輸出周邊電路的類型資訊。儲存單元儲存有複數預備韌體。處理單元連接記憶單元、儲存單元與第二連接介面。處理單元自記憶單元取得類型資訊,並根據類型資訊於預備韌體中取得相符者做為驅動韌體。處理單元執行驅動韌體以控制輸入輸出板的輸入輸出周邊電路。The input-output board includes: a first connection interface and at least one input-output peripheral circuit. Each input-output peripheral circuit is connected to the first connection interface. The computing core board includes: a second connection interface, a memory unit, a storage unit, and a processing unit. The second connection interface is correspondingly connected to the first connection interface of the input-output board. The memory unit records the type information of the corresponding input and output peripheral circuits. The storage unit stores a plurality of prepared firmware. The processing unit is connected to the memory unit, the storage unit and the second connection interface. The processing unit obtains type information from the memory unit, and obtains a match from the prepared firmware according to the type information as the driving firmware. The processing unit executes driving the firmware to control the input-output peripheral circuits of the input-output board.
於一實施例中,運算核心板更包含輸入介面,以經由輸入介面寫入類型資訊至記憶單元。In an embodiment, the computing core board further includes an input interface to write type information to the memory unit through the input interface.
依據上述實施例,本發明的模組化計算機系統及其運算核心板能夠於輸入輸出板連接運算核心板時,運算核心板根據記憶單元而能提供適合的驅動韌體以進一步控制輸入輸出板。藉此能讓使用者操作時能更為便捷,並且節省不少研發成本。According to the above embodiments, when the modular computer system and the computing core board of the present invention can connect the computing core board to the input / output board, the computing core board can provide suitable driving firmware according to the memory unit to further control the input / output board. This allows users to operate more conveniently and saves a lot of research and development costs.
圖1是本發明模組化計算機系統的一實施例之架構示意圖。請參閱圖1,模組化計算機系統1包含輸入輸出板10與運算核心板20。輸入輸出板10是與運算核心板20連接。FIG. 1 is a schematic structural diagram of an embodiment of a modular computer system according to the present invention. Referring to FIG. 1, the modular computer system 1 includes an input-output board 10 and a computing core board 20. The input / output board 10 is connected to a computing core board 20.
於一實施例中,模組化計算機系統1可例如為工業電腦、個人電腦、筆記型電腦、嵌入式系統等。In one embodiment, the modular computer system 1 may be, for example, an industrial computer, a personal computer, a notebook computer, an embedded system, or the like.
於一實施例中,輸入輸出板10包含有第一連接介面11與輸入輸出周邊電路12。輸入輸出周邊電路12連接第一連接介面11。其中,輸入輸出周邊電路12是接收來自第一連接介面11的訊息,並且進而依據訊息而令輸入輸出周邊電路12對應運行。In one embodiment, the input-output board 10 includes a first connection interface 11 and an input-output peripheral circuit 12. The input-output peripheral circuit 12 is connected to the first connection interface 11. The input-output peripheral circuit 12 receives a message from the first connection interface 11, and further causes the input-output peripheral circuit 12 to operate correspondingly according to the message.
於一實施例中,輸入輸出周邊電路12可以為具有一個或多個特定用途之周邊模組,因此可以透過運算核心板20發送訊息並經由第一連接介面11至輸入輸出周邊電路12,以進一步對輸入輸出周邊電路12進行操控。於一些實施例中,輸入輸出周邊電路12可以為儲存模組、顯示模組、控制模組等,本發明並非以此為限制。In an embodiment, the input / output peripheral circuit 12 may be a peripheral module having one or more specific uses. Therefore, it is possible to send a message through the computing core board 20 and to the input / output peripheral circuit 12 through the first connection interface 11 to further The input / output peripheral circuit 12 is controlled. In some embodiments, the input / output peripheral circuit 12 may be a storage module, a display module, a control module, and the like, and the present invention is not limited thereto.
於一些實施例中,輸入輸出周邊電路12還包含有輸出入埠121。輸出入埠121能進一步連接具有特定用途的周邊裝置30。In some embodiments, the input / output peripheral circuit 12 further includes an input / output port 121. The input / output port 121 can be further connected to a peripheral device 30 having a specific application.
於一實施例中,運算核心板20包含有第二連接介面21、記憶單元22、儲存單元23與處理單元24。處理單元24分別與第二連接介面21、記憶單元22以及儲存單元23連接。In one embodiment, the computing core board 20 includes a second connection interface 21, a memory unit 22, a storage unit 23 and a processing unit 24. The processing unit 24 is connected to the second connection interface 21, the memory unit 22, and the storage unit 23, respectively.
第二連接介面21是供輸入輸出板10的第一連接介面11對應連接,是以,輸入輸出周邊電路12能經由第二連接介面21與第一連接介面11接收訊息,並且能讓輸入輸出周邊電路12根據訊息而運行(或對應經由輸出入埠121傳輸)。藉此可對運算核心板20直接控制位於輸入輸出板10上的輸入輸出周邊電路12,亦能因連接不同的輸入輸出板10而擴充更多類型的輸出入埠121。The second connection interface 21 is a corresponding connection for the first connection interface 11 of the input / output board 10, so that the input / output peripheral circuit 12 can receive information through the second connection interface 21 and the first connection interface 11, and can allow input and output peripherals The circuit 12 operates according to the message (or correspondingly transmits through the input / output port 121). In this way, the computing core board 20 can directly control the input / output peripheral circuit 12 located on the input / output board 10, and can also expand more types of input / output ports 121 by connecting different input / output boards 10.
圖2是本發明的記憶單元22之架構示意圖。請回頭參閱圖1與圖2,記憶單元22是紀錄對應於輸入輸出板10的類型資訊。在一實施例中,記憶單元22是紀錄輸入輸出周邊電路12的類型資訊。在此,類型資訊可以包含如輸入輸出板10中各元件(如第一連接介面11或各輸入輸出周邊電路12)的廠商、版本、晶片型號等,但本發明不限於此。FIG. 2 is a schematic structural diagram of a memory unit 22 according to the present invention. Please refer back to FIG. 1 and FIG. 2. The memory unit 22 records type information corresponding to the input / output board 10. In one embodiment, the memory unit 22 records the type information of the input / output peripheral circuit 12. Here, the type information may include, for example, the manufacturer, version, and chip model of each component in the input / output board 10 (such as the first connection interface 11 or each input / output peripheral circuit 12), but the present invention is not limited thereto.
在一實施例中,運算核心板20包含有輸入介面25,記憶單元22的類型資訊是可以經由輸入介面25依據寫入指令載入。換句話說,使用者可以自行利用寫入指令而將對應於輸入輸出板10的類型資訊經由輸入介面25寫入至記憶單元22中。In one embodiment, the computing core board 20 includes an input interface 25, and the type information of the memory unit 22 can be loaded through the input interface 25 according to a write instruction. In other words, the user can write the type information corresponding to the input-output board 10 into the memory unit 22 through the input interface 25 by using the write instruction.
儲存單元23是儲存有單個或複數預備韌體231,在一實施例中為複數。每一類型資訊對應有一預備韌體231。預備韌體231包含對應輸入輸出板10中各元件的晶片的暫存器、腳位等定義。在此,輸入輸出周邊電路12能依據記憶單元22中對應的類型資訊231而能自第一連接介面11接收訊息,以進一步經由輸出入埠121與外部的周邊裝置30正確傳輸。The storage unit 23 stores a single or plural prepared firmware 231, which is plural in one embodiment. Each type of information corresponds to a prepared firmware 231. The preparation firmware 231 includes definitions of registers, pins and the like of the chip corresponding to each element in the input-output board 10. Here, the input / output peripheral circuit 12 can receive information from the first connection interface 11 according to the corresponding type information 231 in the memory unit 22 for further transmission through the input / output port 121 and the external peripheral device 30.
於一實施例中,輸入輸出周邊電路12是可以讓使用者自行設計,或使用與參考電路相同之電路,本發明並非以此為限制。其中,參考電路可以是由運算核心板20的提供商或由輸入輸出板10的提供商提供。In one embodiment, the input / output peripheral circuit 12 can be designed by the user or used the same circuit as the reference circuit, which is not limited in the present invention. The reference circuit may be provided by a provider of the computing core board 20 or a provider of the input / output board 10.
在一實施例中,記憶單元22還儲存有對應類型資訊所對應的參考電路的參數。藉此當使用者使用的輸入輸出周邊電路12是運算核心板20提供商提供的參考電路時,則使用者僅須將輸入輸出板10與運算核心板20相連接後,即可快速地讓輸入輸出板10正常運行。In an embodiment, the memory unit 22 further stores parameters of the reference circuit corresponding to the corresponding type information. Therefore, when the input / output peripheral circuit 12 used by the user is a reference circuit provided by the computing core board 20 provider, the user only needs to connect the input / output board 10 and the computing core board 20 to quickly input. The output board 10 operates normally.
於此,當運算核心板20偵測到有輸入輸出板10連接後(即第一連接介面11與第二連接介面21對應連接後),處理單元24會讀取記憶單元22中儲存的類型資訊。於是,處理單元24自記憶單元22接收類型資訊後,可根據類型資訊於儲存單元23中的各個預備韌體231中取得相符者做為驅動韌體。因此,處理單元24執行驅動韌體後,便而可控制輸入輸出板10,而可經由第一連接介面11與輸入輸出周邊電路12進行傳輸或操控(亦或經由輸出入埠121與所連接之周邊裝置30進行傳輸或操控)。因此,使用者無需額外找尋、安裝合適的韌體,將輸入輸出板10連接到運算核心板20後,即可連接與使用周邊裝置30。Here, when the computing core board 20 detects that the input / output board 10 is connected (that is, after the first connection interface 11 and the second connection interface 21 are correspondingly connected), the processing unit 24 reads the type information stored in the memory unit 22 . Therefore, after receiving the type information from the memory unit 22, the processing unit 24 can obtain the corresponding ones from the respective prepared firmware 231 in the storage unit 23 as the driving firmware according to the type information. Therefore, after the processing unit 24 executes the driving firmware, it can control the input / output board 10, and can transmit or control the input / output peripheral circuit 12 through the first connection interface 11 (or the input / output port 121 and the connected The peripheral device 30 performs transmission or manipulation). Therefore, the user can connect and use the peripheral device 30 after the input / output board 10 is connected to the computing core board 20 without having to find and install appropriate firmware.
在一實施例中,當更換相同類型的輸入輸出板10,且其對應於記憶單元22紀錄的類型資訊。則使用者無須再次對記憶單元22寫入另一符合輸入輸出版10之類型資訊,其可直接更換為相同類型的輸入輸出板10後而能快速的讓輸入輸出板10正常運行。In one embodiment, when the input / output board 10 of the same type is replaced, it corresponds to the type information recorded by the memory unit 22. Then, the user does not need to write another type information conforming to the input / output version 10 to the memory unit 22, and it can be directly replaced with the input / output board 10 of the same type to enable the input / output board 10 to run normally.
在一實施例中,請再次參閱圖2,每一類型資訊包含一共通資訊222及一相異資訊221。共通資訊222為多個該類型資訊中的共同部分,相異資訊221為多個類型資訊中的不同部分。如此,可節省記憶空間。共通資訊222可包含識別字符、類型資訊的版本號及輸入輸出板10的產品編號。In an embodiment, please refer to FIG. 2 again. Each type of information includes a common information 222 and a different information 221. The common information 222 is a common part of a plurality of types of information, and the different information 221 is a different part of the plurality of types of information. This saves memory space. The common information 222 may include the identification number, the version number of the type information, and the product number of the input-output board 10.
於一實施例中,輸出入埠121以COM埠實現。於此,輸入輸出周邊電路12是對應於COM埠之驅動電路。當運算核心板20與輸入輸出板10連接後,輸入輸出板10經由第一連接介面11接收運算核心板20的訊息(如一資料檔)。透過驅動電路能順利地將資料檔由COM埠傳送至與其連接的周邊裝置30,以供其開啟、儲存、載入至一執行程序或其他各種應用。In one embodiment, the I / O port 121 is implemented by a COM port. Here, the input / output peripheral circuit 12 is a driving circuit corresponding to a COM port. After the computing core board 20 is connected to the input / output board 10, the input / output board 10 receives a message (such as a data file) from the computing core board 20 through the first connection interface 11. Through the driving circuit, the data file can be smoothly transferred from the COM port to the peripheral device 30 connected to it, so that it can be opened, stored, and loaded into an execution program or other various applications.
於一實施例中,輸出入埠121以HDMI埠實現。於此,輸入輸出周邊電路12是對應於HDMI埠之驅動電路。當運算核心板20與輸入輸出板10連接後,輸入輸出板10經由第一連接介面11接收運算核心板20的訊息(如一影像檔)。透過驅動電路能順利地將影像檔由HDMI埠傳送至與其連接的周邊裝置30,以供其顯示影像、儲存影像檔或其他各種應用。In one embodiment, the input / output port 121 is implemented as an HDMI port. Here, the input / output peripheral circuit 12 is a driving circuit corresponding to the HDMI port. After the computing core board 20 is connected to the input / output board 10, the input / output board 10 receives a message (such as an image file) from the computing core board 20 through the first connection interface 11. Through the driving circuit, the image file can be smoothly transmitted from the HDMI port to the peripheral device 30 connected to it, so that it can display the image, store the image file, or other various applications.
圖3為本發明一實施例之輸入輸出板10之架構示意圖。請參閱圖3,第一連接介面11以低接腳計數40實現,輸出入埠121以串列通訊埠43實現。輸入輸出周邊電路12於此為兩個,各輸入輸出周邊電路12包含一第一周邊電路41及二個第二周邊電路42。輸入輸出板10經由低接腳計數40接收運算核心板20的訊息。第一周邊電路41將低接腳計數40協定轉換為另一通訊協定,例如UART。在此,第一周邊電路41是轉換成兩組UART輸出。二個第二周邊電路42分別接收此二組UART輸出,而將UART訊號轉換為COM埠訊號(如RS232、RS422、RS485),於串列通訊埠43輸出。於此,運算核心板20可經由低接腳計數40對第一周邊電路41初始化。第一周邊電路41與第二周邊電路42也有部分接腳相連接而以低接腳計數40來通訊,使得運算核心板20可透過第一周邊電路41對第二周邊電路42進行初始化設定。換句話說,輸入輸出周邊電路12能將自第一連接介面11接收的訊息轉換為符合輸出入埠121的通訊協定。FIG. 3 is a schematic structural diagram of an input-output board 10 according to an embodiment of the present invention. Referring to FIG. 3, the first connection interface 11 is implemented by a low pin count 40, and the input / output port 121 is implemented by a serial communication port 43. There are two input-output peripheral circuits 12 here, and each input-output peripheral circuit 12 includes a first peripheral circuit 41 and two second peripheral circuits 42. The input / output board 10 receives messages from the computing core board 20 via the low pin count 40. The first peripheral circuit 41 converts the low pin count 40 protocol into another communication protocol, such as UART. Here, the first peripheral circuit 41 is converted into two sets of UART outputs. The two second peripheral circuits 42 respectively receive the two sets of UART outputs, and convert the UART signals into COM port signals (such as RS232, RS422, RS485), and output them through the serial communication port 43. Here, the computing core board 20 can initialize the first peripheral circuit 41 via the low pin count 40. The first peripheral circuit 41 and the second peripheral circuit 42 also have some pins connected to communicate with the low pin count 40, so that the computing core board 20 can initialize the second peripheral circuit 42 through the first peripheral circuit 41. In other words, the input / output peripheral circuit 12 can convert a message received from the first connection interface 11 into a communication protocol conforming to the input / output port 121.
於一實施例中,儲存單元23與記憶單元22為非揮發記憶體。例如:電子抹除式可複寫唯讀記憶體(EEPROM)。In one embodiment, the storage unit 23 and the memory unit 22 are non-volatile memory. For example: electronic erasable rewritable read-only memory (EEPROM).
於一實施例中,處理單元24可以微處理器、微控制器等。In one embodiment, the processing unit 24 may be a microprocessor, a microcontroller, or the like.
於一實施例中,輸入輸出埠12可例如為DIO(Digital Input Output)埠、USB埠、一HDMI埠、一COM埠、一UART埠、一網路埠、一記憶卡埠或其他種類之輸入輸出埠12中任一者或其任意組合。In an embodiment, the input / output port 12 may be, for example, a DIO (Digital Input Output) port, a USB port, an HDMI port, a COM port, a UART port, a network port, a memory card port, or other types of input. Any one of the output ports 12 or any combination thereof.
於一實施例中,第一連接介面11與第二連接介面21包含COM Express傳輸介面、Qseven傳輸介面、SMARC傳輸介面中任一者或其任意組合,但本發明非以此為限。所述傳輸介面(如第一連接介面11或/及第二連接介面21)可例如為系統管理匯流排(System Management Bus,SMBus)、快速週邊組件互連(PCI Express)、低接腳計數(Low Pin Count,LPC)或其他種類之傳輸介面中任一者或其任意組合。In an embodiment, the first connection interface 11 and the second connection interface 21 include any one of a COM Express transmission interface, a Qseven transmission interface, a SMARC transmission interface, or any combination thereof, but the present invention is not limited thereto. The transmission interface (such as the first connection interface 11 or / and the second connection interface 21) may be, for example, a system management bus (System Management Bus, SMBus), a fast peripheral component interconnect (PCI Express), and a low pin count ( Low Pin Count (LPC) or any other type of transmission interface or any combination thereof.
於一實施例中,周邊裝置30可以為儲存裝置(如硬碟、SSD、記憶卡、ROM或ROM)、顯示裝置(如液晶螢幕、觸控螢幕)、操控裝置(如滑鼠、鍵盤、手寫板或按鍵)、運算裝置(GPU、微處理器或微控制器)或其他各種電子設備,本發明並非為限制。再於一些實施例中,周邊裝置30可以是前述各種電子設備之任意組合。In one embodiment, the peripheral device 30 may be a storage device (such as a hard disk, SSD, memory card, ROM, or ROM), a display device (such as an LCD screen, a touch screen), and a control device (such as a mouse, a keyboard, or a handwriting device). Board or button), computing device (GPU, microprocessor or microcontroller) or various other electronic devices, the present invention is not limited. In some embodiments, the peripheral device 30 may be any combination of the aforementioned various electronic devices.
於一實施例中,運算核心板20可為模組化計算機系統1中提供運算單元的主機板。輸入輸出板10可為計算機系統1提供各類型輸入輸出周邊電路12(如不同類型的輸出入埠121)或周邊裝置30,以進一步能達到模組化計算機系統1預期之功效的主機板。In one embodiment, the computing core board 20 may be a main board that provides a computing unit in the modular computer system 1. The input / output board 10 can provide the computer system 1 with various types of input / output peripheral circuits 12 (such as different types of input / output ports 121) or peripheral devices 30, so as to further achieve the motherboard as expected by the modular computer system 1.
依據上述實施例,本發明實施例之模組化計算機系統1及其運算核心板20能夠在連接有輸入輸出板10時,自動依據記憶單元22中的類型資訊而執行合適的韌體,以正確經由輸入輸出板10與輸入輸出周邊電路12(或進一步與周邊裝置30)進行通訊,無需使用者另外安裝韌體。藉此能讓使用者便捷的進行更新,進而能快速的提升模組化計算機系統1的效能。According to the above embodiment, the modular computer system 1 and the computing core board 20 of the embodiment of the present invention can automatically execute appropriate firmware according to the type information in the memory unit 22 when the input / output board 10 is connected, so as to correctly The I / O board 10 communicates with the I / O peripheral circuit 12 (or further communicates with the peripheral device 30) via the I / O board 10, without requiring the user to install additional firmware. In this way, users can update conveniently and further improve the performance of the modular computer system 1 quickly.
1‧‧‧計算機系統1‧‧‧ computer system
10‧‧‧輸入輸出板10‧‧‧I / O board
11‧‧‧第一連接介面11‧‧‧First connection interface
12‧‧‧輸入輸出周邊電路12‧‧‧I / O peripheral circuit
20‧‧‧運算核心板20‧‧‧ Computing Core Board
21‧‧‧第二連接介面21‧‧‧Second connection interface
22‧‧‧記憶單元22‧‧‧Memory unit
23‧‧‧儲存單元23‧‧‧Storage unit
24‧‧‧處理單元24‧‧‧ Processing Unit
25‧‧‧輸入介面25‧‧‧Input interface
30‧‧‧周邊裝置30‧‧‧ Peripherals
40‧‧‧低接腳計數40‧‧‧ Low pin count
41‧‧‧第一周邊電路41‧‧‧First peripheral circuit
42‧‧‧第二周邊電路42‧‧‧Second peripheral circuit
43‧‧‧串列通訊埠43‧‧‧Serial communication port
121‧‧‧輸出入埠121‧‧‧I / O port
221‧‧‧相異資訊221‧‧‧ Dissimilar information
222‧‧‧共通資訊222‧‧‧ Common Information
231‧‧‧預備韌體231‧‧‧Firmware Preparation
[圖1]是本發明模組化計算機系統的一實施例之架構示意圖。 [圖2]是本發明的記憶單元之架構示意圖。 [圖3]是本發明一實施例之輸入輸出板之架構示意圖。[Fig. 1] A schematic structural diagram of an embodiment of a modular computer system according to the present invention. FIG. 2 is a schematic diagram of a memory unit of the present invention. [FIG. 3] A schematic diagram of the architecture of an input-output board according to an embodiment of the present invention.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107118824A TWI678624B (en) | 2018-05-31 | 2018-05-31 | Modularized computer system and computing core board thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107118824A TWI678624B (en) | 2018-05-31 | 2018-05-31 | Modularized computer system and computing core board thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI678624B true TWI678624B (en) | 2019-12-01 |
TW202004507A TW202004507A (en) | 2020-01-16 |
Family
ID=69582530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107118824A TWI678624B (en) | 2018-05-31 | 2018-05-31 | Modularized computer system and computing core board thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI678624B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200915876A (en) * | 2007-09-21 | 2009-04-01 | Yuan High Tech Dev Co Ltd | Surveillance apparatus capable of receiving TV signal |
TWM470974U (en) * | 2013-04-12 | 2014-01-21 | Aaeon Technology Inc | Computer system compatible with different processor module interface |
US20140075169A1 (en) * | 2012-09-07 | 2014-03-13 | Apple Inc. | Accessory booting over usb |
US20140229650A1 (en) * | 2012-05-08 | 2014-08-14 | Entegra Technologies, Inc | Reconfigurable Modular Computing Device |
-
2018
- 2018-05-31 TW TW107118824A patent/TWI678624B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200915876A (en) * | 2007-09-21 | 2009-04-01 | Yuan High Tech Dev Co Ltd | Surveillance apparatus capable of receiving TV signal |
US20140229650A1 (en) * | 2012-05-08 | 2014-08-14 | Entegra Technologies, Inc | Reconfigurable Modular Computing Device |
US20140075169A1 (en) * | 2012-09-07 | 2014-03-13 | Apple Inc. | Accessory booting over usb |
TWM470974U (en) * | 2013-04-12 | 2014-01-21 | Aaeon Technology Inc | Computer system compatible with different processor module interface |
Also Published As
Publication number | Publication date |
---|---|
TW202004507A (en) | 2020-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9959241B2 (en) | System and method for accessory device architecture that passes via intermediate processor a descriptor when processing in a low power state | |
US10101919B2 (en) | Chipset and server system using the same | |
US7908417B2 (en) | Motherboard system, storage device for booting up thereof and connector | |
US20190286590A1 (en) | Cpld cache application in a multi-master topology system | |
US10437762B2 (en) | Partitioned interconnect slot for inter-processor operation | |
US20160306634A1 (en) | Electronic device | |
US20200341929A1 (en) | Multi-endpoint device sideband communication system | |
WO2024103829A1 (en) | Port configuration method, component, and hard disk expansion apparatus | |
US7080164B2 (en) | Peripheral device having a programmable identification configuration register | |
US9946552B2 (en) | System and method for detecting redundant array of independent disks (RAID) controller state from baseboard management controller (BMC) | |
US11341076B2 (en) | Hot-plugged PCIe device configuration system | |
RU183879U1 (en) | Processor module | |
TWI678624B (en) | Modularized computer system and computing core board thereof | |
US11204775B2 (en) | Automated bios platform configuration system | |
TWI639087B (en) | Computing system and main board thereof | |
CN115905072A (en) | Computer system, control method based on PCIe device and related device | |
US7496747B2 (en) | Redundant link mezzanine daughter card | |
EP2998871B1 (en) | Portable device and control method therefor | |
US11803493B2 (en) | Systems and methods for management controller co-processor host to variable subsystem proxy | |
TWI706258B (en) | A computing device | |
KR101265233B1 (en) | Production and testing the initial storage host bus adapter | |
TWI659295B (en) | Server and initialization method in a booting server process | |
TWM524505U (en) | A motherboard device and an electronic device installed the same | |
TWI567566B (en) | Electronic device | |
CN115834369A (en) | Server network configuration method and system |