CN106569973B - Serial Peripheral Interface (SPI) multiplexing method and communication system - Google Patents
Serial Peripheral Interface (SPI) multiplexing method and communication system Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The present invention relates to a kind of Serial Peripheral Interface (SPI) multiplexing methods, more than two peripheral hardwares are connected by Serial Peripheral Interface (SPI) suitable for the host with Serial Peripheral Interface (SPI), to transmit data between host and peripheral hardware.Pass through the PWM output mode of MCU timer, output passes through the preset phase difference of connection peripheral hardware quantity institute quantification and the waveform of duty ratio respectively in a PWM cycle, it is exported by chip selection signal line to the enabled pin of corresponding peripheral hardware, gate corresponding peripheral hardware, in each peripheral hardware gating time, the host and the corresponding peripheral hardware carry out data transmission.The method is participated in without MCU software, by the SPI multiplexing technology of hardware controls chip selection signal, is realized the application of high speed, more SPI, can not be selected by software control piece for certain applications, realize that the multiplexing of SPI provides solution.The invention further relates to a kind of communication system, which realizes the transmission of data by above-mentioned SPI multiplexing method.
Description
Technical field
The present invention relates to technical field of data transmission, more particularly to a kind of Serial Peripheral Interface (SPI) multiplexing method and communication system
System.
Background technique
SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) is a kind of synchronous serial Peripheral Interface,
Host can be made to be communicated with various peripheral equipments by serial mode to exchange information.The interface generally uses 4 lines: string
Row clock line (SCLK), host input/slave output data line MISO, host output/slave input data line MOSI and low electricity
Put down effective slave selection line CS.SPI interface is with its superior performance, few signal wire (most 4 lines, minimum 2 lines)
It is widely used in various occasions.In point-to-point communication, SPI interface does not need to be addressed to operate, and logical for full duplex
Letter, it appears be simple and efficient.In multiple systems from device, independent enable signal, traditional method each are needed from device
In, by software control each from the enable signal of device, it is easy to realize the multiplexing of SPI.But software control slave makes
Energy signal realizes that the mode of SPI multiplexing is unable to satisfy demand in some occasions, for example requires the control speed to slave enable signal
In application of the degree less than 1uS, just it cannot achieve by software control.
Summary of the invention
Based on this, it is necessary to for the problem that certain applications can not be selected by software control piece, realize SPI multiplexing,
A kind of Serial Peripheral Interface (SPI) multiplexing method and communication system are provided.
A kind of Serial Peripheral Interface (SPI) multiplexing method passes through Serial Peripheral Interface (SPI) suitable for the host with Serial Peripheral Interface (SPI)
More than two peripheral hardwares are connected, to transmit data between host and peripheral hardware, comprising:
It is pulse width modulation output mode by the timer setting of host, and the week of pulse width modulating signal is set
Phase；
According to the peripheral hardware quantity of connection, quantity, the modulation of each pulse width of the pulse width modulating signal of output are determined
The phase difference of the duty ratio of signal and every two adjacent pulse width modulating signal；
The original levels and initial phase of each pulse width modulating signal are set, the pulse width modulation of timer is started
Output mode；
Each pulse width modulating signal is passed through chip selection signal line respectively to export to the enabled pin of corresponding peripheral hardware；
According to the original levels and initial phase of each pulse width modulating signal, modulates and believe in each pulse width
Number low level time in, the host and the corresponding peripheral hardware carry out data transmission.
The quantity of the pulse width modulating signal is equal to the peripheral hardware quantity of the connection in one of the embodiments,.
The duty ratio calculation formula of each pulse width modulating signal is in one of the embodiments,
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection.
The phase difference calculating formula of every two adjacent pulse width modulating signal is in one of the embodiments,
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware number of connection
Amount.
The original levels and initial phase according to each pulse width modulating signal in one of the embodiments,
Position, in the low level time of each pulse width modulating signal, the host and the corresponding peripheral hardware carry out data transmission, packet
It includes:
In the low level time of each pulse width modulating signal, the chip selection signal line of the host exports low electricity
It puts down to the enabled pin of the corresponding peripheral hardware, gates the corresponding peripheral hardware；
In the corresponding peripheral hardware gating time, the host and the corresponding peripheral hardware carry out data transmission.
A kind of communication system is connect including host and by Serial Peripheral Interface (SPI) with the host more than two outer
If the host includes timer,
The timer is configured as pulse width modulation output mode, exports under the pulse width modulation output mode
The phase of the quantity of signal, the duty ratio of each pulse width modulating signal and every two adjacent pulse width modulating signal
Difference is determined according to the peripheral hardware quantity of connection；
The host is configured as respectively passing through each pulse width modulating signal chip selection signal line and exports to corresponding outer
If enabled pin and according to the original levels and initial phase of each pulse width modulating signal, in each pulse width
In the low level time of modulated signal, carry out data transmission with the corresponding peripheral hardware.
The quantity of the pulse width modulating signal of the output is equal to the peripheral hardware of the connection in one of the embodiments,
Quantity.
The calculation formula of the duty ratio of each pulse width modulating signal is in one of the embodiments,
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection.
The phase difference calculating formula of every two adjacent pulse width modulating signal is in one of the embodiments,
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware number of connection
Amount.
Above-mentioned Serial Peripheral Interface (SPI) multiplexing method and communication system pass through PWM (the Pulse Width of MCU timer
Modulation, pulse width modulation) output mode, output is true by connected peripheral hardware quantity respectively in a PWM cycle
The preset phase difference of fixed number amount and the waveform of duty ratio are exported by chip selection signal line to the enabled pin of corresponding peripheral hardware, gating
Corresponding peripheral hardware, in each peripheral hardware gating time, the host and the corresponding peripheral hardware carry out data transmission.It is fixed being provided with
When the PWM output mode of device, under PWM mode after the parameters such as the phase difference of waveform and duty ratio, remaining step is all that hardware is automatic
It completes, is participated in without MCU software.By the SPI multiplexing technology of hardware controls chip selection signal, high speed is realized, more SPI are answered
With can not be selected by software control piece for certain applications, realize that the multiplexing of SPI provides solution.
Detailed description of the invention
Fig. 1 is the multiplexing method flow chart of Serial Peripheral Interface (SPI) in one embodiment；
Fig. 2 is Serial Peripheral Interface (SPI) multiplexing method flow chart in another embodiment；
Fig. 3 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in one embodiment；
Fig. 4 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in another embodiment；
Fig. 5 is the waveform schematic diagram of Serial Peripheral Interface (SPI) multiplexing method in further embodiment；
Fig. 6 is the structural schematic diagram of communication system in one embodiment.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
As shown in Figure 1, in one embodiment, a kind of multiplexing method of Serial Peripheral Interface (SPI) is provided, this method comprises:
Step S100: being pulse width modulation output mode by the timer setting of host, and pulse width modulation is arranged
The period of signal.
Wherein, pulse width modulation (Pulse Width Modulation, PWM) is that a kind of pair of analog signal level carries out
Digitally coded method.The spike train that each pulse width is equal is as PWM waveform, by the period for changing spike train
The width or duty ratio that with frequency modulation, can change pulse can make voltage and frequency coordination using suitable control method with pressure regulation
Variation.Can by adjusting the period of PWM, the duty ratio of PWM and achieve the purpose that control charging current.
Step S110: according to the peripheral hardware quantity of connection, the quantity of the pulse width modulating signal of determining output, each pulse
The phase difference of the duty ratio of bandwidth modulation signals and every two adjacent pulse width modulating signal.
Wherein, according to the peripheral hardware quantity of connection, the parameter of corresponding pulse-width-modulated mode, including pulse width are determined
The number of output of modulated signal, the duty ratio of each pulse width modulating signal and every two adjacent pulse width modulation letter
Number phase difference.The setting of above-mentioned parameter, so that pulse width modulating signal is corresponding with the peripheral hardware of connection, different parameters is set
It is fixed, different multiplexing effects may be implemented.
Step S120: the original levels and initial phase of each pulse width modulating signal are set, the arteries and veins of timer is started
Rush width modulated output mode.
Wherein, the original levels of each pulse width modulating signal and initial phase determine corresponding peripheral data
The sequencing of transmission starts the pulse width modulation output mode of timer, subsequent step after the completion of above-mentioned parameter is respectively provided with
Suddenly it can be automatically performed by hardware, the participation without micro-control unit software.
Step S130: by each pulse width modulating signal pass through respectively chip selection signal line export it is enabled to corresponding peripheral hardware
Pin.
Wherein, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus system is a kind of synchronization
Serial Peripheral Interface (SPI), it can be such that MCU is communicated in a serial fashion with various peripheral equipments to exchange information.The interface is general
Use 4 lines: serial time clock line (SCLK), host input/slave output data line MISO, host output/slave input data
The line MOSI and effective peripheral hardware selection line CS of low level.By peripheral hardware selection line CS, each pulse width modulating signal is distinguished
It exports to the enabled pin of corresponding peripheral hardware.
Step S140: according to the original levels and initial phase of each pulse width modulating signal, in each pulse
In the low level time of bandwidth modulation signals, the host and the corresponding peripheral hardware carry out data transmission.
Wherein, after the enabled interface of each peripheral hardware is connected to the corresponding peripheral hardware selection line CS of host, the peripheral hardware of host
Selection line CS output pulse width modulation waveform, the relevant parameter of the waveform have preset, have been modulated according to pulse width
Waveform, in the low level time of each waveform, host carries out data exchange with the corresponding peripheral hardware, realizes data transmission.
As shown in Fig. 2, in one embodiment, step S140 includes:
Step S142: in the low level time of each pulse width modulating signal, the chip selection signal of the host
Line exports the enabled pin of low level to the corresponding peripheral hardware, gates the corresponding peripheral hardware；
Step S144: in the corresponding peripheral hardware gating time, the host and the corresponding peripheral hardware carry out data transmission.
Wherein, the enable signal of peripheral hardware is that low level is effective, in the low level time of each pulse width modulating signal,
Peripheral hardware corresponding with the pulse-modulated signal is strobed, at this point, host carries out data transmission with the peripheral hardware, and continues to that pulse is wide
Until degree signal becomes high level.After the pulse width modulating signal becomes high level, Selection of chiller and another pulse are wide
Degree modulated signal is that low level peripheral hardware carries out data transmission, to realize that the data between a host and multiple peripheral hardwares are handed over
It changes, that is, the multiplexing of SPI.
As shown in figure 3, for waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of timer
The quantity of the pulse width modulating signal of output mode output is equal to the peripheral hardware quantity of connection, at this point, each pulse width is modulated
The duty ratio of signal can be calculated by following formula
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection；Every two pulse
The phase difference of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware number of connection
Amount.From above-mentioned calculation formula: when the quantity of pulse width modulating signal is equal to the peripheral hardware quantity of the connection, at one
In PWM cycle, the data of host are divided into n equal part (n indicates peripheral hardware quantity and is more than or equal to 2), in the low of each pwm signal
In level time, host peripheral hardware corresponding with pwm signal carries out data exchange, and n parts of data are transmitted to outside n to realize
If realizing the multiplexing of SPI.
As shown in figure 4, for waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of timer
The quantity of the pulse width modulating signal of output mode output is equal to the peripheral hardware quantity of connection, but duty ratio is less thanAt this point,
Assuming that the duty ratio of each pulse width modulating signal can be calculated by following formula
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection；Every two pulse
The phase difference of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware number of connection
Amount.From above-mentioned calculation formula: when the quantity of pulse width modulating signal is equal to the peripheral hardware quantity of the connection, keeping every
The phase difference of two pulse width modulating signals is constant, and duty ratio becomesAt this point, the transmission of data becomes discontinuous
, i.e., occur between every two adjacent peripheral hardwareThe data-transmission interruptions of a duty cycle time, if in this break period
Data are invalid data, then can realize the screening of data by data-transmission interruptions, valid data are transmitted, and invalid number
According to by Transmission, without transmission, to realize the maximization of data transmission quality, the data for guaranteeing that peripheral hardware receives are equal
For valid data.
As shown in figure 5, for waveform schematic diagram in one embodiment.In the present embodiment, the pulse width modulation of timer
The quantity of the pulse width modulating signal of output mode output is greater than the peripheral hardware quantity of connection, at this time, it is assumed that connection peripheral hardware quantity
Quantity for n, the pulse width modulating signal of output is 2n, then the duty ratio of each pulse width modulating signal can be by following public affairs
Formula calculates
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection；Every two pulse
The phase difference of bandwidth modulation signals can be calculated by following formula
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware number of connection
Amount.Known to above-mentioned calculation formula: since the duty ratio of each pulse width modulating signal becomesEvery two pulse width
The phase difference variable of modulated signal isAt this point, the first half of a PWM cycle carries out data transmission, latter half data
Transmission can form the biography of half PWM cycle by the data transfer mode among two cycle data transfers
Defeated interruption, so that the delay of two period intermediate data transmission is realized, likewise, the screening of data can also be realized.
As shown in fig. 6, in one embodiment, providing a kind of communication system, which includes: host 10 and leads to
Crossing peripheral hardware 20,30 and 40 that Serial Peripheral Interface (SPI) connect with host 10, (quantity of the peripheral hardware is two or more, in the present embodiment
By taking three peripheral hardwares as an example), host 10 includes timer 100,
Timer 100 is configured as pulse width modulation output mode, exports under the pulse width modulation output mode
The phase of the quantity of signal, the duty ratio of each pulse width modulating signal and every two adjacent pulse width modulating signal
Difference is determined according to the peripheral hardware quantity of connection；
Host 10 is configured as respectively passing through each pulse width modulating signal chip selection signal line and exports to corresponding peripheral hardware
Enabled pin and according to the original levels and initial phase of each pulse width modulating signal, in each pulse width tune
In the low level time of signal processed, carry out data transmission with the corresponding peripheral hardware.
In one embodiment, the number of the pulse width modulating signal of the pulse width modulation output mode output of timer
Amount is equal to the peripheral hardware quantity of connection, at this point, passing through formulaWithEach pulse width modulation is calculated
The duty ratio η of signal is 66.67%；The phase difference φ of every two pulse width modulating signal is 120 °.Therefore, at one
In PWM cycle, the data of host are divided into 3 equal parts, it is assumed that the original levels of the PWM output signal corresponding to IO1 are low level,
Initial phase is 0, and data transmitted waveform schematic diagram is as shown in Figure 3.In the preceding one third period of PWM cycle, pwm signal gating
Peripheral hardware 20, host 10 carry out data transmission with peripheral hardware 20；In the intermediate one third period of PWM cycle, pwm signal gates peripheral hardware
30, host 10 carries out data transmission with peripheral hardware 30；In the rear one third period of PWM cycle, pwm signal gates peripheral hardware 40, main
Machine 10 carries out data transmission with peripheral hardware 40.After a PWM cycle, the data that host 10 transmits in the period are just respectively allocated to
In three peripheral hardwares 20,30 and 40, to realize the multiplexing of data transmission by SPI interface.Correspondingly, adjustable duty ratio reaches
To data screening, the functions such as transmission delay, specific method is explained in the embodiment of Serial Peripheral Interface (SPI) multiplexing method
It states, details are not described herein again.
Above-mentioned Serial Peripheral Interface (SPI) multiplexing method and communication system, by the PWM output mode of MCU timer, at one
The waveform for exporting corresponding with connection peripheral hardware quantity preset phase difference and duty ratio in PWM cycle respectively, passes through chip selection signal
Line is exported to the enabled pin of corresponding peripheral hardware, gates corresponding peripheral hardware, in each peripheral hardware gating time, the host and described
Corresponding peripheral hardware carries out data transmission.The phase difference and duty of waveform in the case where being provided with the PWM output mode of timer, PWM mode
Than etc. after parameters, remaining step is all that hardware is automatically performed, and is participated in without MCU software.Pass through the SPI of hardware controls chip selection signal
Multiplexing technology realizes the application of high speed, more SPI, can not be selected by software control piece for certain applications, realize SPI's
Multiplexing provides solution.Further, by the way that different duty ratios is arranged, data screening may be implemented, data transmission is prolonged
When etc. functions so that the transmission of data is more accurate.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (7)
1. a kind of Serial Peripheral Interface (SPI) multiplexing method is connected suitable for the host with Serial Peripheral Interface (SPI) by Serial Peripheral Interface (SPI)
More than two peripheral hardwares are connect, to transmit data between host and peripheral hardware characterized by comprising
It is pulse width modulation output mode by the timer setting of host, and the period of pulse width modulating signal is set；
According to the peripheral hardware quantity of connection, the quantity of the pulse width modulating signal of determining output, each pulse width modulating signal
Duty ratio and every two adjacent pulse width modulating signal phase difference；
The original levels and initial phase of each pulse width modulating signal are set, and described two adjacent pulse widths modulate letter
Number phase difference calculating formula be
Or
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware quantity of connection；
Start the pulse width modulation output mode of timer；
Each pulse width modulating signal is passed through chip selection signal line respectively to export to the enabled pin of corresponding peripheral hardware；
The original levels and initial phase of each pulse width modulating signal determine corresponding peripheral data transmission
Sequencing；
According to the original levels and initial phase of each pulse width modulating signal, in each pulse width modulating signal
In low level time, the host and the corresponding peripheral hardware carry out the data transmission.
2. Serial Peripheral Interface (SPI) multiplexing method according to claim 1, which is characterized in that the pulse width modulating signal
Quantity be equal to the connection peripheral hardware quantity.
3. Serial Peripheral Interface (SPI) multiplexing method according to claim 2, which is characterized in that each pulse width modulating signal
Duty ratio calculation formula be
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection.
4. Serial Peripheral Interface (SPI) multiplexing method according to claim 1, which is characterized in that described according to each pulse
The original levels and initial phase of bandwidth modulation signals, in the low level time of each pulse width modulating signal, the master
Machine and the corresponding peripheral hardware carry out data transmission, comprising:
In the low level time of each pulse width modulating signal, the chip selection signal line output low level of the host is extremely
The enabled pin of the corresponding peripheral hardware gates the corresponding peripheral hardware；
In the corresponding peripheral hardware gating time, the host and the corresponding peripheral hardware carry out data transmission.
5. a kind of communication system, including host and the more than two peripheral hardwares being connect by Serial Peripheral Interface (SPI) with the host,
The host includes timer,
The timer is configured as pulse width modulation output mode, output signal under the pulse width modulation output mode
Quantity, the duty ratio of each pulse width modulating signal and every two adjacent pulse width modulating signal phase difference root
It is determined according to the peripheral hardware quantity of connection；
The phase difference calculating formula of described two adjacent pulse width modulating signals is
Or
Wherein, Δ φ indicates that the phase difference of every two adjacent pulse width modulating signal, n indicate the peripheral hardware quantity of connection；
The host is configured as respectively passing through each pulse width modulating signal chip selection signal line and exports to corresponding peripheral hardware
Enabled pin and according to the original levels and initial phase of each pulse width modulating signal, is modulated in each pulse width
In the low level time of signal, carry out data transmission with the corresponding peripheral hardware；
The original levels and initial phase of each pulse width modulating signal determine corresponding peripheral data transmission
Sequencing.
6. communication system according to claim 5, it is characterised in that: the quantity of the pulse width modulating signal of the output
Equal to the peripheral hardware quantity of the connection.
7. communication system according to claim 6, which is characterized in that the meter of the duty ratio of each pulse width modulating signal
Calculating formula is
Wherein, η indicates the duty ratio of each pulse width modulating signal, and n indicates the peripheral hardware quantity of connection.
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| US10313157B2 (en) * | 2017-04-25 | 2019-06-04 | Realtek Semiconductor Corp. | Apparatus and method for multiplexing multi-lane multi-mode data transport |
| CN107480090B (en) * | 2017-08-01 | 2020-08-04 | 晶晨半导体(上海)股份有限公司 | Circuit and method for realizing GPIO function on serial peripheral interface device |
| CN107967227A (en) * | 2017-12-22 | 2018-04-27 | 苏州国芯科技有限公司 | A kind of communication means and SPI hosts, SPI slaves based on SPI |
| CN110083572A (en) * | 2019-04-30 | 2019-08-02 | 京东方科技集团股份有限公司 | Chip, the control method based on chip and system, computer readable storage medium |
| CN110471865B (en) * | 2019-08-15 | 2021-04-02 | 绵阳市维博电子有限责任公司 | Method for realizing communication between controller and driver by simulating SPI communication |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949164A (en) * | 2006-07-10 | 2007-04-18 | 王耀 | Time-division multiplexing IC card interface equipment |
| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| CN104408002A (en) * | 2014-12-05 | 2015-03-11 | 上海斐讯数据通信技术有限公司 | Serial port master-slave communication control system and method |
| CN104467378A (en) * | 2014-12-12 | 2015-03-25 | 苏州慧科电气有限公司 | Modular multi-level converter trigger pulse generating system and method |
| CN104866054A (en) * | 2014-02-26 | 2015-08-26 | 鸿富锦精密工业（深圳）有限公司 | Polyphase source protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007051657A1 (en) * | 2007-10-26 | 2009-04-30 | Robert Bosch Gmbh | Communication system with a CAN bus and method for operating such a communication system |
-
2016
- 2016-10-25 CN CN201610938535.2A patent/CN106569973B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949164A (en) * | 2006-07-10 | 2007-04-18 | 王耀 | Time-division multiplexing IC card interface equipment |
| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| CN104866054A (en) * | 2014-02-26 | 2015-08-26 | 鸿富锦精密工业（深圳）有限公司 | Polyphase source protection circuit |
| CN104408002A (en) * | 2014-12-05 | 2015-03-11 | 上海斐讯数据通信技术有限公司 | Serial port master-slave communication control system and method |
| CN104467378A (en) * | 2014-12-12 | 2015-03-25 | 苏州慧科电气有限公司 | Modular multi-level converter trigger pulse generating system and method |
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