CN107463474A

CN107463474A - A kind of high-speed reconfigurable test platform

Info

Publication number: CN107463474A
Application number: CN201710864636.4A
Authority: CN
Inventors: 何建樑; 张泽渺
Original assignee: CHENGDU XUANJILI COMMUNICATION TECHNOLOGY Co Ltd
Current assignee: CHENGDU XUANJILI COMMUNICATION TECHNOLOGY Co Ltd
Priority date: 2017-09-22
Filing date: 2017-09-22
Publication date: 2017-12-12

Abstract

The invention discloses a kind of high-speed reconfigurable test platform.It includes DSP Processor, fpga chip, 10GE interface chips, the first DDR3 memories, the 2nd DDR3 memories, COMe connectors, power circuit and clock circuit.The test data that 10GE interface chips are used to send optical module is XFI interfaces by SFI interface conversions, and test data includes DSP programs and FPGA programs；DSP Processor is used to run DSP program programs, and by FPGA program caches to the first DDR3 memories, and after caching, load FPGA programs, FPGA programs are sent to fpga chip；Fpga chip is configured for running FPGA programs, and the data interacted between I/O interfaces and DSP Processor are carried out into logical transition according to FPGA programs.The present invention can take into account cost and performance, and possess open and compatibility.

Description

A kind of high-speed reconfigurable test platform

Technical field

The present invention relates to technical field of measurement and test, more particularly to a kind of high-speed reconfigurable test platform.

Background technology

For a long time, ground checkout equipment industry is divided into special test equipment and general purpose test equipment, general purpose test equipment Using NI companies as representative, based on a certain industry control machine platform such as PXI platform developments standard I/O module.Domestic each military project research institute all exists Demand is proposed towards ATE (automated test device) direction.

2005, Agilent company and VXI companies were proposed LXI standards jointly.LXI(LAN eXtension for Instrumentation) it is a kind of modular testing platform standard based on LAN, it has merged the high property of GPIB instruments The high-throughput of energy, the small size of VXI, PXI instrument and LAN, and consider that the instruments such as timing, triggering, cooling, electromagnetic compatibility will Ask.The purpose is to make full use of the newest fruits and PC standard I/O abilities of current measuring technology, set up flexibly, efficiently, can Lean on, modular test platform.LXI instruments are based on IEEE802.3, TCP/IP, network-bus, web browser, IVI-COM The new instrument of driver, clock synchronization protocol (IEEE1588) and standard module size.

2009 to 2010, Agilent tissue set up AXIe alliances, and releases AXIe1.0 infrastructures of knowing clearly Standard and AXIe3.1 semiconductor test technologies.AXIe compatibilities PXI.It with reference to AdvanceTCA, PXI, LXI at the beginning of formulation It is the open-standards based on AdvanceTCA with the existing standard such as IVI, its target is to create one by various members The ecosystem of device, product and system composition, promotes the development of all purpose instrument and semiconductor test.AXIe standards can provide most Big scalability, meet the needs of various platforms, including implement porter stack system, modular system, semiconductor ATE systems System, and workbench and module plug-in.

AXIe can make full use of rack space, there is provided higher performance, more powerful scalability, outstanding module Property and flexibility, can easily be carried out with PXI, LXI and IVI integrated and substantially reduce development cost and component costs.AXIe bags Two kinds of interfaces of PCIe and LAN are included, are LXI and PXI standards optimal supplement.AXIe instruments phase compared with virtual PXI or LXI instruments Seemingly, can Seamless integration- in system and provide very high performance.

Basis of the AdvanceTCA PICMG3.0 standards as AXIe standards, it is a kind of use large scale circuit proved The Open Architecture structure of plate.

AXIe has higher scalability, and user can carry out integration instrument using 1 to 14 slot and one or more cabinets Device, it might even be possible to by adapter using embedded PXI or CPCI modules come integral instrument.AdvanceTCA can also be provided simultaneously Single track power management and powerful heat sinking function, it is the ideal chose of high-power applications.AdvanceTCA supports LAN's and PCIe Data optical fiber framework, designed available for virtual LXI and PXI.

AXIe instrument modules based on PCIe can serve as control computer as PCIe hardware devices, its working method with PXI instrument modules are the same.AXIe instrument modules based on LAN can serve as control computer, its work side as network node Formula is as PXI instrument modules.

Therefore, in the case where no any a company has the ability to corner the market with technology, using compatible AXIe standards Open platform, can make itself product that there is more preferable adaptability.

Because the data that test fields of measurement needs to exchange at present are more and more, it is necessary to higher and higher data/address bus interconnection Test module, standard newest at present have evolved to the test cabinet standard based on high-speed PCI e buses and 10GE interconnection, come Support the mass data interaction demand of test fields of measurement.

CPCI platforms are relatively low in performance at present, it is difficult to meet the platforms such as high-performance high-speed demand, VPX, AdvanceTCA Although performance is very strong, price is too high, and the narrow and small situation in market is necessarily faced as platform development.It would therefore be highly desirable to develop A kind of cost is cheap, and performance is higher, has open and compatibility test equipment, to meet increasingly keen competition and city Field demand.

The content of the invention

The present invention solves the technical problem of a kind of high-speed reconfigurable test platform is provided, cost and property can be taken into account Can, and possess open and compatibility.

In order to solve the above technical problems, one aspect of the present invention is：A kind of high-speed reconfigurable test is provided Platform, including DSP Processor, fpga chip, 10GE interface chips, the first DDR3 memories, the 2nd DDR3 memories, COMe connect Connect device, power circuit and clock circuit；The DSP Processor and the fpga chip are connected with the COMe connectors, described First DDR3 memories and the fpga chip are connected with the DSP Processor, the 2nd DDR3 memories and the FPGA Chip is connected, and the DSP Processor be connected by the 10GE interface chips with outside optical module, COMe connectors and outside The I/O interfaces connection of portion's mainboard, the power circuit are used to supply for the DSP Processor, fpga chip and 10GE interface chips Electricity, the clock circuit are used to provide clock for the DSP Processor and fpga chip；The 10GE interface chips are used for institute The test data for stating optical module transmission by SFI interface conversions is XFI interfaces, and the test data includes DSP programs and FPGA journeys Sequence；The DSP Processor is used to run the DSP programs program, and the FPGA program caches to the first DDR3 are deposited Reservoir, and after caching, the FPGA programs are loaded from the first DDR3 memories, by the FPGA programs send to The fpga chip；The fpga chip is used to run the FPGA programs and configured, and according to the FPGA programs by institute State the data interacted between I/O interfaces and the DSP Processor and carry out logical transition.

Wherein, the DSP Processor is connected with the fpga chip by PCIE X2 buses.

The beneficial effects of the invention are as follows：

1. the AXIe standards of AXI alliances can be met；

2. the test application extension of new EBI and high speed bus interface can be met, improving performance and processing energy Power, and using unified standard design；

3. the hardware cost of production phase can be reduced.

Brief description of the drawings

Fig. 1 is the configuration diagram of the high-speed reconfigurable test platform of the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

It is the configuration diagram of the high-speed reconfigurable test platform of the embodiment of the present invention refering to Fig. 1.The high speed of the present embodiment Reconstruction test platform includes DSP Processor 10, fpga chip 20,10GE interface chips 30, the first DDR3 memories 40, second DDR3 memories 50, COMe connectors 60, power circuit 70 and clock circuit 80.

DSP Processor 10 and fpga chip 20 are connected with COMe connectors 60, the first DDR3 memories 40 and fpga chip 20 are connected with DSP Processor 10, and the 2nd DDR3 memories 50 are connected with fpga chip 20, and DSP Processor 10 passes through 10GE interfaces Chip 30 is connected with outside optical module, and COMe connectors 60 are connected with the I/O interfaces of outside mainboard, and power circuit 70 is for being DSP Processor 10, fpga chip 20 and 10GE interface chips 30 are powered, and it is DSP Processor 10 and FPGA that clock circuit 80, which is used for, Chip 20 provides clock.

The test data that 10GE interface chips 30 are used to send optical module is XFI interfaces by SFI interface conversions, tests number According to including DSP programs and FPGA programs.

DSP Processor 10 is used to run DSP program programs, and by FPGA program caches to the first DDR3 memories 10, and After caching, FPGA programs are loaded from the first DDR3 memories 10, FPGA programs are sent to fpga chip 20.Due to The data volume of FPGA programs is generally larger, and therefore, the memory capacity of the first DDR3 memories 10 is preferably 2GB.

Fpga chip 20 is used to run FPGA programs and configured, and according to FPGA programs by I/O interfaces and DSP Processor The communication data of interaction carries out logical transition between 10, and the communication data after conversion is cached to the 2nd DDR3 memories 50. Because the data volume of communication data is generally smaller, therefore, the memory capacity of the 2nd DDR3 memories 50 is preferably 256MB.

In the present embodiment, DSP Processor 10 is preferably the model 66AK2E05 of TI companies SOC.

VPX/ATCA/LXI (e) modules and equipment are built using the high-speed reconfigurable test platform of the present embodiment, are based on ISCSI network storage protocols can realize that maximum more than data block between 800MB/S device networks and exchange files speed, is far above The platform Front Side Bus message transmission rate such as PXI/CPCI/LXI；The Front Side Bus of system more matches (preceding with back side bus speed Bus PC IeX2 is held to provide theoretical 1GB/S message transmission rates, back-end network Bus Speed 10GE networks can provide theory 1.25GB/S message transmission rates, remove protocol overhead, and the two valid data transmission rate approaches), the front and back end bus of matching Speed is that data transfer simplifies Software for Design, improves processor efficiency；General Interface design simplifies application software and set Meter, for virtual instrument design provide conveniently, unified interface, be easy to design ATE automatization test systems, by FPGA outside Expansion I/O interfaces synchronize the instrument and equipment with simple 10GE/PCIe interfaces, and its clock is synchronous up to nanosecond；Compare In traditional tester and device control module, cost is lower, and configuration is more flexible (can load and debug by network), and Compatible traditional instrument and equipment interface (network interface).

Embodiments of the invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this hair The equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills Art field, is included within the scope of the present invention.

Claims

A kind of 1. high-speed reconfigurable test platform, it is characterised in that including DSP Processor, fpga chip, 10GE interface chips, First DDR3 memories, the 2nd DDR3 memories, COMe connectors, power circuit and clock circuit；The DSP Processor and institute State fpga chip to be connected with the COMe connectors, the first DDR3 memories and the fpga chip and the DSP processing Device is connected, and the 2nd DDR3 memories are connected with the fpga chip, and the DSP Processor passes through the 10GE interface chips It is connected with outside optical module, the COMe connectors are connected with the I/O interfaces of outside mainboard, and it is described that the power circuit, which is used for, DSP Processor, fpga chip and the power supply of 10GE interface chips, it is the DSP Processor and FPGA cores that the clock circuit, which is used for, Piece provides clock；

It is XFI interfaces by SFI interface conversions that the 10GE interface chips, which are used for the test data that the optical module is sent, described Test data includes DSP programs and FPGA programs；

The DSP Processor is used to run the DSP programs program, and the FPGA program caches to the first DDR3 are deposited Reservoir, and after caching, the FPGA programs are loaded from the first DDR3 memories, by the FPGA programs send to The fpga chip；

The fpga chip is used to run the FPGA programs and configured, and according to the FPGA programs by the I/O interfaces The data interacted between the DSP Processor carry out logical transition.
2. high-speed reconfigurable test platform according to claim 1, it is characterised in that the DSP Processor with it is described Fpga chip is connected by PCIE X2 buses.