CN107452722A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN107452722A CN107452722A CN201611197122.XA CN201611197122A CN107452722A CN 107452722 A CN107452722 A CN 107452722A CN 201611197122 A CN201611197122 A CN 201611197122A CN 107452722 A CN107452722 A CN 107452722A
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- tube core
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Abstract
半导体器件包括:第一管芯、接合至第一管芯从而形成接合界面的第二管芯、以及第一管芯的焊盘并且焊盘从第一管芯的聚合物层暴露。半导体器件还具有位于焊盘上并且在平行于第一管芯和第二管芯的堆叠方向的方向上从焊盘延伸的导电材料。在半导体器件中,导电材料延伸至顶面,顶面垂直地高于第二管芯的背侧,其中,背侧是与接合界面相对的表面。
Description
技术领域
本发明的实施例涉及半导体器件。
背景技术
涉及半导体器件的电子器件在我们的日常生活中不可或缺。随着电子技术的进步,电子设备变得更复杂,并涉及更大量的用于执行所期望的多功能性的集成电路。因此,电子设备的制造包括组件和处理的越来越多的步骤以及用于产生电子设备中的半导体器件的材料。因此,存在关于简化生产步骤、提高生产效率和对每个电子设备降低相关制造成本的连续需求。
在制造半导体器件的操作中,半导体器件装配有多个包括具有热性能差的各种材料的集成组件。如此,集成组件处于不期望的配置。不期望的配置会导致半导体器件的产量损失、组件之间的接合性差、裂纹的发展、组件的分层等。此外,半导体器件的组件包括有限数量并且因此成本高的各种金属材料。组件的不期望的配置和半导体器件的产量损失会进一步加剧材料浪费,并因此制造成本会增加。
由于涉及具有不同材料的更多不同组件和半导体器件的制造操作的复杂性增加,所以修改半导体器件的结构和改进制作操作存在更多的挑战。如此,对改进用于制造半导体的方法和解决上述缺陷存在连续需求。
发明内容
本发明的实施例提供了一种半导体器件,包括:第一管芯;第二管芯,连接至所述第一管芯,从而形成接合界面;所述第一管芯的焊盘,从所述第一管芯的聚合物层暴露;以及导电材料,位于所述焊盘上并且在平行于所述第一管芯和所述第二管芯的堆叠方向的方向上从所述焊盘延伸,并且所述导电材料延伸至顶面,所述顶面垂直地高于所述第二管芯的背侧,其中,所述背侧是与所述接合界面相对的表面。
本发明的另一实施例提供了一种三维(3D)半导体器件,包括:第一管芯;第二管芯,堆叠在所述第一管芯上方并且与所述第一管芯的导电结构垂直地接合;所述第一管芯的焊盘,通过所述第一管芯和所述第二管芯的接合与所述第二管芯电通信;以及导电材料,设置在所述焊盘上方,其中,所述导电材料从所述焊盘突出并且到达高于所述第二管芯的垂直层级。
本发明的又一实施例提供了一种半导体器件,包括:第一管芯;第二管芯,接合到所述第一管芯;衬底,位于所述第一管芯和所述第二管芯外部并且电连接至所述第一管芯和所述第二管芯,其中,所述第一管芯、所述第二管芯和所述衬底布置成垂直堆叠的方式;导电材料,从所述第一管芯的焊盘突出并且垂直地延伸至比所述第二管芯更高的层级,其中,所述第一管芯、所述第二管芯和所述衬底通过所述导电材料相互通信。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的半导体器件的示意图。
图2是根据一些实施例的具有导电层的半导体器件的示意图。
图3是根据一些实施例的具有焊盘的半导体器件的示意图。
图4是根据一些实施例的具有介电材料的半导体器件的示意图。
图5是根据一些实施例的具有穿孔的半导体器件的示意图。
图6是根据一些实施例的具有导电柱的半导体器件的示意图。
图7是根据一些实施例的具有另一管芯的半导体器件的示意图。
图8是根据一些实施例的焊盘暴露的半导体器件的示意图。
图9是根据一些实施例的具有聚合物层的半导体器件的示意图。
图10和图10A是根据一些实施例的具有要设置的导电材料的半导体器件的示意图。
图11和图11A是根据一些实施例的具有导电材料的半导体器件的示意图。
图12是根据一些实施例的接合有另一衬底的半导体器件的示意图。
图13是根据一些实施例的具有管芯的半导体器件的示意图。
图14是根据一些实施例的具有导电层的半导体器件的示意图。
图15是根据一些实施例的具有焊盘的半导体器件的示意图。
图16是根据一些实施例的具有介电材料的半导体器件的示意图。
图17是根据一些实施例的具有穿孔的半导体器件的示意图。
图18是根据一些实施例的具有导电柱的半导体器件的示意图。
图19是根据一些实施例的具有另一管芯的半导体器件的示意图。
图20是根据一些实施例的具有聚合物层的半导体器件的示意图。
图21是根据一些实施例的具有导电材料的半导体器件的示意图。
图22是根据一些实施例的接合有另一电子组件的半导体器件的示意图。
图23是根据一些实施例的接合有另一衬底的半导体器件的示意图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
导体被提供作为接合的半导体结构的电终端,以便通过导体与外部器件连接。示出制造实施例的中间阶段。讨论了实施例的变型。贯穿各个视图和示例性实施例中,相同的参考数字用于表示相同的元件。
参照图1,管芯100中包括衬底112和集成电路(图中未示出)。衬底112可以是半导体衬底,诸如块状硅衬底,或其它半导体材料,诸如III族、IV族和/或V族元素。在一些实施例中,衬底可以包括二氧化硅、氧化铝、蓝宝石、锗、砷化镓(GaAs)、硅和锗的合金或磷化铟(InP)。表面112a是衬底112的前侧并且包括半导体器件,诸如晶体管。互连结构120包括形成在其中的导电线和通孔(未示出),互连结构120形成在衬底112的前侧112a上并且连接到有源半导体器件。导电线和通孔可以由铜或铜合金形成,并且可以使用镶嵌工艺形成。在一些实施例中,导电线通过单镶嵌或双镶嵌操作形成,并且至少六至七层导电线包括在互连结构120中。互连结构120可以包括层间电介质(ILD)和在不同导电线之间的金属间电介质(IMD)。在一些实施例中,ILD或IMD包括介电材料,诸如氧化硅、氮化硅、氮氧化硅、低k介电材料或其他合适的介电材料和/或它们的组合。
在一些实施例中,通过沉积设置ILD或IMD。沉积可以是汽相沉积,包括诸如但不限于化学汽相沉积(CVD)和物理汽相沉积(PVD)的任何工艺。汽相沉积方法的实例包括热丝CVD、rf-CVD、激光CVD(LCVD)、共形金刚石涂层工艺、金属有机CVD(MOCVD)、溅射、热蒸发PVD、离子化金属PVD(IMPVD)、电子束PVD(EBPVD)、活性PVD、原子层沉积(ALD)、PECVD、HDPCVD、LPCVD等。在一些实施例中,通过旋涂设置ILD或IMD。互连结构120的顶部导电焊盘124至少从互连结构120的电介质部分地暴露。在整个说明书中,表面112b与表面112a相对并被称为衬底112的“背侧”。
参照图2,另一导电层130设置在互连焊盘124上。在另一实施例中,导电层130是可选的。导电层130的材料或组分可以不同于导电焊盘124。在一些实施例中,导电层130由铝或铝合金形成,并且可能比导电焊盘124更易受到含有氯或氟的蚀刻剂的损害。在一些实施例中,导电层130的材料选择标准是确保能够在导电层130和导电焊盘124之间形成欧姆接触。
参照图3,部分地去除导电层130以在前侧112a上方形成至少一个焊盘130a。焊盘130a还覆盖至少一个导电焊盘124,导电焊盘124暴露于互连结构120的电介质。焊盘130a与导电焊盘124直接接触,使得管芯100可通过焊盘130a与外部器件进行通信。在一些实施例中,自上而下视角,焊盘130a具有比导电焊盘124更大的尺寸。导电焊盘124从顶视图隐藏于焊盘130a之下。
参照图4,介电材料140设置在前侧112a上方。在一些实施例中,介电材料140覆盖导电焊盘124、焊盘130a和互连结构120的顶面并且与导电焊盘124、焊盘130a和互连结构120的顶面接触。在一些实施例中,介电材料140涂覆在前侧112a上方。在一些实施例中,介电材料140沉积在前侧112a上方。
沉积可以是汽相沉积,包括诸如但不限于化学汽相沉积(CVD)和物理汽相沉积(PVD)的任何工艺。汽相沉积方法的实例包括热丝CVD、rf-CVD、激光CVD(LCVD)、共形金刚石涂层工艺、金属有机CVD(MOCVD)、溅射、热蒸发PVD、离子化金属PVD(IMPVD)、电子束PVD(EBPVD)、活性PVD、原子层沉积(ALD)、PECVD、HDPCVD、LPCVD等。层104可以包括介电材料,诸如氧化硅、氮化硅、氧氮化硅、高k介电材料、低k介电材料、其他适合的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适合的高k介电材料和/或它们的组合。然而,这不是对本发明的限制。
参照图5,图案化介电材料140以包括果然穿孔142。在介电材料140下方的一些导电焊盘124经由穿孔142暴露。对介电材料140实施的图案化操作可以包括若干子操作。例如,光刻胶首先设置在介电材料140上方并且被图案化成所设计的掩模。部分介电材料140被光刻胶掩蔽。然后采用蚀刻操作以去除绝缘材料140的未掩蔽部分。
参照图6,导电材料填充穿孔142以形成导电柱145。在一些实施例中,以至少两个阶段填充导电材料。在第一阶段中,薄导电层共形地设置在穿孔142内。薄导电层是晶种层,并且可以包括使用CVD或PVD技术形成的Cu、Ti、Ta、TiN、TaN等。例如,在一个实施例中,薄导电层是包括Ti层的复合层,通过PVD工艺沉积至约的厚度。在第二阶段中,另一导电材料填充在晶种层上。填充导电材料可以是铜或铜合金并通过电镀操作填充。一些穿孔142可能由填充导电材料过填充,从而覆盖介电材料140。采用CMP操作以去除过量的填充材料并形成如图6所示的柱145。柱145延伸穿过介电材料140以提供用于外部器件的接触。
参照图7,另一管芯200垂直设置在衬底112的前侧112a上方。在一些实施例中,管芯200是从晶圆分割的半导体芯片。在设置在前侧112a上方之前,管芯200可以经历一系列的晶圆级半导体操作。例如,提供半导体晶圆,并在半导体衬底中形成有源和无源器件,诸如CMOS、二极管等。类似于互连件120的互连层220可以包括并设置在管芯200的有源表面上方。在互连件120的最上一层上,电介质240设置为钝化层以隔离湿气渗入互连层220,然而,一些导电焊盘224从介电层240暴露。然后管芯200可以从晶圆分割并重新定位在衬底112上方。导电柱245设置在暴露的导电焊盘224上并作为管芯200的电通信终端。导电柱245能够在分割操作之前或之后设置在暴露的导电焊盘224上。
在图7中,管芯200与管芯100接合。管芯200的表面朝向管芯100并且配置为与管芯100接合。第一表面230可包括导电焊盘224的暴露表面和介电层240的表面。管芯200与100之间的接合可以包括至少三种不同的接合类型。其中一种接合是金属至金属接合,例如,管芯200的导电柱245接合到管芯100的导电柱145。第二种类型是直接电介质至电介质接合,例如,在介电层140和介电层240之间的界面处观察到直接电介质至电介质接合。第三种类型是金属至电介质接合。第三种类型是在导电柱145和介电层240之间的界面或导电柱245和介电层140之间的界面上的金属至电介质接合。一旦管芯100与管芯200接合,通过导电柱145和导电柱245的连接而形成电通信路径。除了电连接,在管芯100和管芯200之间通过电介质至电介质接合或金属至电介质接合也形成机械连接。一旦管芯200与管芯100接合,在SEM下在管芯200与管芯100之间可观察到接合界面230。在一些实施例中,可以对横截面施加斜染以显示界面230。
参照图8,部分地去除介电层140以暴露焊盘130a。在一些实施例中,去除部分比焊盘130a的宽度小,以便使焊盘130a仍由介电层140部分覆盖。介电层140在焊盘130a处凹进并且使表面150暴露。
参照图9,聚合物层146可选择地设置在介电层140和管芯200上方。去除聚合物层146的部分,以使穿孔与介电层140的凹槽重叠。在一些实施例中,焊盘130a的表面150从介电层140和聚合物层146部分地暴露。在一些实施例中,暴露的表面150的宽度w在约10um和约100um之间。在一些实施例中,宽度w在约15um和约95um之间。在一些实施例中,宽度w在约25um和约85um之间。在一些实施例中,穿孔的宽度基本小于介电层140的凹槽的宽度。
在一些实施例中,聚合物层146具有在约2um和约15um之间的厚度h。在一些实施例中,聚合物层146具有在约3um和约13um之间的厚度h。在一些实施例中,聚合物层146具有在约4um和约11um之间的厚度h。
在一些实施例中,管芯200被聚合物层146覆盖。管芯200具有背侧232,背侧232是相对于接合界面230、被聚合物层146覆盖的表面。在一些实施例中,背侧232至少部分地从聚合物层146暴露。互连层220基本被聚合物层146围绕。在一些实施例中,互连层220被聚合物层146部分地围绕。可以选择光敏材料以形成聚合物层146。例如,聚酰亚胺被选择为旋涂在介电层140上方。在步进器或扫描仪中使用中间掩模,以通过在预定波长光下的曝光操作限定将转印至光敏材料的图案。曝光的光敏材料被进一步显影,使得去除光敏材料的一部分,以在光敏材料中形成穿孔或其他指定的图案。聚酰亚胺膜的实例包括Apical、Kapton、UPILEX、VTEC PI,、Norton TH和Kaptrex。在一些实施例中,诸如聚苯并恶唑(PBO)、苯并环丁烯(BCB)、有机硅、丙烯酸酯和环氧树脂的其它光敏材料也是适合的材料。
参照图10,导电材料155配置为设置在暴露的表面150上。可以存在一些其他层插入在导电材料155和暴露的表面150之间。在一些实施例中,凸块下金属化(UBM)设置在导电材料155和暴露的表面150之间,如图10A所示。在一些实施例中,导电材料155包括焊料材料,诸如Sn、Ag、Cu、Zn、Pb、Sb、Bi、In、Cd、Au、Cd、Si、Ge等的合金。
在一些实施例中,导电材料155通过设置在暴露的表面150上方的模版设置暴露的表面150,其中模版具有与暴露的表面150对准的穿孔。导电材料155是焊球状材料,并通过穿孔落下。导电材料155最终接合在暴露的表面150上。在一些实施例中,通过在暴露的表面150上焊接焊料材料而设置导电材料155。
在一些实施例中,在导电材料155接合在暴露的表面150后引入高温下的流动/回流操作。流动/回流操作的温度优选为足够高,以使焊球或焊膏加热以提高它们的流动性。
参照图11,导电材料155变形并填充聚合物层146中的穿孔。可以在导电材料155和焊盘130a之间形成共晶接合。导电材料155延伸穿过聚合物层146和介电层140中的穿孔。导电材料155也与焊盘130a的暴露的表面150接触。通过管芯100和200之间的接合,管芯200通过管芯100进一步与导电材料155电通信。因此,导电材料155是集成接合结构的导电终端,集成接合结构包括管芯100和管芯200。管芯200通过焊盘130a可进一步电连接至管芯100或管芯200外部的器件。
在一些实施例中,导电材料155过填充聚合物层146中的穿孔,并进一步覆盖聚合物层146的部分。导电材料155从焊盘130a的暴露的表面150延伸,然后转向横向并且沿着聚合物层146的顶面146a粘附。导电材料155的横向延伸在转折点155c结束并且随后向上改变,以形成与顶面146a相交的曲线。
曲线155a是导电材料155的外表面,并且配置为与集成接合半导体管芯结构外部的另一电子组件或电路接触。曲线155a与聚合物层146的顶面146a的交点处形成角度θ。θ值由导电材料155和聚合物层146之间的表面张力来确定。在图11中的实施例中,导电材料155被聚合物层146排斥并且角度θ小于约90度。在一些实施例中,角度θ小于约80度。在一些实施例中,角度θ是导电材料155和聚合物层146之间的润湿角。
导电材料155具有沿着平行于表面146a的方向测得的最大宽度D。在一些实施例中,最大宽度D为约50um和100um之间。在一些实施例中,最大宽度D为约100um和150um之间。在一些实施例中,最大宽度D为约100um和200um之间。在一些实施例中,最大宽度D为约200um和250um之间。在一些实施例中,最大宽度D为约250um和300um之间。在一些实施例中,最大宽度D为约50um和300um之间。在一些实施例中,最大宽度D大于约10um。
导电材料155从焊盘130a突出并继续沿着聚合物材料146的表面146a横向延伸。在一些实施例中,导电材料155的部分是半球形并且具有直径。在一些实施例中,该直径基本等于最大宽度D。
导电材料155具有顶面155e,其与表面150相对。导电材料155从表面150延伸到顶面155e。本发明中,导电材料155的延伸或突出方向被定义为基本平行于管芯100和管芯200的堆叠方向的方向。在此描述的方向也被定义为垂直方向。导电材料155的顶面155e处于高于管芯200的背侧232的垂直层级。
在一些实施例中,导电材料155是导体,诸如导电柱或微凸块。如在图11A中,导电材料155定义成柱形状。导电材料155从焊盘130a突出并垂直延伸到顶面155e。顶面155e比管芯200的表面(或背侧)232在垂直方向上更高。
参照图12,另一衬底500电连接至导电材料155。通过导电材料155,衬底500与管芯100或管芯200电通信。在一些实施例中,管芯100、管芯200和衬底500按垂直堆叠方式布置以形成三维(3D)半导体器件。
在一些实施例中,导电材料155设置在衬底112的背侧112b上。参照图13,提供了图1中的管芯100,且在图14中,导电层130设置在背侧112b上。衬底112还具有若干衬底通孔(TSV)134。在一些实施例中,绝缘层128设置在背侧112b和导电层130之间。
参照图15,部分地去除导电层130以在背侧112b上方形成至少一个焊盘130a。参照图16,介电材料140设置在背侧112b上方。在一些实施例中,介电材料140覆盖焊盘130a。在一些实施例中,介电材料140具有平面140a。
参照图17,图案化介电材料140以包括若干穿孔142以暴露TSV134的一端。对介电材料140实施的图案化操作可以包括若干子操作。例如,光刻胶首先设置在介电材料140上方并且被图案化成所设计的掩模。介电材料140的部分被光刻胶掩蔽。然后采用蚀刻操作以去除介电材料140的未掩蔽部分。
参照图18,导电材料填充穿孔142以形成导电柱145。在一些实施例中,以至少两个阶段填充导电材料。在第一阶段中,薄导电层共形地设置在穿孔142内。薄导电层可以包括使用CVD或PVD技术形成的Cu、Ti、Ta、TiN、TaN等。例如,在一个实施例中,薄导电层是包括Ti层的复合层,其通过PVD工艺沉积至约的厚度。在第二阶段中,另一导电材料填充在晶种层上。填充导电材料可以是铜或铜合金并且通过电镀操作填充。一些穿孔142可由填充导电材料过填充,从而介电材料140被覆盖。采用CMP操作以去除过量的填充材料并形成如图18所示的柱145。柱145延伸穿过介电材料140以提供用于外部器件的接触。
参照图19,另一管芯200设置在衬底112的背侧112上方。在一些实施例中,管芯200是从晶圆分割的半导体芯片。在设置在前侧112a上方之前,管芯200可以经历一系列的晶圆级半导体操作。例如,提供半导体晶圆,并在半导体衬底中形成有源和无源器件,诸如CMOS、二极管等。类似于互连件120的互连层220可以包括并设置在管芯200的有源表面上方。在互连件120的最上层级上,电介质240设置为钝化层以隔离湿气渗入互连层220,然而,一些导电焊盘224从介电层240暴露。管芯200然后可以从晶圆分割并重新定位在衬底112上方。导电柱245(图19中与导电柱224合并为一体)设置在暴露的导电焊盘224上并作为管芯200的电通信终端。导电柱245能够在分割操作之前或之后设置在暴露的导电焊盘224上。
管芯200与管芯100接合。管芯200的导电柱245接合到管芯100的导电柱145。管芯200和管芯100之间的接合可以涉及直接金属至金属接合、直接电介质至电介质接合和金属至电介质接合。直接金属至金属接合位于导电柱145和导电柱245之间的界面上。直接电介质至电介质接合位于介电层140和介电层240之间的界面上。金属至电介质接合位于导电柱145和介电层240之间的界面上或导电柱245和介电层140之间的界面上。一旦管芯100与管芯200接合,通过导电柱145及导电柱245的连接而形成电通信路径。在管芯100和管芯200之间通过电介质至电介质接合或金属至电介质接合也形成机械连接。
仍参照图19,部分地去除介电层140以暴露焊盘130a。在一些实施例中,去除部分比焊盘130a的宽度小,以便使焊盘130a仍被介电层140部分地覆盖。介电层140在焊盘130a处凹进并使表面150暴露。
参照图20,聚合物层146设置在介电层140上方。去除部分聚合物层146,并使穿孔与介电层140的凹槽重叠。在一些实施例中,焊盘130a的表面150从介电层140和聚合物层146部分地暴露。
在一些实施例中,管芯200不被聚合物层146覆盖,而是被聚合物层146部分地围绕。互连层220基本被聚合物层146围绕。光敏材料可以被选择为形成聚合物层146。例如,聚酰亚胺被选择为旋涂在介电层140上方。在步进器或扫描仪中使用中间掩模,以通过在预定波长光下的曝光操作限定将转印至光敏材料的图案。
参照图21,导电材料155配置为设置在暴露的表面150上方并且填充聚合物层146中的穿孔。类似于图11,导电材料155延伸穿过聚合物层146和介电层140中的穿孔。导电材料155也与焊盘130a的暴露表面150接触。通过管芯100和200的接合,管芯200进一步通过管芯100与导电材料155电通信。因此,导电材料155是集成接合结构的导电终端,集成接合结构包括管芯100和管芯200。
在一些实施例中,导电材料155过填充聚合物层146中的穿孔,并进一步覆盖聚合物层146的部分。导电材料155从焊盘130a的暴露表面150延伸,然后转向横向并且沿着聚合物层146的顶面146a粘附。导电材料155的横向延伸在转折点155c结束,然后向上改变,以形成与顶面146a相交的曲线。
曲线155a是导电材料155的外表面,并且配置为与集成接合半导体管芯结构外部的另一电子组件或电路接触。曲线155a与聚合物层146的顶面146a的交点处形成角度θ。θ值由导电材料155和聚合物层146之间的表面张力来确定。在图11中的实施例中,导电材料155被聚合物层146排斥并且角度θ小于约90度。在一些实施例中,角度θ小于约80度。在一些实施例中,角度θ是导电材料155和聚合物层146之间的润湿角。
导电材料155通过焊盘130a与管芯100和管芯200电通信。在一些实施例中,存在再分布层(RDL),其包括导电迹线或电连接焊盘130a与管芯100或管芯200的通孔。
参照图22,另一电子组件300在前侧112a上接合至管芯100。管芯100和组件300之间的结合可以涉及直接金属至金属接合、直接电介质至电介质接合和金属至电介质接合。一旦管芯100与组件300接合,电通信路径以及机械连接将形成。管芯100、200和组件300形成三层半导体结构。
参照图23,另一衬底500电连接至导电材料155。通过导电材料155,衬底500与管芯100、管芯200或组件300电通信。
在一些实施例中,半导体器件包括:第一管芯、接合至第一管芯从而形成接合界面的第二管芯、以及第一管芯的焊盘并且焊盘从第一管芯的聚合物层暴露。半导体器件还具有位于焊盘上并且在平行于第一管芯和第二管芯的堆叠方向的方向上从焊盘延伸的导电材料。在半导体器件中,半导体材料延伸至顶面,顶面垂直地高于第二管芯的背侧,其中,背侧是与接合界面相对的表面。
在一些实施例中,第二管芯的侧壁被聚合物层覆盖。在一些实施例中,第二管芯被聚合物层围绕。在一些实施例中,第二管芯至第一管芯的接合包括金属至金属接合。在一些实施例中,第二管芯至第一管芯的接合包括金属至电介质接合。在一些实施例中,第二管芯通过第一管芯的互连件与第一管芯电连接。在一些实施例中,导电材料为铜柱。在一些实施例中,部分导电材料是半球形。
在一些实施例中,第一管芯还包括具有前侧和背侧的第一衬底,并且第二管芯在第一衬底的背侧上接合至第一管芯;并且其中,半导体器件还包括在第一衬底的前侧上接合至第一管芯的电子组件。在一些实施例中,还包括连接至导电材料的第二衬底。在一些实施例中,电子组件与第二管芯重叠并且通过衬底通孔电连接至第二管芯。在一些实施例中,第一管芯还包括衬底并且衬底包括与第二管芯相对的背侧。
在一些实施例中,三维(3D)半导体器件包括第一管芯100和堆叠在第一管芯100上方并且与第一管芯的导电结构垂直地接合的第二管芯200。半导体器件还具有通过第一管芯和第二管芯的接合与第二管芯电通信的第一管芯的焊盘以及设置在焊盘上方的导电材料。在半导体器件中,半导体材料从焊盘突出并且到达高于第二管芯的垂直层级。
在一些实施例中,还包括覆盖第一管芯和第二管芯的焊盘的部分的聚合物层。在一些实施例中,第一管芯还包括衬底和位于衬底中的衬底通孔(TSV)。在一些实施例中,第二管芯与TSV接合。在一些实施例中,还包括部分地围绕第二管芯的模制。
在一些实施例中,半导体器件包括:第一管芯、接合到第一管芯的第二管芯以及位于第一管芯和第二管芯外部的电连接至第一管芯和第二管芯的衬底。在半导体器件中,第一管芯、第二管芯和衬底布置成垂直堆叠的方式,并且导电材料从第一管芯的焊盘突出并且垂直地延伸至比第二管芯更高的层级。半导体器件中,第一管芯、第二管芯和衬底通过导电材料相互通信。
在一些实施例中,导电材料与聚合物材料的表面接触,并且从表面弯曲。在一些实施例中,导电材料具有在聚合物材料的表面上的横向延伸件,并且横向延伸件在第一管芯的焊盘外面横向延伸。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (1)
1.一种半导体器件,包括:
第一管芯;
第二管芯,连接至所述第一管芯,从而形成接合界面;
所述第一管芯的焊盘,从所述第一管芯的聚合物层暴露;以及
导电材料,位于所述焊盘上并且在平行于所述第一管芯和所述第二管芯的堆叠方向的方向上从所述焊盘延伸,并且所述导电材料延伸至顶面,所述顶面垂直地高于所述第二管芯的背侧,其中,所述背侧是与所述接合界面相对的表面。
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