CN107424987A - Stack type semiconductor structure and its manufacture method - Google Patents

Stack type semiconductor structure and its manufacture method Download PDF

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Publication number
CN107424987A
CN107424987A CN201710524769.7A CN201710524769A CN107424987A CN 107424987 A CN107424987 A CN 107424987A CN 201710524769 A CN201710524769 A CN 201710524769A CN 107424987 A CN107424987 A CN 107424987A
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China
Prior art keywords
substrate
semiconductor structure
type semiconductor
contact
stack type
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CN201710524769.7A
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CN107424987B (en
Inventor
沈家贤
颜瀚琦
刘盈男
李维钧
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN107424987A publication Critical patent/CN107424987A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A kind of stack type semiconductor structure and its manufacture method.Stack type semiconductor structure pastes element including first substrate, second substrate, the first semiconductor chip, the second semiconductor chip and surface.First substrate has upper surface.Second substrate has lower surface.First semiconductor chip is located at the upper surface of first substrate.Second semiconductor chip is located at the lower surface of second substrate.First surface pastes element between the upper surface of first substrate and the lower surface of second substrate and is electrically connected with first substrate and second substrate.Because first surface pastes element between first substrate and second substrate, the size of semiconductor structure can be so reduced.

Description

Stack type semiconductor structure and its manufacture method
It is on March 28th, 2014, Application No. " 201410122664.5 ", entitled " heap the applying date that the application, which is, The divisional application of the application for a patent for invention of stacked semiconductor structure and its manufacture method ".
Technical field
The invention relates to a kind of stack type semiconductor structure and its manufacture method, and have in particular to one kind Paste the stack type semiconductor structure and its manufacture method of element in surface.
Background technology
With development in science and technology, industry is more and more more to the function of semiconductor structure and the demand of size, causes semiconductor junction The size of structure is more and more small, and function is more and more more.More and more more based on functional requirement, semiconductor structure generally comprises multiple Chip and multiple passive devices.
Passive device is located at outside substrate by conventional semiconductor structure, therefore causes the area of semiconductor structure to increase.Therefore, How to configure passive device and make great efforts one of target as industry to reduce semiconductor structure size.
Radio communication device/system generally includes to have the semiconductor structure of antenna to receive and transmission signal.With day The semiconductor structure of line can be installed on the circuit board or support plate of radio communication device/system, and through the connection of additional designs Structure is transmitted with reaching the signal between semiconductor structure and the circuit board or support plate of radio communication device/system.
The attachment structure of additional designs not only increases radio communication device/system holistic cost, while also increases channel radio The volume of T unit/system.
The content of the invention
The present invention is related to a kind of stack type semiconductor structure and its manufacture method, and in an embodiment, element is pasted on surface Between two substrates, semiconductor structure lateral dimension can be so reduced.
A kind of according to the present invention it is proposed that stack type semiconductor structure.Stack type semiconductor structure includes a first substrate, one Second substrate, one first semiconductor chip, one second semiconductor chip, a first surface paste element and a packaging body.First Substrate has a upper surface.Second substrate has a lower surface.First semiconductor chip is on the upper surface of first substrate.The Two semiconductor chips are on the lower surface of second substrate.First surface pastes the upper surface and second that element is located at first substrate Between the lower surface of substrate and it is electrically connected with first substrate and second substrate.The upper surface of packaging body coats first substrate, second The lower surface of substrate, the first semiconductor chip, the second semiconductor chip and first surface paste element.
A kind of according to the present invention it is proposed that stack type semiconductor structure.Stack type semiconductor structure includes the first substrate, second Substrate, at least one surface mounted component, antenna, at least one first conductive hole and at least one second conductive hole.First lining Bottom has upper surface.Second substrate has upper and lower surface, and the lower surface is relative to the upper surface, second lining The lower surface at bottom faces the upper surface of first substrate.At least one surface mounted component is located at first substrate Between upper surface and the lower surface of second substrate and there is the first contact and the second contact, first contact and described the Two point then electrically connects in the upper surface of first substrate, the second contact of at least one surface mounted component respectively It is connected to the ground plane of first substrate.Antenna is arranged on the upper surface of second substrate.At least one first conductive hole Located at second substrate and it is electrically connected with the first contact of the antenna and at least one surface then element.At least One the second conductive hole is located at second substrate and is electrically connected with the antenna and at least one surface then element The second contact.
A kind of according to the present invention it is proposed that manufacture method of stack type semiconductor structure.Manufacture method comprises the following steps.Carry For a first substrate；One first semiconductor chip is set in a upper surface of first substrate；A second substrate is provided, wherein second The lower surface of substrate is provided with one second semiconductor chip；The upper surface and one of element connection first substrate is pasted with a first surface To be electrically connected with first substrate and second substrate between a lower surface of second substrate；And form a packaging body coats first The portion of upper surface of substrate, the portion lower surface of second substrate, the first semiconductor chip, the second semiconductor chip and first surface Paste element.
A kind of according to the present invention it is proposed that manufacture method of stack type semiconductor structure.Manufacture method comprises the steps of.Carry For at least one first substrate, every one first substrate has upper surface；At least one second substrate, every one second substrate tool are provided There is upper and lower surface, the lower surface has antenna relative to the upper surface, the upper surface of every one second substrate, and often One second substrate has the first conductive hole and the second conductive hole, and first conductive hole is located at second substrate and electrically connects The antenna is connect, and second conductive hole located at second substrate and is electrically connected with the antenna；In every one second substrate Lower surface and every one first substrate upper surface between at least one surface peace with the first contact and the second contact is provided Fill element, by the first contact of at least one surface mounted component be electrically connected to first substrate first surface and First conductive hole, and the second contact of at least one surface mounted component is electrically connected to first substrate Ground plane and second conductive hole.
A kind of according to the present invention it is proposed that electronic installation.Electronic installation includes support plate and stack type semiconductor structure, the load Plate has corner, and the stack type semiconductor structure is located on the corner of the support plate and comprising the first substrate, the second lining Bottom, at least one surface mounted component, antenna, at least one first conductive hole and at least one second conductive hole.First substrate With upper surface.Second substrate has upper and lower surface, and the lower surface is relative to the upper surface, second substrate Lower surface face first substrate upper surface.At least one surface mounted component is located at the upper of first substrate Between surface and the lower surface of second substrate and there is the first contact and the second contact, first contact and described second Contact is then electrically connected with the upper surface of first substrate, the second contact of at least one surface mounted component respectively To the ground plane of first substrate.Antenna is arranged on the upper surface of second substrate.At least one first conductive hole is set In second substrate and it is electrically connected with the first contact of the antenna and at least one surface then element.At least one Individual second conductive hole is located at second substrate and is electrically connected with the antenna and at least one surface then element Second contact.
For the above of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing, elaborate It is as follows：
Brief description of the drawings
Figure 1A illustrates the sectional view of the stack type semiconductor structure according to one embodiment of the invention.
Figure 1B illustrates Figure 1A top view.
Fig. 2 illustrates the top view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 3 illustrates the top view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 4 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 5 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 6 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 7 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 8 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Fig. 9 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Figure 10 A to 10G illustrate the process drawing of Figure 1A stack type semiconductor structure.
Figure 11 A to 11E illustrate the process drawing of Fig. 4 stack type semiconductor structure.
Figure 12 A to 12C illustrate the process drawing of Fig. 7 stack type semiconductor structure.
Figure 13 A illustrate the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Figure 13 B illustrate the circuit diagram of Figure 13 A stack type semiconductor structure.
Figure 14 A illustrate the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Figure 14 B illustrate the circuit diagram of Figure 14 A stack type semiconductor structure.
Figure 15 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Figure 16 illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.
Figure 17 to 21 illustrates the flow chart making of Figure 13 A stack type semiconductor structure.
Figure 22 to 26 illustrates the flow chart making of Figure 15 stack type semiconductor structure.
Figure 27 A illustrate the schematic diagram of the antenna of Figure 13 A stack type semiconductor structure.
Figure 27 B illustrate the reflection loss schematic diagram of Figure 27 A antenna.
Figure 28 A illustrate the schematic diagram of the antenna of Figure 13 A stack type semiconductor structure.
Figure 28 B illustrate the reflection loss schematic diagram of Figure 28 A antenna.
The stack type semiconductor structure that Figure 29 A illustrate Figure 13 A applies schematic diagram in system support plate.
Figure 29 B illustrate the CURRENT DISTRIBUTION schematic diagram of the antenna of the stack type semiconductor structure depicted in Figure 29 A.
Figure 29 C illustrate the CURRENT DISTRIBUTION schematic diagram of system support plate shown in Figure 29 A and the antenna of stack type semiconductor structure.
Figure 30 illustrates the schematic block circuit diagram of Figure 13 A stack type semiconductor structure.
Main element symbol description：
100、200、300、400、500、600、700：Stack type semiconductor structure
110、510、610：First substrate
111：The first base material
111b、131b、132b：Lower surface
111s、131s、151s、152s、515s、535s：Lateral surface
111u、112u、131u：Upper surface
112：First line layer
113：Second line layer
114、114'、114”：First conductive hole
120：First semiconductor chip
125：Bonding wire
126：Antenna
130、530、630：Second substrate
131：Second base material
132：Tertiary circuit layer
133：4th line layer
134：Second conductive hole
140：Second semiconductor chip
150：Packaging body
151：First packaging body
152：Second packaging body
160、161、161'、162、163、164、165'、165”、165”'：First surface pastes element
160a、161a、162a、163a、164a、165a、170a：First contact
160b、161b、162b、163b、164b、165b、170b：Second contact
170：Second surface pastes element
175：Solder
190：Support plate
515：First earthing member
535：Second earthing member
580：Screened film
616：First screen layer
636：Secondary shielding layer
H1：Highly
H2：Distance
P1：Cutting Road
S：Space
1：Electronic installation
800、810、900、910：Stack type semiconductor structure
18、181、182：Conductive connecting material
Embodiment
Fig. 1 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to one embodiment of the invention.Stack half Conductor structure 100 includes first substrate 110, at least one first semiconductor chip 120, second substrate 130, at least 1 the second half led Body chip 140, packaging body 150, an at least first surface paste element (Surface Mount Device, SMD) 160 and at least One second surface pastes element 170.
First substrate 110 is led including the first base material 111, first line layer 112, the second line layer 113 and at least 1 first Electric hole 114.The upper surface 111u of the first base material 111 and the upper surface 112u common definitions first substrate 110 of first line layer 112 Upper surface.The line layer 113 of first line layer 112 and second is respectively formed in the upper surface 111u and following table of the first base material 111 Face 111b, it is for electrically connecting to the element being provided thereon.First conductive hole 114 extends the upper surface 111u of the first base material 111 Between the 111b of lower surface and it is electrically connected with the line layer 113 of first line layer 112 and second.
With its active surface, orientation is located on the upper surface of first substrate 110 first semiconductor chip 120 upward, and by extremely A few bonding wire 125 is electrically connected at first line layer 112.First semiconductor chip 120 can pass through first line layer 112, first Element 160 is pasted on surface and second surface pastes element 170 and is electrically connected with second substrate 130, and/or person, and can pass through first Line layer 112, the first conductive hole 114 and the second line layer 113 are electrically connected at an external ground end (not illustrating), an outside and handed over Flow power supply (not illustrating) or an external dc power (not illustrating).In another example, the first semiconductor chip 120 also can be flip (flip chip), it is located at active faced downwards position on the upper surface of first substrate 110, and electrical by an at least soldered ball It is connected to first line layer 112.
Second substrate 130 is led including the second base material 131, tertiary circuit layer 132, the 4th line layer 133 and at least 1 second Electric hole 134.The lower surface 131b of second base material 131 and the lower surface 132b common definitions second substrate 130 of tertiary circuit layer 132 Lower surface.The line layer 133 of tertiary circuit layer 132 and the 4th is respectively formed in the lower surface 131b and upper table of the second base material 131 Face 131u, it is for electrically connecting to the element being provided thereon.Second conductive hole 134 extends the upper surface 131u of the second base material 131 Between the 131b of lower surface and it is electrically connected with the line layer 133 of tertiary circuit layer 132 and the 4th.
Second semiconductor chip 140 be, for example, flip, its with active surface upward orientation be located at second substrate 130 lower surface On, and tertiary circuit layer 132 is electrically connected at by an at least soldered ball.Second semiconductor chip 140 can pass through tertiary circuit layer 132nd, second surface pastes element 170 and first surface pastes element 160 and is electrically connected with first substrate 130.In another example, second Semiconductor chip 140 can also its active faced downwards position on the lower surface of second substrate 130, and pass through an at least bonding wire It is electrically connected at tertiary circuit layer 132.
In this example, packaging body 150 coats portion of upper surface, the part following table of second substrate 130 of first substrate 110 simultaneously Face, the first semiconductor chip 120, the second semiconductor chip 140, first surface pastes element 160 and second surface pastes element 170.Packaging body 150 may include phenolic group resin (Novolac-based resin), epoxy (epoxy-based Resin), silicone (silicone-based resin) or other appropriate coverings.Packaging body 150 also may include suitably Filler, e.g. powdery silica.Packaging body, e.g. compression forming are formed using several encapsulation technologies (compression molding), injection moulding (injection molding), liquid encapsulation type (liquid Encapsulation) or metaideophone is molded (transfer molding).
It is, for example, passive device that first surface, which pastes element 160, such as resistor, capacitor or inductor.First surface sticks Element 160 is pasted on the upper surface of first substrate 110, and under the upper surface of first substrate 110 and second substrate 130 Between surface and it is electrically connected with first substrate 110 and second substrate 130.First surface, which pastes element 160, can pass through first line The conductive hole 114 of layer 112 and first is electrically connected at the second line layer 113, and is electrically connected at outside by the second line layer 113 Earth terminal, external ac power source or external dc power.In one, it can be 40 that first surface, which pastes the length of element 160 × wide, The English silk of English silk × 20, its thickness are 0.5 millimeter；Or it can be 60 English silk × 30 that first surface, which pastes the length of element 160 × wide, English silk, its thickness are 0.8 millimeter, or are other appropriate sizes.
It is, for example, passive device that second surface, which pastes element 170, such as resistor, capacitor or inductor.In this example, second Element 170 is pasted on the lower surface of second substrate 130 and element is pasted with first surface by an at least solder 175 in surface 160 docking.Straightly stacked because first surface pastes element 160 and pastes element 170 with second surface, therefore stack can be reduced The lateral dimension of semiconductor structure 100.In addition, the dimensions that second surface pastes element 170 is pasted similar in appearance to first surface Element 160, hold this and repeat no more.
Second surface, which pastes element 170, to be electrically connected at the 4th line layer 133 by the second conductive hole 134, and passes through 4th line layer 133 is electrically connected at external ground end, external ac power source or external dc power.In addition, first surface sticks Patch element 160 pastes the height H1 after element 170 docks with second surface and is more than the first semiconductor chip 120 and the second semiconductor The gross thickness of chip 140, make to form space S between the first semiconductor chip 120 and the second semiconductor chip 140, this space S can Bonding wire 125 is accommodated, bonding wire 125 is not interfered with the second semiconductor chip 140 easily.In addition, above-mentioned packaging body 150 fills up this Space S, and more fix bonding wire 125, the first semiconductor chip 120 and the second semiconductor chip 140.
First surface paste element 160 paste element 170 with second surface can be in parallel.Specifically, first surface is pasted Element 160 includes the first contact 160a and the second contact 160b, and second surface paste element 170 include the first contact 170a and Second contact 170b, wherein first surface paste the first contact 160a and the second contact 160b of element 160 respectively with the second table Face paste element 170 the first contact 170a and the second contact 170b docking and it is in parallel.Right not limited to this of the embodiment of the present invention, the One surface pastes element 160 and pastes element 170 with second surface and can also connect, for example, first surface pastes the first of element 160 Contact 160a pastes the second contact 170b docking of element 170 with second surface and connected；Or first surface pastes element 160 Second contact 160b pastes the first contact 170a docking of element 170 with second surface and connected.
Figure 1B is refer to, it illustrates Figure 1A top view, and (to clearly show that, Figure 1B does not illustrate first substrate 130, the second half Conductor chip 140 and second surface paste element 170).The series/parallel of element is pasted via surface, a default electricity can be obtained Line structure.Illustrating so that first surface pastes element 161 as an example, it is, for example, inductor that one of first surface, which pastes element 161, It includes the first contact 161a and the second contact 161b, wherein the first contact 161a is grounded by the first conductive hole 114', and the Two point 161b is electrically connected at the external world by the first conductive hole 114 ", and is electrically connected by first line layer 112 and bonding wire 125 The first semiconductor chip 120 is connected to, in this way, the electrostatic for coming from the external world can be by the first conductive hole 114 " and the second contact 161b Dredge to the earth terminal being electrically connected with the first conductive hole 114', avoid the first semiconductor chip of electrostatic breakdown 120.
In another example, it is capacitor that first surface, which pastes element 161, wherein the first contact 161a passes through the first conductive hole 114' is grounded, and the second contact 161b is electrically connected at an external power source and by first line layer by the first conductive hole 114 " 112 and bonding wire 125 be electrically connected at the first semiconductor chip 120, by this design, can be the DC influence of external power source (Noise) or low-frequency disturbance is pasted element 161 by first surface and dredged to the ground connection being electrically connected with the first conductive hole 114' End.
In another example, it is, for example, capacitor that first surface, which pastes element 161', and it is series at the first semiconductor chip 120, It can be formed and flow obstructing instrument (DC blocking) always, stop that DC signal enters the first semiconductor chip 120.
In other examples, another two first surface is pasted element 162 and is one another in series, and passes through first line layer 112 and bonding wire 125 are electrically connected with the first semiconductor chip 120.Specifically, two first surfaces, which paste element 162, respectively includes the first contact 162a And the second contact 162b, wherein a first surface pastes the first contact 162a of element 162 and another first surface pastes element 162 the second contact 162b is electrically connected with and connected directly or by first line layer 112.In this example, two first surfaces are pasted Element 162 is resistor, and the first semiconductor chip 120 can be electrically connected at 2 first by bonding wire 125 and first line layer 112 Between element 162 is pasted on surface, and form a bleeder circuit (Bias circuit).
In another example, another two first surface is pasted element 163 and can be connected in parallel to each other.Specifically, two first surfaces paste member Part 163 respectively includes the first contact 163a and the second contact 163b, wherein a first surface pastes the first contact 163a of element 163 And second contact 163b pasted respectively with another first surface element 163 the first contact 163a and the second contact 163b directly or It is electrically connected with by first line layer 112 and parallel connection.
Fig. 2 is refer to, it illustrates the top view of the stack type semiconductor structure according to another embodiment of the present invention.This example In, it is, for example, inductor that first surface, which pastes element 164, and it includes first end point 164a and the second end points 164b, wherein first End points 164a is electrically connected at a direct current (DC) power supply by the first conductive hole 114, and the second end points 164b is electrically connected at The antenna 126 of semiconductor chip 120 and one or high-frequency circuit, by this design, make the height for coming from antenna 126 or high-frequency circuit Frequency signal will not paste element 164 via first surface and dredge to the dc source being electrically connected with the first conductive hole 114.Tying On structure, antenna 126 (or high-frequency circuit) can be at least a portion of the 4th line layer 133 or be additionally formed in the second base material 131 upper surface 131u antenna stack.
Fig. 3 is refer to, it illustrates the top view of the stack type semiconductor structure according to another embodiment of the present invention.This example In, three first surfaces paste element 165', 165 " and 165 " ' and are connected into a π shape impedance matchings, and wherein first surface pastes element 165 " be coupled to first surface paste element 165' and first surface paste element 165 " ' between.First surface pastes element 165' the first contact 165a is electrically connected at earth terminal by the first conductive hole 114, and first surface pastes the of element 165 Two point 165b is electrically connected at antenna 126 and pastes element 165 " with first surface.
It is above-mentioned that the circuit feature that element 160 formed is pasted by first surface is only the wherein several embodiments of the present invention.According to According to spirit of the embodiment of the present invention, the series/parallel of element 160 can be pasted by several first surfaces to design wave filter (filter), balun (balun), power divider (power divider), diplexer (diplexer), attenuator (attenuator) or other various circuits.In addition, second surface pastes the connection side of element 170 Formula pastes the connected mode of element 160 similar in appearance to first surface, holds this and repeats no more.In addition, first surface paste element 160 with Second surface, which pastes element 170, can also use similar manner serial or parallel connection.
Fig. 4 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 200 includes first substrate 110, at least one first semiconductor chip 120, second substrate 130, at least 1 the second half Conductor chip 140, the first packaging body 151, the second packaging body 152, an at least first surface paste element 160 and at least one second Paste element 170 in surface.
The packaging body that first packaging body 151 and the second packaging body 152 are each individually formed, wherein the first packaging body 151 wraps Cover the first semiconductor chip 120 and first surface pastes element 160, and the second packaging body 152 coats the second semiconductor chip 140 And second surface pastes element 170.The material of first packaging body 151 and the second packaging body 152 can be similar in appearance to above-mentioned packaging body 150, hold this and repeat no more.In addition, the material of the first packaging body 151 and the second packaging body 152 can be identical or different.
Although between the first substrate 110 and second substrate 130 of above-described embodiment using stack two-layer surface paste element as Example explanation, element is pasted on the surface that more than two layers also so can be stacked between first substrate 110 and second substrate 130；Or also Stackable monolayer surface pastes element, is illustrated below with 5 figures.
Fig. 5 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 300 includes first substrate 110, at least one first semiconductor chip 120, second substrate 130, at least 1 the second half Conductor chip 140, packaging body 150 and at least a first surface pastes element 160.
In this example, the surface between first substrate 110 and second substrate 130 pastes the single first surface of element and pastes member Part 160, or can say it is the element for being located at same stack layer.The first contact 160a and second that first surface pastes element 160 connects Point 160b is connected to the upper surface of first substrate 110 and the lower surface of second substrate 130, and is electrically connected with first substrate 110 with second substrate 130.In this example, first surface, which pastes element 160, can be purely by way of first substrate 110 and second substrate 130 Between telecommunication transmission medium, without provide circuit function, circuit function so can be also provided, such as passive device function.
The distance H2 that first surface pastes the first contact 160a and the second contact 160b of element 160 is more than the first semiconductor The gross thickness of the semiconductor chip 140 of chip 120 and second, makes between the first semiconductor chip 120 and the second semiconductor chip 140 Form space S.Packaging body 150 can fill up this space and coat bonding wire 125, and more fix bonding wire 125, the first semiconductor core The semiconductor chip 140 of piece 120 and second.
Fig. 6 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 400 includes stack type semiconductor structure 100 and stack type semiconductor structure 300, and it overlies one another together.Heap Second line layer 113 of stacked semiconductor structure 100 is stacked in and is electrically connected at the 4th line of stack type semiconductor structure 300 Road floor 133, the semiconductor chip 120 and 140 of stack type semiconductor structure 100 is set to pass through first line layer 112, the second line layer 113rd, the 4th line layer 133 of stack type semiconductor structure 300 and tertiary circuit layer 132 are electrically connected at stack type semiconductor knot The semiconductor chip 120 and 140 of structure 300.
Although Fig. 6 stack type semiconductor structure is illustrated exemplified by stacking two semiconductor structures, so also stackable two Semiconductor structure above.
Fig. 7 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 500 includes first substrate 510, at least one first semiconductor chip 120, second substrate 530, at least 1 the second half Conductor chip 140, the first packaging body 151, the second packaging body 152, an at least first surface paste element 160, at least one second Paste element 170 and screened film 580 in surface.
First substrate 510 includes the first base material 111, first line layer 112, the second line layer 113, at least one first conduction Hole 114 and at least one first earthing member 515.The upper surface 111u of the first base material 111 and upper surface 112u of first line layer 112 The upper surface of common definition first substrate 510.The line layer 113 of first line layer 112 and second is respectively formed in the first base material 111 Upper surface 111u and lower surface 111b, to be electrically connected with the element that is provided thereon.First conductive hole 114 extends the first base material Between 111 upper surface 111u and lower surface 111b, and it is electrically connected with the line layer 113 of first line layer 112 and second.First connects Ground part 515 is extended between the upper surface 111u of the first base material 111 and lower surface 111b, and from the lateral surface of the first base material 111 111s exposes, to be electrically connected at screened film 580.First earthing member 515 is, for example, earthing rod, and it is electrically connected at an earth terminal (not illustrating), earth terminal can be electrically connected at by the first earthing member 515 by first surface is pasted element 160.So, first surface Paste element 160 also can be electrically connected at earth terminal by the earthing member 515 of screened film 580 and first.
First semiconductor chip 120 is, for example, flip, and it is located at the upper surface of first substrate 510 with active faced downwards position On, and first line layer 112 is electrically connected at by an at least soldered ball.First semiconductor chip 120 can pass through first line layer 112 and first surface paste element 160 be electrically connected with second substrate 530.In another example, the first semiconductor chip 120 can also Orientation is located on the upper surface of first substrate 510 active surface upward, and is electrically connected at first line layer by an at least bonding wire 112。
Second substrate 530 includes the second base material 131, tertiary circuit layer 132, the 4th line layer 133, at least one second conduction Hole 134 and at least one second earthing member 535.The lower surface 131b of the second base material 131 and lower surface 132b of tertiary circuit layer 132 The upper surface of common definition second substrate 530.The line layer 133 of tertiary circuit layer 132 and the 4th is respectively formed in the second base material 131 Upper surface 131u and lower surface 131b, to be electrically connected with the element that is provided thereon.Second conductive hole 134 extends the second base material Between 131 upper surface 131u and lower surface 131b and it is electrically connected with the line layer 133 of tertiary circuit layer 132 and the 4th.Second connects Ground part 535 is extended between the upper surface 131u and lower surface 131b of the second base material 131, and from the lateral surface of the second base material 131 131s exposes, to be electrically connected at screened film 580.Second earthing member 535 can paste member by second substrate 530, first surface First conductive hole 114 of part 160 and first substrate 510 is electrically connected at earth terminal；Or screened film 580 and first can be passed through First earthing member 515 of substrate 510 is electrically connected at earth terminal.
With active surface, orientation is located on the upper surface of second substrate 530 second semiconductor chip 140 upward, and by least One bonding wire is electrically connected at tertiary circuit layer 132.Second semiconductor chip 140 can be sticked by tertiary circuit layer 132, second surface Patch element 170 and first surface paste element 160 and are electrically connected with first substrate 530.In another example, the second semiconductor chip 140 E.g. flip, it can be with its active faced downwards position on the upper surface of second substrate 530, and passes through at least soldered ball electricity Property is connected to tertiary circuit layer 132.
Screened film 580 is formed at the lateral surface 111s of the first base material 111, the lateral surface 131s of the second base material 131, first connect The lateral surface 515s of ground part 515, the lateral surface 535s of the second earthing member 535, the lateral surface 151s and second of the first packaging body 151 The lateral surface 152s of packaging body 152, and earth terminal is electrically connected at by the first earthing member 515 and/or the second earthing member 535.
The materials of aluminum of screened film 580, copper, chromium, tin, gold, silver, nickel, stainless steel or above-mentioned material combination made by, it can Using e.g. chemical vapor deposition (Chemical Vapor Deposition, CVD), electroless plating (electroless Plating), electroplate, print (printing), spraying (spraying), sputter or vacuum moulding machine (vacuum deposition) It is made etc. technology.Screened film 580 can be single or multiple lift material.For example, the three-decker of screened film 580, its internal layer stainless steel Layer, intermediate layer layers of copper, and outer layer stainless steel layer；Or the double-decker of screened film 580, its internal layer layers of copper, and its outer layer stainless steel Layer.
Fig. 8 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 600 includes first substrate 610, at least one first semiconductor chip 120, second substrate 630, at least 1 the second half Conductor chip 140, the first packaging body 151, the second packaging body 152, an at least first surface paste element 160, at least one second Paste element 170 and screened film 580 in surface.
First substrate 610 includes the first base material 111, first line layer 112, the second line layer 113, at least one first conduction Hole 114, at least one first earthing member 515 and first screen layer 616.First screen layer 616 is electrically connected at the first earthing member 515.First screen layer 616 is formed at the inside of the first base material 111 and extended transversely with, to be produced to the first semiconductor chip 120 Electromagnetic interference shielding acts on.In addition, first screen layer 616 continuously extends in the inside of the first base material 111, and opened with least one Hole 616a, to isolate the first conductive hole 114, avoid the first conductive hole 114 and the electrical short of first screen layer 616.
Second substrate 630 includes the second base material 131, tertiary circuit layer 132, the 4th line layer 133, at least one second conduction Hole 134, at least one second earthing member 535 and secondary shielding layer 636.Secondary shielding layer 636 is electrically connected at the second earthing member 535.Secondary shielding layer 636 is formed at the inside of the second base material 131 and extended transversely with, with to the first semiconductor chip 120 and the Two semiconductor chips 140 produce electromagnetic interference shielding effect.Further say, the first semiconductor chip 120 is by the first shielding Layer 616, secondary shielding layer 636 and screened film 580 surround, and electromagnetic interference, which can be reduced or avoided, negatively influences the first semiconductor Chip 120.Similarly, the second semiconductor chip 140 is surrounded by secondary shielding layer 636 and screened film 580, can reduce or keep away Exempting from electromagnetic interference negatively influences the second semiconductor chip 140.
Fig. 9 is refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 700 includes first substrate 510, at least one first semiconductor chip 120, second substrate 530, at least 1 the second half Conductor chip 140, the first packaging body 151, the second packaging body 152, an at least first surface paste element 160, at least one second Paste element 170 and screened film 580 in surface.In this example, first surface pastes being similarly configured in above-mentioned Fig. 5 heap of element 160 The first surface of stacked semiconductor structure 300 pastes element 160, holds this and repeats no more.
Figure 10 A to 10G are refer to, it illustrates the process drawing of Figure 1A stack type semiconductor structure.
As shown in Figure 10 A, there is provided first substrate 110.First substrate 110 include the first base material 111, first line layer 112, Second line layer 113 and at least one first conductive hole 114.The upper surface 111u of the first base material 111 is upper with first line layer 112 The upper surface of surface 112u common definitions first substrate 110.The line layer 113 of first line layer 112 and second is respectively formed in The upper surface 111u and lower surface 111b of one base material 111, the first conductive hole 114 is through the first base material 111 and electric connection first The line layer 113 of line layer 112 and second.
As shown in Figure 10 B, to be, for example, that technology (Surface Mounted Technology, SMT) is pasted on surface, set At least one first semiconductor chip 120 is electrically connected with first on the upper surface of first substrate 110, and with an at least bonding wire 125 Semiconductor chip 120 and first line layer 112.
As illustrated in figure 10 c, to be, for example, that technology is pasted on surface, an at least first surface is set to paste element 160 in first On the upper surface of substrate 110.First surface pastes element 160 and is electrically connected at the second line layer 113 by first line layer 112 And first semiconductor chip 120.
As shown in Figure 10 D, the first contact 160a and that an at least solder 175 pastes element 160 in first surface is formed On two point 160b.
As shown in figure 10e, similar in appearance to Figure 10 A to Figure 10 D technique, to form second substrate 130, the second semiconductor chip 140 and second surface paste the combining structure of element 170.Then, technology or other proper engagement skills are e.g. pasted with surface Art, docking second surface paste element 170 and paste element 160 with first surface.Then, reflow (reflow) technique is performed, is led to Cross the soldering second surface of solder 175 and paste element 170 and first surface and paste element 160.
As shown in figure 10f, to be, for example, compression forming, injection moulding, liquid encapsulation type or metaideophone forming technique, envelope is formed Fill body 150 coat the portion of upper surface of first substrate 110, the portion lower surface of second substrate 130, the first semiconductor chip 120, First surface pastes element 160, bonding wire 125, the second semiconductor chip 140 and second surface and pastes element 170.
As shown in figure 10g, the structure of unification 10F figures.For example, with cutter or laser, an at least Cutting Road P1 is formed By second substrate 130, packaging body 150 and first substrate 110, to form at least one stack type semiconductor knot as shown in Figure 1A Structure 100.
Figure 11 A to 11E are refer to, it illustrates the process drawing of Fig. 4 stack type semiconductor structure.
As shown in Figure 11 A, to be, for example, compression forming, injection moulding or metaideophone forming technique, the first packaging body 151 is formed Coat the first semiconductor chip 120, first surface pastes element 160 and bonding wire 125.
As shown in Figure 11 B, with such as grinding method, the portion of material of packaging body 150 is removed, is sticked until exposing first surface Paste the first contact 160a and the second contact 160b of element 160.
As shown in Figure 11 C, an at least solder 175 is formed to paste in element 160 exposed to packaging body 150 in first surface On first contact 160a and the second contact 160b.
As shown in Figure 11 D, similar in appearance to Figure 11 A to Figure 10 C technique, to form second substrate 130, the second semiconductor chip 140th, the second packaging body 152 and second surface paste the combining structure of element 170.Then, e.g. surface paste technology or its Its proper engagement technology, docking second surface paste element 170 and paste element 160 with first surface.Then, reflow work is performed Skill, element 170 is pasted by the soldering second surface of solder 175 and pastes element 160 with first surface.
As depicted in fig. 11E, unification Figure 11 D structure.For example, with cutter or laser, at least Cutting Road P1 warps are formed Second substrate 130, the first packaging body 151, the second packaging body 152 and first substrate 110 are crossed, it is as shown in Figure 4 to form at least one Stack type semiconductor structure 200.
System of the manufacturing process of Fig. 5 stack type semiconductor structure 300 similar in appearance to Figure 1A stack type semiconductor structure 100 Process is made, holds this and repeats no more.In the manufacturing process of Fig. 6 stack type semiconductor structure 400, by stack type semiconductor structure 100 are stacked in stack type semiconductor structure 300.
Figure 12 A to 12C are refer to, it illustrates the process drawing of Fig. 7 stack type semiconductor structure.
As illustrated in fig. 12, there is provided first substrate 510, the first semiconductor chip 120, the first packaging body 151 and first surface Paste the combining structure of element 160, the manufacturing process of the forming process of this combining structure similar in appearance to above-mentioned Figure 11 A to Figure 11 B.And And, there is provided second substrate 530, the second semiconductor chip 140, the second packaging body 152 and second surface paste the combination of element 170 Structure, the manufacturing process of the forming process of this combining structure similar in appearance to above-mentioned Figure 11 A to Figure 11 B.
In Figure 12 A, to be, for example, that technology is pasted on surface, the 4th line layer 133 of second substrate 530 is stacked in the first table Face is pasted on element 160, makes the second semiconductor chip 140 can be by tertiary circuit layer 132, the 4th line layer 133 and the first table Paste element 160 and be electrically connected at the first semiconductor chip 120 in face.
As shown in Figure 12 B, Figure 12 A structure is set on a support plate 190.Then, to be, for example, cutter or laser, formed An at least Cutting Road P1 carries by the second packaging body 152, second substrate 530, the first packaging body 151, first substrate 510 and part Plate 190, to cut off the structure of whole 12A figures, cutting mode so is referred to as worn entirely to be cut (full cut).
As indicated in fig. 12 c, to be, for example, the skills such as chemical vapor deposition, electroless plating, plating, printing, spraying, sputter or vacuum moulding machine Art, form screened film 580 and cover the lateral surface 111s of the first base material 111, the lateral surface 131s of the second base material 131, the first ground connection The lateral surface 515s of part 515, the lateral surface 535s of the second earthing member 535, the lateral surface 151s of the first packaging body 151 and the second envelope The lateral surface 152s of body 152 is filled, to form at least one stack type semiconductor structure 500 as shown in Figure 7.Screened film 580 passes through First earthing member 515 and/or the second earthing member 535 are electrically connected at an earth terminal (not illustrating).
The manufacturing process of Fig. 8 stack type semiconductor structure 600 and Fig. 9 stack type semiconductor structure 700 and similar in appearance to The manufacturing process of Fig. 7 stack type semiconductor structure 500, holds this and repeats no more.
Figure 13 A are refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Formula semiconductor structure 800 can be including but not limited to the first substrate 110, at least one surface mounted component 160, packaging body 150, screen Cover film 580, the substrate 130 of conductive connecting material 18 and second.
As shown in FIG. 13A, the first substrate 110 has upper surface 111u, lower surface 111b and side 111S.Lower surface 111b Relative to upper surface 111u.Side 111S connections upper surface 111u and lower surface 111b.In an embodiment of the present invention, the first lining Bottom 110 can be or can include but is not limited to such as RF magnetron sputtering, glass, silicon, silica or other silicides.First lining Can have connection weld pad (connection pad, not shown) or trace (trace, not shown) on the upper surface 111u at bottom 110, It can be electrically connected to the ground plane of the first substrate 110 via interlayer circuit (inter-layer circuit, not shown) (ground, not shown).First substrate 110 can have the thickness from 10 μm to 3000 μm, for example, in embodiments of the invention In, the thickness can be the distance between first surface 101 and second surface 102.
At least one surface mounted component 160 is located at the upper surface 111u of first substrate 110, and has the first contact 160a and the second contact 160b.First contact 160a and the second contact 160b is respectively then in the upper surface of the first substrate 110 111u, wherein, the second contact 160b of at least one surface mounted component 160 may be connected to the connection weld pad or trace To be electrically connected with the ground plane of the first substrate 110.In an embodiment of the present invention, at least one surface mounted component 160 The two-terminal that coding (imperial code) for example made in Great Britain is 0603 can be but not limited to and encapsulate (two-terminal Package) element, or the two-terminal potted element that metric system coding (metric code) is 1608.A for example, at least surface peace Dress element 160 can be with the height for being essentially the length of 1.6 millimeters (mm), 0.8mm width and 0.8mm.It is at least one Surface mounted component 160 can be but not limited to passive element (passive component, such as capacitor or inductor), Discrete elements (such as transistor or diode) or other two-terminal potted elements.In an embodiment of the present invention, it is at least one The height of surface mounted component 160 is the height relatively larger than other elements on the 111u of upper surface.At least one surface installation member Part 160 connects the substrate 130 of the first substrate 110 and second, and other elements on the 111u of upper surface are accommodated to form accommodation space (as described later).(do not illustrate) in another embodiment, the height of at least one surface mounted component 160 can be relatively shorter than The height of other elements on the 111u of upper surface, its heap poststack can be made by stacking at least two surface mounted component 160 Highly it is relatively larger than other elements on the 111u of upper surface.At least two surface mounted component 160 is electric connection, and its In one be electrically connected with first substrate 110, another is electrically connected with described second substrate 130, to form accommodation space appearance Receive other elements on the 111u of upper surface.
Stack type semiconductor structure 800 separately may include but be not limited to RF front-end module (Front End Module, FEM) 110a, transceiver chip set (Transceiver Chipset) 110b, memory (Memory) 110c, surface mounted component 110d, voltage-stablizer (regulator) 110e and microcontroller (microcontroller, MCU)/application specific integrated circuit (Application-specific integrated circuit,ASIC)110f.It can be used according to the encapsulation kenel of element The technologies such as routing, welding or flip-chip are by RF front-end module 110a, transceiver chip set 110b, memory 110c, surface Installation elements 110d, voltage-stablizer 110e and microcontroller/application specific integrated circuit 110f are connected to positioned at the upper of the first substrate 110 Surface 111u circuit.
Packaging body (encapsulation material) 150 is located at the upper surface 111u of first substrate 110, and has There are upper surface 1501 and side 1502, and the side 1502 of the packaging body 150 and the side of first substrate 110 111S is flushed, therefore stack type semiconductor structure 800 has comparatively smooth outward appearance and less size.Packaging body 150 Coat the upper surface 111u of first substrate 110 and at least one surface mounted component 160, and expose it is described at least The the first contact 160a and the second contact 160b of one surface mounted component 160.Packaging body 150 can be or can include but not It is limited to such as novolac resin (novolac resin), epoxy resin (Epoxy resin), silica resin (silicone ) or other suitable materials resin.
Screened film 580 is anti electromagnetic wave shade (EMI shielding), and it can be but not limited to conformal shade (conformal shielding).Screened film 580 includes first screen layer 5801 and secondary shielding layer 5802, and the first shielding Layer 5801 connects secondary shielding layer 5802.First screen layer 5801 covers the side 111S and packaging body of first substrate 110 150 side 1502.First screen layer 5801 has a lower surface, and the lower surface and first substrate 110 Lower surface 111b is substantially flushed, and can completely coat the first substrate 110 effectively to completely cut off Electromagnetic Interference.Secondary shielding layer 5802 The upper surface 1501 of covering part packaging body 150 and partial at least one surface mounted component 160.Secondary shielding layer 5802 is sudden and violent Reveal the first contact 160a of at least one surface mounted component 160, and the second of at least one surface mounted component 160 of contact Contact 160b.Screened film 580 is electrically connected to the ground plane of first substrate 110.In an embodiment of the present invention, screened film 580 generation type can be or can include but is not limited to for example by chemical vapor deposition, electroless-plating, electrolysis plating, spray Painting, printing and sputter.Screened film 580 can be or can include but is not limited to such as aluminium, copper, chromium, tin, gold, silver, nickel, stainless Steel or other suitable metal or alloy.
Conductive connecting material 18 is located on the upper surface 1501 of the packaging body 150.Conductive connecting material 18 includes first The conductive connecting material 182 of conductive connecting material 181 and second.First conductive connecting material 181 and the second conductive connecting material 182 Electrically isolation, therefore short circuit phenomenon will not be produced.First conductive connecting material 181 is connected at least one surface mounted component 160 the first contact 160a, the second conductive connecting material 182 connect the secondary shielding layer 5802.In embodiments of the invention In, conductive connecting material 18 can be but not limited to conducting resinl.In another embodiment of the invention, conductive connecting material 18 can To be but not limited to solder (solder).
Second substrate 130 is located at the top of upper surface 1501 of the packaging body 150.Second substrate 130 has upper surface 131u, lower surface 131b and side 131S.Lower surface 131b is relative to upper surface 131u.In an embodiment of the present invention, second Substrate 130 can be or can include but is not limited to such as silicon, silica or other silicides.Second substrate 130 can have Thickness from 10 μm to 3000 μm, for example, in an embodiment of the present invention, the thickness can be upper surface 131u and lower surface The distance between 131b.
Formed with the 3rd trace layer 132 on the lower surface 131b of second substrate 130.3rd trace layer 132 includes the first gold medal Belong to layer 132f and second metal layer 132g.The first metal layer 132f and second metal layer 132g are separated by space 132S, to keep away Exempt from short circuit.In an embodiment of the present invention, the first metal layer 132f can be but not limited to for example connect weld pad (connection Pad), second metal layer 132g can be but not limited to such as ground mat (ground pad).The first metal layer 132f and second Metal level 132g can be or can include but is not limited to such as copper or other suitable metal or alloy.In the another of the present invention In embodiment, the first metal layer 132f and second metal layer 132g can be made up of different metal or alloy.The first metal layer 132f can have the thickness from 1 μm to 72 μm, and second metal layer 132g has the thickness from 1 μm to 72 μm.The present invention's In embodiment, second metal layer 132g area of the area relatively larger than the first metal layer 132f.In another implementation of the present invention In example, second metal layer 132g can be used as but be not limited to the ground plane of the second substrate 130.In an embodiment of the present invention, due to The second metal layer 132g is formed at the lower surface 131b of second substrate 130, and electrically connects via the screened film 580 It is connected to the ground plane of the first substrate 110.As depicted in Figure 13 A, the area of the second substrate 130 is relatively larger than the secondary shielding layer 5802 area, and second metal layer 132g area is relatively larger than the area of the secondary shielding layer 5802, therefore, the second gold medal It is larger to belong to layer 132g dead areas, there is preferable metallic shield effect.
Second substrate 130 includes conductive hole 134.Conductive hole 134 includes at least one first conductive hole 134a and at least one Individual second conductive hole 134b.At least one first conductive hole 134a through the second substrate 130 with connect the first metal layer 132f with 4th trace layer 133.And at least one second conductive hole 134b through the second substrate 130 to connect second metal layer 132g and the Four trace layers 133.In an embodiment of the present invention, at least one first conductive hole 134a and at least one second conductive hole 134b Can be but not limited to cylinder, cone or other shapes, visual demand on the second substrate 130 by laser, sandblast (sandblasting) and/or etching etc. mode form at least one first conductive hole 134a and at least one second conductive hole 134b.At least one first conductive hole 134a and at least one second conductive hole 134b are upper surface 131u's and lower surface 131b Opening may include but be not limited to circular, square or other shapes.
Formed with antenna 126 on the upper surface 131u of second substrate 130.Antenna 126 can be the 4th trace layer 133 extremely A few part is additionally formed in the upper surface 131u of the second substrate 130 antenna stack.Antenna 126 connects at least one conduction Hole 134a and at least the second conductive hole 134b.In an embodiment of the present invention, antenna 126 can be or can include but is not limited to Such as copper or other suitable metal or alloy.Antenna 126 can have the thickness from 1 μm to 72 μm.In embodiments of the invention In, antenna 126 is formed at second substrate 130, and the second substrate 130 is located on the packaging body 150, therefore, can reduce Stack type semiconductor structure 800 is arranged on space occupied on the circuit board or support plate of device/system, to accommodate other elements Or be advantageous to other relevant designs.It is electrically connected with because antenna 126 passes through the conductive hole 134 being formed in the second substrate 130 To first substrate 110, the first substrate 110 is electrically connected to relative to through the conductive hole being formed in packaging body 150 For there are preferable process yields.
In an embodiment of the present invention, the signal (not shown) that stack type semiconductor structure 800 receives via antenna 126 can Pacify via at least one first conductive hole 134a, the first metal layer 132f, the first conductive connecting material 181 and at least one surface First contact 160a of dress element 160 by reception signal feed-in (feed) but is not limited to RF front-end module 110a.In the present invention Another embodiment in, RF front-end module 110a can via at least one surface mounted component 160 the first contact 160a, The signal that one conductive connecting material 181, the first metal layer 132f and at least one first conductive hole 134a will launch is sent to Antenna 126.That is, at least one first conductive hole 134a, the first metal layer 132f, the and of the first conductive connecting material 181 First contact 160a of at least one surface mounted component 160 can be used as stack type semiconductor knot in an embodiment of the present invention The signal feed-in of structure 800 and transmission path.In an embodiment of the present invention, at least one second conductive hole 134b, the second metal Layer 132g, the second contact 160b of the second conductive connecting material 182 and at least one surface mounted component 160 are electrically connected to the The ground plane (not illustrating) of one substrate 110, using the signal return path (return as stack type semiconductor structure 800 ) or grounding path (ground path) path.In another embodiment of the invention, at least one second conductive hole 134b, Two metal level 132g, the second conductive connecting material 182 and screened film 580 are electrically connected to the ground plane of the first substrate 110, to make For the signal return path or grounding path of stack type semiconductor structure 800.In an embodiment of the present invention, when antenna 126 will When receiving or launching high-frequency signal, by antenna 126, the first conductive hole 134a, the second conductive hole 134b, the second substrate 130, first The structure that metal level 132f and second metal layer 132g are formed can produce signal resonance in operating frequency, pass high-frequency signal The circuit that is delivered in encapsulation is radiated air and received again by another external receiver.
In an embodiment of the present invention, when at least one surface mounted component 160 is inductor, can prevent from outside High-frequency noise destroy stack type semiconductor structure 800, and can be as electrostatic discharge protective (electrostatic Discharge protection, ESD protection).In another embodiment of the invention, when at least one surface is pacified When dress element 160 is inductor, the direct current spike (DC spike) from outside can be grounded and then avoid damage to stack half Conductor structure 800.In another embodiment of the invention, can conduct when at least one surface mounted component 160 is capacitor A part for impedance matching circuit, to adjust the impedance of antenna 126.
Figure 13 B are refer to, it illustrates the circuit diagram of Figure 13 A stack type semiconductor structure.Positioned at Figure 13 A stacking The lower surface 131b of second substrate 130 of formula semiconductor structure 800 the first metal layer 132f and second metal layer 132g is mutual Do not contact.As shown in Figure 13 B, there is space 132S at interval between the first metal layer 132f and second metal layer 132g.It is at least one First conductive hole 134a is located at the first metal layer 132f opening and connected with the first end 160a of at least one surface mounted component 160 Connect, and at least one second conductive hole 134b is located at second metal layer 132g opening and at least one surface mounted component 160 The second end 160b connections.As shown in the equivalent circuit in Figure 13 B, at least one surface mounted component 160 can be with front-end module 110a equiva lent impedance 110aP is in parallel.In an embodiment of the present invention, when at least one surface mounted component 160 is inductor When, it can prevent that the high-frequency noise from outside destroys stack type semiconductor structure 800, and can be as electrostatic discharge protective (electrostatic discharge protection,ESD protection).In another embodiment of the invention, when When at least one surface mounted component 160 is inductor, the direct current spike (DC spike) from outside can be grounded and then be kept away Exempt to destroy stack type semiconductor structure 800.In another embodiment of the invention, when at least one surface mounted component 160 is , can be as a part for impedance matching circuit, to adjust the impedance of antenna 126 during capacitor.
Figure 14 A are refer to, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Formula semiconductor structure 900 can be stack type semiconductor structure 900 similar in appearance to stack type semiconductor structure 800, its difference The first metal layer 132f and second metal layer 132g the first metal layer for being shaped differently than stack type semiconductor structure 800 132f and second metal layer 132g shape.And in stack type semiconductor structure 900, at least one first conductive hole 134a It is different from at least one second conductive hole 134b relative position in stack type semiconductor structure 800, at least one first leads Electric hole 134a and at least one second conductive hole 134b relative position.But at least one first conductive hole 134a and at least one Second conductive hole 134b stack type semiconductor structure 900 and other elements annexation similar in appearance to stack type semiconductor structure At least one first conductive hole 134a and at least one second conductive hole 134b and other elements annexation in 800.
With reference to figure 14B, it illustrates the circuit diagram of Figure 14 A stack type semiconductor structure.Circuit shown in Figure 14 B is similar In circuit shown in Figure 13 B, its difference is at least one first conductive hole 134a and at least one second conductive hole 134b Relative position and Figure 13 B at least one first conductive hole 134a and at least one second conductive hole 134b relative position not Together.And the first metal layer 132f's and second metal layer 132g is shaped differently than the first metal layer 132f and second in Figure 13 B Metal level 132g shape.
With reference to figure 15, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 810 can be similar in appearance to the stack type semiconductor structure 800 depicted in Figure 13 A, and its difference is stack half The second metal layer 132g of conductor structure 810 instead of the second conductive connecting material 182 and of stack type semiconductor structure 800 Two screen layers 5802.The second metal layer 132g of stack type semiconductor structure 810 forms screened film with first screen layer 5801 580.In other words, the second metal layer 132g of stack type semiconductor structure 810 forms a part for screened film 580.Stack The side 131S of second substrate 130 of semiconductor structure 810 substantially flushes with first screen layer 5801, relative to Figure 13 A's Stack type semiconductor structure 800 has less size.
With reference to figure 16, it illustrates the sectional view of the stack type semiconductor structure according to another embodiment of the present invention.Stack Semiconductor structure 910 can be similar in appearance to the stack type semiconductor structure 900 depicted in Figure 14 A, and its difference is stack half The second metal layer 132g of conductor structure 910 instead of the second conductive connecting material 182 and of stack type semiconductor structure 900 Two screen layers 5802.The second metal layer 132g of stack type semiconductor structure 910 forms screened film with first screen layer 5801 580.In other words, the second metal layer 132g of stack type semiconductor structure 910 forms a part for screened film 580.Stack The side 131S of second substrate 130 of semiconductor structure 910 substantially flushes with first screen layer 5801, relative to Figure 14 A's Stack type semiconductor structure 900 has less size.
Figure 17 to 21 is refer to, it illustrates the flow chart making of Figure 13 A stack type semiconductor structure.
With reference to figure 17, there is provided the first substrate 110, at least one surface mounted component 160, RF front-end module 110a, receipts Generate device chipset 110b, memory 110c, surface mounted component 110d, voltage-stablizer 110e and microcontroller/special integrated electricity Road 110f.
First substrate 110 has upper surface 111u and lower surface 111b, and lower surface 111b is relative to upper surface 111u.
At least one surface mounted component 160 have the first contact 160a and the second contact 160b and the first contact 160a with Second contact 160b is respectively then in the upper surface 111u of the first substrate 110.The second of at least one surface mounted component 160 connects Point 160b is electrically connected to the ground plane (not shown) of the first substrate 110.In an embodiment of the present invention, first substrate 110 Can have the connection weld pad or trace being electrically connected with ground plane via interlayer circuit, at least one table on the 111u of upper surface Second contact 160b of face installation elements 160 may be connected to the connection weld pad or trace so as to the ground connection with the first substrate 110 Face is electrically connected with.
The technologies such as routing, welding or flip-chip can be used according to the encapsulation kenel of Individual elements by least one surface It is installation elements 160, RF front-end module 110a, transceiver chip set 110b, memory 110c, surface mounted component 110d, steady Depressor 110e and microcontroller/application specific integrated circuit 110f is connected to the circuit on the upper surface 111u of the first substrate 110. In an embodiment of the present invention, surface mounted component 110d is similar at least one surface mounted component 160, and its difference exists It is smaller by contrast in surface mounted component 110d size and the size of at least one surface mounted component 160, such as surface Installation elements 110d height is less than the height of at least one surface mounted component 160.In an embodiment of the present invention, at least one Height of the height of individual surface mounted component 160 relatively larger than other elements on the 111u of upper surface.In another implementation of the present invention In example, at least one surface mounted component 160 can be but not limited to 0603 element and visually demand is with larger sized terminal (terminal) element is replaced so that at least one surface mounted component 160 is height highest element on the 111u of upper surface.
With reference to figure 18, can be used packaging body 150 encapsulate at least one surface mounted component 160, RF front-end module 110a, Transceiver chip set 110b, memory 110c, surface mounted component 110d, voltage-stablizer 110e and microcontroller/special integrated Circuit 110f and the first substrate 110 upper surface 111u, and expose the first of at least one surface mounted component 160 and connect Point 160a and the second contact 160b.In an embodiment of the present invention, exposure shaping (exposed molding) mode profit can be used Connect with the first contact 160a and second that packaging body 150 encapsulates said elements and exposes at least one surface mounted component 160 Point 160b.In another embodiment of the invention, covering shaping (over-mold) mode can be used to be encapsulated using packaging body 150 Said elements, packaging body 150 then is abraded to expose at least one surface mounted component in a manner of grinding (polishing) again 160 the first contact 160a and the second contact 160b.
As shown in figure 19, can be along the first substrate 110 after the Cutting Road P1 cutting encapsulation in Figure 18, and sealed along passing through The side 111S of the first substrate 110, the upper surface 1501 of packaging body 150 and the side 1502 of dress form screened film 580, to be formed Encapsulating structure 800a.In an embodiment of the present invention, can be along the side 111S of the first substrate 110, packaging body 150 upper surface 1501 and side 1502 formed screened film 580, then in a manner of laser drill on screened film 580 drilling with least one table of exposure The the first contact 160a and partial encapsulation body 150 of face installation elements 160.In another embodiment of the invention, it is available but It is not limited to mask (mask) and plating mode forms the pattern of required screened film 580.
As shown in figure 20, it is possible to provide multiple second substrates 130, each second substrate 130 have upper surface 131u with Surface 131b, lower surface 131b is relative to upper surface 131u.
Formed with antenna 126 on the upper surface 131u of second substrate 130.Formed on the lower surface 131b of second substrate 130 There is the 3rd trace layer 132.3rd trace layer 132 includes the first metal layer 132f and second metal layer 132g.
Second substrate 130 includes at least one first conductive hole 134a and at least one second conductive hole 134b.At least one Individual first conductive hole 134a runs through the second substrate 130 to connect antenna 126 and the first metal layer 132f.At least one second is conductive Hole 134b runs through the second substrate 130 to connect antenna 126 and second metal layer 132g.
Conductive connecting material 18 can be formed on the first metal layer 132f and second metal layer 132g, to form encapsulation knot Structure 800b.In an embodiment of the present invention, conductive connecting material 18 can be but not limited to conducting resinl.Another implementation of the present invention In example, conductive connecting material 18 can be solder.
With reference to figure 21, using the conductive connecting material 18 in Figure 20 by encapsulating structure 800b the first metal layer 132f with First contact 160a connections of encapsulating structure 800a at least one surface mounted component 160 in Figure 19, and will be sealed in Figure 20 The second of encapsulating structure 800a at least one surface mounted component 160 in assembling structure 800b second metal layer 132g and Figure 19 Contact 160b connections.Formed after being cut after connection encapsulating structure 800a and 800b further along Cutting Road P1 indivedual or single in Figure 13 A Individual stack type semiconductor structure 800.In an embodiment of the present invention, for knife used in the encapsulating structure in cutting drawing 21 The thickness of tool is less than Cutting Road P1 thickness, and therefore, the side 131S of second substrate 130 protrudes from the packaging body 150 side 1502.In another embodiment of the invention, for cutter used in the encapsulating structure in cutting drawing 21 Thickness substantially close to the Cutting Road P1 width, therefore, the side 131S of second substrate 130 substantially with The side 1502 of the packaging body 150 flushes, and has comparatively smooth outward appearance and less size.
Figure 22 to 26 is refer to, it illustrates the flow chart making of Figure 15 stack type semiconductor structure.
With reference to figure 22, there is provided multiple first substrates 110, at least one surface mounted component 160, RF front-end module 110a, transceiver chip set 110b, memory 110c, surface mounted component 110d, voltage-stablizer 110e and microcontroller/special Integrated circuit 110f.
First substrate 110 has upper surface 111u and lower surface 111b, and lower surface 111b is relative to upper surface 111u.
At least one surface mounted component 160 have the first contact 160a and the second contact 160b and the first contact 160a with Second contact 160b is respectively then in the upper surface 111u of the first substrate 110.The second of at least one surface mounted component 160 connects Point 160b is electrically connected to the ground plane (not shown) of the first substrate 110.In an embodiment of the present invention, first substrate 110 Can have the connection weld pad or trace being electrically connected with ground plane via interlayer circuit, at least one table on the 111u of upper surface Second contact 160b of face installation elements 160 may be connected to the connection weld pad or trace so as to the ground connection with the first substrate 110 Face is electrically connected with.
The technologies such as routing, welding or flip-chip can be used according to the encapsulation kenel of Individual elements by least one surface It is installation elements 160, RF front-end module 110a, transceiver chip set 110b, memory 110c, surface mounted component 110d, steady Depressor 110e and microcontroller/application specific integrated circuit 110f is connected to the circuit on the upper surface 111u of the first substrate 110. In an embodiment of the present invention, surface mounted component 110d is similar at least one surface mounted component 160, and its difference exists It is smaller by contrast in surface mounted component 110d size and the size of at least one surface mounted component 160, such as surface Installation elements 110d height is less than the height of at least one surface mounted component 160.In an embodiment of the present invention, at least one Height of the height of individual surface mounted component 160 relatively larger than other elements on the 111u of upper surface.In another implementation of the present invention In example, at least one surface mounted component 160 can be but not limited to 0603 element and visually demand is with larger sized terminal (terminal) element is replaced so that at least one surface mounted component 160 is height highest element on the 111u of upper surface.
Multiple second substrates 130 are provided, each second substrate 130 has upper surface 131u and lower surface 131b, following table Face 131b is relative to upper surface 131u.Formed with antenna 126 on the upper surface 131u of second substrate 130.Under second substrate 130 Formed with the 3rd trace layer 132 on the 131b of surface.3rd trace layer 132 includes the first metal layer 132f and second metal layer 132g。
Second substrate 130 includes at least one first conductive hole 134a and at least one second conductive hole 134b.At least one Individual first conductive hole 134a runs through the second substrate 130 to connect antenna 126 and the first metal layer 132f.At least one second is conductive Hole 134b runs through the second substrate 130 to connect antenna 126 and second metal layer 132g.
As shown in figure 22, can be used conductive connecting material 18, such as solder 18, by the first metal layer 132f with it is at least one The first end 160a connections of surface mounted component 160, and by second metal layer 132g and at least one surface then element 160 The second end 160b connections.
With reference to figure 23, packaging body 150 can be used to coat (encapsluate) at least one surface mounted component 160, radio frequency Front-end module 110a, transceiver chip set 110b, memory 110c, surface mounted component 110d, voltage-stablizer 110e, microcontroller Device/application specific integrated circuit 110f and the first substrate 110 upper surface 111u, to form encapsulating structure (package structure)810a.In an embodiment of the present invention, perforate (opening, figure available but that be not limited to the first substrate 110 Do not show) as shaping channel (molding channel), the first lining after being connected with least one surface mounted component 160 Space (the lower surface 131b of the upper surface 111u of the first substrate 110 and the second substrate 130 between the substrate 130 of bottom 110 and second Between space) injection packaging body 150 is packaged technique.In another embodiment of the invention, the second substrate can be used 130 as the fixture (Mold Chase) of casting inject packaging body 150 the upper surface 111u and second of first substrate 110 Space between the lower surface 131b of substrate 130, therefore extra mould is not needed in process, cost can be reduced.
With reference to figure 24, irrigation canals and ditches 5801a can be formed in Figure 23 encapsulating structure 810a.In an embodiment of the present invention, may be used Using but be not limited to cutter and cut from the lower surface 111b of the first substrate 110 initially towards upper surface 111u direction, with the Irrigation canals and ditches 5801a is formed in the packaging body 150 of one substrate 110 and uncoated element, and in the second metal for reaching the second substrate 130 Stop cutting action during layer 132g surfaces.In other words, the lower surface 111b of irrigation canals and ditches 5801a from the first substrate 110 extends to The second metal layer 132g of two substrates 130.
With reference to figure 25, conductive material can be inserted in irrigation canals and ditches 5801a to form first screen layer 5801.Conductive material can be But it is not limited to such as conducting resinl.First screen layer 5801 is accessible or is electrically connected with the ground plane of the first substrate 110.In other words Say, first screen layer 5801 can be electrically connected with the ground plane of second metal layer 132g and the first substrate 110.
With reference to figure 26, cutting technique can be used to cut the encapsulating structure 810a being connected in Figure 25 along Cutting Road P1, with shape Into stack type semiconductor structure 810 as shown in figure 15.In an embodiment of the present invention, it can be used but be not limited to cutter, along Figure 25 Cutting Road P1 makes cutter from first screen layer 5801 by second metal layer 132g, the second substrate 130 and antenna 126 So that connected encapsulating structure 810a to be cut, and form stack type semiconductor structure 810 as shown in figure 15.In the reality of the present invention Apply in example, be less than for the thickness of cutter used in the encapsulating structure in cutting drawing 25 in Figure 24 to form irrigation canals and ditches 5801a The thickness of cutter..As shown in Figure 26 and Figure 15, in an embodiment of the present invention, the second substrate of stack type semiconductor structure 810 130 length can be more than the length of the first substrate 110.In other words, the first substrate 110 of stack type semiconductor structure 810 Side 111S does not flush with the side 131S of the second substrate 130.
Figure 27 A are refer to, it illustrates the schematic diagram of the antenna of Figure 13 A stack type semiconductor structure.In the reality of the present invention Apply in example, the pattern that the antenna 126 of Figure 13 A stack type semiconductor structure 800 can be as shown in fig. 27 a.Can be in rectangle or side The metal level 126 of shape forms rectangle fluting (slot) 1261 to form notch antenna (slot antenna) 126.In the present invention Another embodiment in, antenna 126 can also have the pattern of other forms, e.g. loop aerial (loop antenna).
Figure 27 B illustrate the reflection loss schematic diagram of Figure 27 A antenna.Have in Figure 13 A stack type semiconductor structure 800 As Figure 27 A notch antenna 126 when, the reflection loss (return loss) of its signal as shown in figure 27b, its midpoint m1 institute it is right The frequency and reflection loss answered are respectively 2.404GHz and 9.364dB, and frequency and reflection loss corresponding to point m2 are respectively 2.480GHz and 9.461dB, frequency and reflection loss corresponding to point m3 are respectively 2.440GHz and 25.059dB.In other words Say, the working frequency of Figure 13 A stack type semiconductor structure 800, which is in, has relatively small reflection damage when near 2.440GHz Lose ratio.Therefore, the stack type semiconductor structure 800 that discloses of the present invention can be operated effectively but to be not limited to working frequency 2.440GHz attached Closely.
Figure 28 A are refer to, it illustrates the schematic diagram of the antenna of Figure 13 A stack type semiconductor structure.In the reality of the present invention Apply in example, the antenna 126 of Figure 13 A stack type semiconductor structure 800 can be but be not limited to loop aerial (loop antenna) 126.Antenna 126 includes at least one second leading as at least one first conductive hole 134a and earth terminal of signal feed side Electric hole 134b.
Figure 28 B are refer to, it illustrates the reflection loss schematic diagram of Figure 28 A antenna.In Figure 13 A stack type semiconductor knot When structure 800 has the loop aerial 126 such as Figure 28 A, the reflection loss of its signal is as shown in Figure 28 B.In Figure 13 A stack half The working frequency of conductor structure 800, which is in, has relatively small reflection loss ratio when near 2.450GHz.Therefore, the present invention takes off The stack type semiconductor structure 800 shown can effectively be operated but is not limited near working frequency 2.450GHz.
Figure 29 A are refer to, it illustrates Figure 13 A stack type semiconductor structure and applies schematic diagram in system support plate.Electronics Device 1 includes the stack type semiconductor structure 800 being located on system support plate 3, processor (Processor) 5, sensor (sensor) 7 with PMU (Power Management) 9.Processor 5 carries out calculation process for system documentation.Pass Sensor 7 may include but be not limited to for example, be used for the device of detection temperature, humidity, speed, direction or pressure.Stacking can be passed through The information of electronic installation 1 is transmitted into external device (ED) or from external device (ED) receive information by formula semiconductor structure 800.Power management Unit 9 provides system power supply and adjusts output voltage according to system operating state.In an embodiment of the present invention, system support plate 3 Such as rectangle substrate 3 can be but not limited to.Stack type semiconductor structure 800 can be arranged on system support plate 3 close to corner, Preferably close to the long side of rectangle support plate 3, produce inducing current (will introduce below) whereby with improve radiation efficiency and Radiation gain, so increase wireless transmission distance or in same transmission range with less power complete signal transmission with up to The effect of power saving.
Figure 29 B are refer to, it illustrates the CURRENT DISTRIBUTION signal of the antenna of the stack type semiconductor structure depicted in Figure 29 A Figure.In an embodiment of the present invention, antenna 126 can be similar to the loop aerial 126 shown in Figure 28 A, and arrow A show annular day The sense of current and current strength on line 126.
Figure 29 C are refer to, it illustrates the CURRENT DISTRIBUTION of system support plate shown in Figure 29 A and the antenna of stack type semiconductor structure Schematic diagram.In an embodiment of the present invention, the girth of antenna 126 can be but be not limited to receive or transmission signal wavelength four/ One (1/4 λ), and the length of the long side of system support plate 3 is received more than or equal to antenna 126 or a quarter of transmission signal wavelength (1/4λ).As shown in Figure 29 C, when stack type semiconductor structure 800 is installed to system support plate 3, electric current (such as arrow on antenna 126 Shown in number A) (excite) can be excited to go out reverse current (as shown in arrow B) on support plate 3, when the length of the long side of system support plate 3 Received more than or equal to antenna 17 or during a quarter of transmission signal wavelength (1/4 λ), arrow A and the electric current represented by arrow B The electric current of the long side of (induce) system support plate 3 can be induced (as shown in arrow C).In an embodiment of the present invention, working frequency is worked as For 2.45GHz when, there is radiation efficiency and spoke of the stack type semiconductor structure 800 before system support plate 3 is attached to of antenna 126 The peak value for penetrating gain (Radiation Gain) is respectively 2% and negative 16.5dB.And when the stack type semiconductor with antenna 126 After structure 800 is attached to system support plate 3, caused radiation efficiency and radiation gain in same working frequency The peak value of (Radiation Gain) is respectively 45% and negative 0.94dB.In other words, antenna 126 and system support plate 3 are passed through Design, inducing current (as shown in arrow C in Figure 29 C) can be produced to improve radiation efficiency and radiation gain, and then increase nothing Line transmission range completes signal transmission with up to the effect of power saving in same transmission range with less power.
With reference to figure 30, it illustrates the schematic block circuit diagram of Figure 13 A stack type semiconductor structure.Stack type semiconductor structure 800 comprising at least one surface mounted component 160, RF front-end module 110a, transceiver chip set 110b, memory 110c, Surface mounted component 110d, voltage-stablizer 110e and microcontroller/application specific integrated circuit 110f and antenna 126.Such as Figure 30 institutes Show, transceiver chip set 110b connection RF front-end modules 110a, memory 110c and voltage-stablizer 110e.Voltage-stablizer 110e connections Microcontroller/application specific integrated circuit 110f.RF front-end module 110a connects antenna by least one surface mounted component 160 126.The signal that antenna 126 receives can be via at least one feed-in RF front-end module 110a of surface mounted component 160.And it is intended to send out The signal penetrated can be sent to antenna 126 via at least one surface mounted component 160.
In another embodiment of the invention, the stacking described with reference to figure 27A, Figure 28 A, Figure 29 A and Figure 30 diagram Formula semiconductor structure 800 and antenna 126 can also be shown in Figure 14 A, Fig. 3 or Fig. 4 stack type semiconductor structure 810,900 or 910 and antenna 126 substitute without influence its operation and benefit.
In summary, although the present invention is disclosed above with embodiment, so it is not limited to the present invention.Institute of the present invention Has usually intellectual in category technical field, without departing from the spirit and scope of the present invention, when various changes and profit can be made Decorations.Therefore, the scope of protection of the present invention is defined by those of the claims.

Claims (20)

1. a kind of stack type semiconductor structure, it is characterised in that it is included：
First substrate, it has upper surface；
Second substrate, it has upper surface, lower surface, at least one first conductive hole and at least one second conductive hole, described Relative to the upper surface, the lower surface of second substrate faces the upper surface of first substrate for lower surface；
At least one passive device, at least one passive device are located at the upper surface of first substrate and second lining Between the lower surface at bottom, and first substrate and second substrate are electrically connected with the first contact and the second contact；
Antenna, it is arranged on the upper surface of second substrate, and institute is electrically connected with by least one first conductive hole The first contact is stated, and second contact is electrically connected with by least one second conductive hole；
Screened film, cover at least one passive device, and exposure first contact, and contact second contact.
2. stack type semiconductor structure according to claim 1, it is characterised in that it further includes packaging body, packaging body bag The portion of upper surface of the first substrate, the portion lower surface of the second substrate and at least one passive device are covered, the screened film is at least Coat the portion of upper surface of the side of first substrate, the side of the packaging body and the packaging body.
3. stack type semiconductor structure according to claim 2, it is characterised in that it further includes the first metal layer and second Metal level, the first metal layer and the second metal layer are located at the lower surface of second substrate, the first metal layer At least one first conductive hole is connected, and the second metal layer connects at least one second conductive hole.
4. stack type semiconductor structure according to claim 3, it is characterised in that the first metal layer is electrically connected with institute The first contact of at least one surface mounted component is stated, and the second metal layer is electrically connected with least one passive device The second contact.
5. stack type semiconductor structure according to claim 3, it is characterised in that the second metal layer forms the screen Cover a part for film.
6. stack type semiconductor structure according to claim 2, it is characterised in that described in the screened film electric connection extremely Second contact of a few passive device.
7. stack type semiconductor structure according to claim 3, it is characterised in that it further includes conductive connecting material, institute State the first contact that conductive connecting material connects the first metal layer and at least one passive device.
8. stack type semiconductor structure according to claim 7, it is characterised in that described in the conductive connecting material connection Second metal layer and the screened film.
9. stack type semiconductor structure according to claim 7, it is characterised in that described in the conductive connecting material connection Second contact of second metal layer and at least one passive device.
10. a kind of electronic installation, it is included：
A kind of electronic installation, it is included：
Support plate, the support plate have corner；And
Stack type semiconductor structure, the stack type semiconductor structure be located on the corner of the support plate and comprising：
First substrate；
Packaging body, coat first substrate；
Second substrate, positioned at the top of the packaging body；
Antenna, it is arranged on a upper surface of second substrate；
The length of the long side of wherein described support plate is more than or equal to the girth of antenna.
11. stack type semiconductor structure according to claim 10, it is characterised in that it further includes at least one surface peace Element is filled, at least one surface mounted component connects between first substrate and second substrate and with first Point and the second contact, first contact are electrically connected with first substrate and second substrate with second contact.
12. stack type semiconductor structure according to claim 11, it is characterised in that at least one surface installation member Second contact of part is electrically connected to a ground plane of first substrate.
13. stack type semiconductor structure according to claim 12, it is characterised in that second substrate includes：
At least one first conductive hole, it is electrically connected with described the first of the antenna and at least one surface mounted component Contact；And
At least one second conductive hole, it is electrically connected with described the second of the antenna and at least one surface mounted component Contact.
A kind of 14. stack type semiconductor structure, it is characterised in that including：
One first substrate, it has a upper surface；
One second substrate, it has a lower surface；
One first semiconductor chip, it is located at the upper surface of the first substrate；
One second semiconductor chip, it is located at the lower surface of the second substrate；
One first surface pastes element, and it is located between the upper surface of the first substrate and the lower surface of the second substrate simultaneously It is electrically connected with the first substrate and the second substrate；And
One packaging body, its coat a part for the upper surface of the first substrate, the second substrate the lower surface a part, First semiconductor chip, second semiconductor chip and the first surface paste element.
15. stack type semiconductor structure as claimed in claim 14, it is characterised in that the first surface, which pastes element, includes one First contact and one second contact, the first surface pastes first contact of element and second contact be connected to this The upper surface of one substrate and the lower surface of the second substrate.
16. stack type semiconductor structure as claimed in claim 14, it is characterised in that the first surface pastes element located at this On first substrate, the stack type semiconductor structure further includes：
One second surface pastes element, and it is located on the second substrate and pastes element with the first surface and docks.
17. stack type semiconductor structure as claimed in claim 16, it is characterised in that the first surface paste element and this Element is pasted on two surfaces respectively includes one first contact and one second contact, and the first surface is pasted first contact of element and is somebody's turn to do Second contact pastes first contact of element with the second surface respectively and second contact docks.
18. stack type semiconductor structure as claimed in claim 14, it is characterised in that the packaging body includes：
One first packaging body, its coat the part of the upper surface of the first substrate, first semiconductor chip and this first Paste element in surface；And
One second packaging body, its coat the part of the lower surface of the second substrate, second semiconductor chip and this second Paste element in surface.
19. stack type semiconductor structure as claimed in claim 16, it is characterised in that the first surface paste element with this The docking height that element is pasted on two surfaces is more than the gross thickness of first semiconductor chip and second semiconductor chip, make this A space is formed between semiconductor chip and second semiconductor chip；
The stack type semiconductor structure further includes：
One bonding wire, it is located in the space.
20. stack type semiconductor structure as claimed in claim 14, it is characterised in that the first substrate includes a first line Layer, the second substrate include a tertiary circuit layer, the first surface paste element by first line layer be electrically connected at this Semiconductor chip, second semiconductor chip can paste element electric connection by the tertiary circuit layer and the first surface In the first semiconductor chip.
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