CN107416762B - Silicon nano-pore structure and manufacturing method thereof - Google Patents
Silicon nano-pore structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a silicon nanopore structure and a manufacturing method thereof. The method comprises the following steps: a silicon chip on the insulating substrate as a substrate; depositing SiN nano films on the surfaces of two sides of the substrate, and etching the SiN on one side of the substrate to form a silicon surface; simultaneously etching the SiN nano film to form a matrix release window; uniformly dispersing metal nanoparticles on the silicon surface; depositing a protective layer on the metal nano-particles and the silicon surface, coating a layer of tackifier and glue of alkali-resistant etching liquid on the protective layer, and etching the silicon substrate by using the alkali solution to obtain the self-supporting nano-film consisting of the SOI oxide layer, the SOI top layer silicon, the metal nano-particles, the protective layer and the protective glue. Removing the protective glue, the tackifier and the SOI oxide layer, and etching to remove part of the protective layer above the self-supporting nano film to obtain a protective layer window; and (3) preparing an etching liquid by using hydrogen peroxide and hydrofluoric acid, and assisting the metal nano particles to etch to obtain the silicon nano hole structure. The invention has simple process, can be repeatedly recycled and has wide application prospect in the field of biochemical detection.
Description
Technical Field
The invention belongs to the technical field of micro-nano device preparation and application, relates to a nanopore manufacturing method, and particularly relates to a silicon nanopore structure and a manufacturing method thereof.
Background
The use of nanopores (nanopores) for base sequence recognition of DNA molecules has been studied for 20 years. When the DNA molecule passes through the nanopore under the action of the electric field force, the ion current amplitude in the nanopore is changed, and the base is identified by the current amplitude. With the research of the nanopore DNA sequencing method, scientists think that the nanopore array sensor can realize DNA parallel detection and achieve the purpose of high-throughput sequencing. The most promising of them is the technology of total internal reflection fluorescence parallel detection of DNA sequences based on solid-state nanopore arrays. The DNA via hole signals of each nanopore in the nanopore array are captured by means of an electron multiplying CCD (charge coupled device) camera, so that the optical signals and the ion current signals are in one-to-one correspondence, and high-throughput DNA sequencing is realized. (McNally B, Singer A, Yu Z, et al, optical recording of converted DNA nucleotides for use in detecting DNA sequences nanopore arrays [ J ]. Nano letters,2010,10(6):2237-
As a core functional unit, the fabrication of solid state nanopores is directly related to the performance index of the detection system. Solid-state nanopore fabrication methods suitable for DNA sequencing can be summarized into two broad categories according to the fabrication mechanism: the first is a "top-down" etching technique based on high energy particles (e.g., focused ion beam and high energy electron beam); the second category is based on the first category on "bottom-up" hole-shrinkage techniques (e-beam assisted deposition, atomic layer deposition, etc.). However, the existing solid-state nanopore manufacturing methods are all based on a nanometer-scale processing tool, such as a Focused Ion Beam (FIB), a Transmission Electron Microscope (TEM), and the like, and are limited by the cavity of the device, so that the manufacturing efficiency is low. Thus, the existing methods constrain the fabrication and application of solid-state nanopore array sensors. How to realize the manufacture of the solid-state nanopore array with low cost and high efficiency is a serious challenge to the micro-nano manufacturing technology by the nanopore DNA sequencing technology. Therefore, the research on the manufacturing method of the novel solid-state nanopore array is of great significance. The invention is to design a silicon nanopore chip structure and how to manufacture. The manufacturing method of the solid-state nanopore chip with simple process and low manufacturing cost has important significance.
Disclosure of Invention
In view of the above disadvantages of the prior art, the present invention provides a silicon nanopore structure and a method for fabricating the same, which are used to solve the problem that the prior art is not feasible, and simultaneously achieve the compatibility between the prior art and the CMOS technology, thereby effectively reducing the complexity of the fabrication process.
In order to achieve the above and other related objects, the present invention provides a silicon nanopore structure and a method for fabricating the same, the method at least comprising:
1) providing a Silicon-On-Insulator (SOI) wafer On an insulating substrate as a substrate;
2) depositing a layer of SiN nano film on the surfaces of two sides of the substrate;
3) etching the SiN nano film on one side of the substrate to form a silicon surface;
4) etching the SiN nano film on one side of the substrate to form a substrate release window;
5) uniformly dispersing metal nanoparticles on the silicon surface;
6) depositing a protective layer over the metal nanoparticles and silicon surface;
7) coating a layer of tackifier and glue for resisting alkaline etching liquid on the protective layer;
8) etching the silicon substrate by using an alkaline solution to obtain a self-supporting nano film consisting of an SOI oxide layer, SOI top silicon, the metal nano particles, the protective layer and the protective adhesive;
9) removing the protective glue and the SOI oxide layer;
10) etching off part of the protective layer above the self-supporting nano film by using an etching method again;
11) finally, using an etching liquid prepared from hydrogen peroxide and hydrofluoric acid to assist the metal nano-particles to etch to obtain a silicon nano-pore structure;
optionally, the thickness ranges of the SOI top layer silicon adopted in the step 1) are respectively 50-500 nm.
Optionally, the SiN nano film deposition process adopted in step 2) may be chemical vapor deposition, epitaxial growth or atomic layer deposition, and the thickness intervals of the SiN nano films are 20-200 nm respectively.
Optionally, the step 3) etches the SiN nano film on one side of the substrate to form a silicon surface. The etching method can be reactive ion etching or phosphoric acid solution etching. The SiN nano-film is completely etched.
Optionally, in the step 4), the SiN nano film on one side of the substrate is etched to form a substrate release window, and the size range of the window is 550 μm × 550 μm to 750 μm × 750 μm. The etching method can be reactive ion etching or phosphoric acid solution etching. And the SiN nano film in the matrix release window is completely etched.
Optionally, the step 5) uniformly disperses the metal nanoparticles on the silicon surface. The metal nanoparticles may be one of gold, silver, platinum, or a mixture thereof. The diameter range of the metal nanoparticles is 2-200 nm.
Optionally, the step 6) deposits a protective layer over the metal nanoparticles and silicon surface. The deposition process may be physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The protective layer material can be silicon nitride, silicon oxide or a composite protective layer consisting of the silicon nitride and the silicon oxide, and the thickness of the protective layer is 50 nm-1 mu m.
Optionally, the step 7) coats a layer of adhesion promoter and glue resisting alkaline etching liquid on the protective layer. The thickness range of the coating adhesion promoter is 1-3 mu m, and the thickness range of the KOH etching resistant glue is 2-3 mu m.
Optionally, in the step 8), an alkaline solution is used to etch the silicon substrate to obtain a self-supporting nano-film composed of an SOI oxide layer, SOI top silicon, the metal nanoparticles, the protective layer, and the protective glue. The alkaline solution used may be KOH or TMAH.
Optionally, the protective glue and the SOI oxide layer are removed in the step 9). The protective glue is removed by acetone, and the SOI Oxide layer is etched by Buffered hydrofluoric acid (BOE). The time range of removing the protective glue by acetone is 5-30 min, and the time range of etching the SOI oxide layer by BOE is 5-60 s.
Optionally, in the step 10), a RIE etching method is used to etch away a portion of the protection layer above the self-supporting nano film, so as to obtain a protection layer window. The window area of the protective layer is 4 μm2～200μm2Or an array of multiple windows.
Optionally, hydrogen peroxide (H) is used in the step 11)2O2) And hydrofluoric acid (HF) is prepared into etching liquid to assist the metal nano particles to obtain the silicon nano hole array structure. Wherein H2O2The concentration range of (A) is 5-20%, the concentration range of HF is 0.05-1%, and the etching time is 5 s-2 min.
As described above, the present invention provides a silicon nanopore structure and a method of fabricating the same. The method comprises the following steps: first, a Silicon On Insulator (SOI) On an insulating substrate is provided as a substrate. And SiN nano films are deposited on the surfaces of the two sides of the matrix. The SiN on one side of the substrate is then etched using an etching technique to form a silicon surface. And etching the SiN nano film to form a matrix release window. Uniformly dispersing metal nanoparticles on the silicon surface. Subsequently, a protective layer is deposited over the metal nanoparticles and the silicon surface. And then coating a layer of tackifier and glue of alkali-resistant etching liquid on the protective layer. And then, etching the silicon substrate by using alkaline solution to obtain the self-supporting nano film consisting of the SOI oxide layer, the SOI top layer silicon, the metal nano particles, the protective layer and the protective glue. And after removing the protective glue, the tackifier and the SOI oxide layer, removing part of the protective layer above the self-supporting nano film by using an etching method again to obtain a protective layer window. And finally, preparing etching liquid by using hydrogen peroxide and hydrofluoric acid, and assisting the metal nano particles to etch to obtain the silicon nano hole structure.
The invention has the following beneficial effects:
1. and the manufacturing cost is reduced due to the compatibility with the CMOS technology. The method solves the difficulties of high cost and low efficiency in the manufacturing of the solid-state nanopore array by the predecessor, and is beneficial to the large-scale integrated manufacturing and application of the solid-state nanopore sensor.
2. The silicon nano-pore size is controllable. The nanopore length is controlled by the SOI top layer silicon thickness. Meanwhile, the nanopore diameter is controlled by the metal nanoparticle size. Compared with a nanopore size control method in the traditional manufacturing technology, the method for indirectly controlling the size of the silicon nanopore based on the metal nanoparticles and the SOI top layer silicon is simpler and more efficient.
Drawings
Fig. 1 shows a process flow diagram of the silicon nanopore structure and the method for making the same of the present invention.
FIG. 2 is a schematic view of a silicon substrate required for the present invention.
Fig. 3 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same in step 2) of the present invention.
Fig. 4 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same in step 3) of the present invention.
Fig. 5 shows a schematic structural diagram of the silicon nanopore structure and the manufacturing method thereof in step 4) of the present invention.
Fig. 6 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same of the present invention, step 5).
Fig. 7 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same of the present invention, step 6).
Fig. 8 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same in step 7) of the present invention.
Fig. 9 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same in step 8) of the present invention.
Fig. 10 to 11 show the silicon nanopore structure and the structure thereof in step 9) of the method of manufacturing the silicon nanopore structure of the present invention.
Fig. 12 shows a schematic structural view of the silicon nanopore structure and the method for making the same in step 10) of the present invention.
Fig. 13 shows a schematic structural diagram of the silicon nanopore structure and the method for manufacturing the same of the present invention, step 11).
Description of the element reference numerals
S1-S11
1 base body
10 SOI top layer silicon
100 silicon nanopores
11 SiO2
110 SiO2Window opening
12 silicon substrate
120 etching groove
2 SiN film
20 SiN film-1
21 SiN film-2
210 silicon substrate release window
3 Metal nanoparticles
4 protective layer
40 protective layer window
5 protective glue
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a silicon nanopore structure and a method for fabricating the same, the method at least comprising the following steps:
s1, providing an SOI as the substrate;
s2, depositing SiN nano films on the surfaces of the two sides of the substrate;
s3, etching the SiN nano film on one side of the substrate to form a silicon surface;
s4, etching the SiN nano film on one side of the substrate to form a substrate release window;
s5, uniformly dispersing the metal nanoparticles on the silicon surface;
s6, depositing a protective layer on the metal nano particles and the silicon surface;
s7, coating a layer of tackifier and glue for resisting alkaline etching liquid on the protective layer;
s8, etching the silicon substrate by using an alkaline solution to obtain a self-supporting nano film;
s9, removing the protective glue and the SOI oxide layer;
s10, etching a protective layer window;
s11, preparing an etching liquid by using hydrogen peroxide and hydrofluoric acid, and assisting metal nano particles to etch to obtain a silicon nano pore structure;
the silicon nanopore structure and the manufacturing method thereof of the present invention will be described in detail below with reference to the accompanying drawings.
First, step S1 is executed to provide an SOI substrate, as shown in fig. 2. Wherein the thickness interval of the SOI substrate top layer silicon 10 is 50-500 nm respectively. In this embodiment, the thickness of the SOI substrate top layer silicon 10 is selected to be 100 nm.
Then, step S2 is performed to deposit 20-200 nm SiN films (SiN film-1, SiN film-2) on the two side surfaces of the substrate 1. The SiN nano film deposition process can be chemical vapor deposition, epitaxial growth or atomic layer deposition. In this embodiment, a chemical vapor deposition SiN film is used, and the thickness of the deposited SiN film is 80 nm. Other deposition methods and SiN film thicknesses within the desired range may also be selected, as shown in FIG. 3.
Next, step S3 is performed, wherein the SiN film-1 is etched to form a silicon surface, and the SiN film-1 is completely etched. The etching method can be reactive ion etching or phosphoric acid solution etching. In this example, a reactive ion etching method is used for etching.
Then, step S4 is executed to coat a photoresist on the surface of the SiN film-2, then the photoresist is patterned by photolithography to form an opening, and the SiN film-2 below the opening is etched to form a silicon substrate release window 210, wherein the size range of the silicon substrate release window 210 is 550 μm × 550 μm to 750 μm × 750 μm. The thickness may be 550. mu. m.times.550. mu.m, 600. mu. m.times.600. mu.m, or 750. mu. m.times.750. mu.m. The etching method can be reactive ion etching or phosphoric acid solution etching. In this embodiment, as shown in fig. 5, the dimensions of the release window 21 of the etched silicon-releasing substrate are 600 μm × 600 μm by using a reactive ion etching method.
Next, step S5 is performed to uniformly disperse metal nanoparticles on the silicon surface. The metal nanoparticles may be one of gold, silver, platinum, or a mixture thereof. The diameter range of the metal nanoparticles is 2-200 nm. In this embodiment, as shown in fig. 6, the metal nanoparticles 3 are silver nanoparticles, and the diameter thereof is 50nm, but other diameters within a required range may be selected.
Next, step S6 is performed, as shown in fig. 7, a SiN nano-film is deposited on the metal nanoparticles 3 and the SOI top layer silicon 10, so as to obtain the protection layer 4. The deposition process may be physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the protective layer 4 can be silicon nitride, silicon oxide or a composite protective layer consisting of the silicon nitride and the silicon oxide, and the thickness of the protective layer 4 is 50 nm-1 μm. In this embodiment, the protective layer 4 is deposited by chemical vapor deposition, and the protective layer 4 is 500nmSiN, or other dimensions within the required range may be selected.
Next, step S7 is performed to coat the alkali-resistant etching liquid glue 5 on the protective layer 4, wherein it is required to coat the adhesion promoter before coating the alkali-resistant etching liquid glue. The thickness range of the tackifier is 1-3 mu m, and the thickness range of the alkali-resistant etching liquid glue 5 is 2-3 mu m. The thickness of the adhesion promoter selected in this example is 1.7 μm, and the thickness of the alkali-resistant etching liquid glue 5 is 2.4 μm, as shown in fig. 8.
Next, step S8 is executed, the whole structure is placed in an alkaline solution, the silicon substrate release window 210 formed by etching in step S4 is used for releasing, the silicon substrate 12 is removed, and the etching groove 120, the top layer silicon 10 and the SiO layer are obtained211 and the metal nanoparticles. Specifically, as shown in fig. 9, in the present embodiment, the alkaline solution for removing half of the silicon substrate 12 is a TMAH solution with a concentration of 25%. The silicon substrate 12 may optionally be removed using KOH.
Next, step S9 is performed to remove the protective glue and the SOI oxide layer. Specifically, the alkali-resistant etching solution 5 is removed by using acetone, and the SiO is etched by using Buffered hydrofluoric acid (BOE)211. The time range of removing the alkali-resistant etching liquid glue 5 by acetone is 5-30 min, and BOE etches the SiO2The time range of 11 is 5-60 s. In the example, the time for removing the photoresist by adopting acetone is 25min, and BOE etches the SiO2The time of 11 was 30 seconds, as shown in FIGS. 10 to 11.
Next, step S10 is performed, etching using RIE, resulting in the protective layer window 40. Coating photoresist on the protective layer 4, patterning the photoresist to form an opening by photolithography, and etching the photoresist below the opening by Reactive Ion Etching (RIE)And a protective layer 4 forming a protective layer window 40. The window area of the protective layer is 4 μm2～200μm2Or an array of multiple windows. In this example, the number of windows of the protective layer is only 1, and the area thereof is 78.5 μm2As shown in fig. 12.
And finally, executing step S11, and using an etching liquid prepared from hydrogen peroxide and hydrofluoric acid to assist the metal nano-particles 3 in etching to obtain the silicon nano-holes 100. Wherein H2O2The concentration range of (A) is 5-20%, the concentration range of HF is 0.05-1%, and the etching time is 5 s-2 min. In this example, H2O2Was 9%, the concentration of HF ranged from 0.06%, and the etching time was 80s, as shown in fig. 13.
In summary, the silicon nanopore structure and the manufacturing method thereof provided by the invention solve the problems of high cost and low efficiency in the prior solid state nanopore array manufacturing. The silicon nanopore structure provided by the invention has controllable size, and is beneficial to large-scale integrated manufacturing and application of the solid-state nanopore sensor. In addition, the invention has simple process, low manufacturing cost and complete compatibility with the CMOS process, so that the invention has better expansibility and wider application range. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for manufacturing a silicon nanopore structure is characterized by comprising the following steps:
1) providing a Silicon-On-Insulator (SOI) wafer On an insulating substrate as a substrate;
2) a layer of SiN nano film is deposited on the surfaces of the two sides of the substrate;
3) etching the SiN nano film on one side of the substrate to form a silicon surface;
4) etching the SiN nano film on one side of the substrate to form a substrate release window;
5) uniformly dispersing metal nanoparticles on the silicon surface, wherein the metal nanoparticles are one or a mixture of gold, silver and platinum, and the diameter range of the metal nanoparticles is 2-200 nm;
6) depositing a protective layer above the metal nanoparticles and the silicon surface, wherein the deposition mode is one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, the protective layer is one of silicon nitride and silicon oxide or a combination of the silicon nitride and the silicon oxide, and the thickness of the protective layer is 50 nm-1 μm;
7) a layer of tackifier is coated on the protective layer, and alkali-resistant glue is coated on the tackifier, wherein the alkali-resistant glue is glue for resisting alkaline etching liquid;
8) etching the substrate by alkaline solution to obtain a self-supporting nano film consisting of an SOI oxide layer, SOI top silicon, the metal nano particles, the protective layer and the alkali-resistant glue;
9) removing the alkali-resistant adhesive and the SOI oxide layer;
10) etching off part of the protective layer above the self-supporting nano film by using an etching method again;
11) and (3) preparing an etching liquid by using hydrogen peroxide and hydrofluoric acid, and assisting the metal nano particles to etch to obtain the silicon nano hole structure.
2. The method of claim 1, wherein: in the step 1), the thickness range of SOI top layer silicon is 50-500 nm.
3. The method of claim 1, wherein: the SiN nano film deposition process adopted in the step 2) is chemical vapor deposition, epitaxial growth or atomic layer deposition, and the thickness interval of the SiN nano film is 20-200 nm.
4. The method of claim 1, wherein: and 3) etching the SiN nano film on one side of the substrate to form a silicon surface, wherein the etching mode is reactive ion etching or phosphoric acid solution etching, and the SiN nano film is completely etched.
5. The method of claim 1, wherein: and 4) etching the SiN nano film on one side of the substrate in the step 4) to form a substrate release window, wherein the size of the window of the substrate release window is 550 micrometers multiplied by 550 micrometers to 750 micrometers multiplied by 750 micrometers, the etching mode is reactive ion etching or phosphoric acid solution etching, and the SiN nano film in the substrate release window is completely etched.
6. The method of claim 1, wherein: and 7) coating a layer of tackifier and alkali-resistant adhesive on the protective layer, wherein the thickness range of the tackifier is 1-3 mu m, and the thickness range of the alkali-resistant adhesive is 2-3 mu m.
7. The method of claim 1, wherein: and 8) etching the substrate by using an alkaline solution to obtain the self-supporting nano film consisting of the SOI oxide layer, the SOI top silicon, the metal nanoparticles, the protective layer and the alkali-resistant glue, wherein the alkaline solution is KOH or TMAH.
8. The method of claim 1, wherein: removing the alkali-resistant glue and the SOI oxide layer in the step 9), respectively removing the alkali-resistant glue by using acetone, etching the SOI oxide layer by using Buffered hydrofluoric acid (BOE), wherein the time for removing the alkali-resistant glue by using the acetone is 5-30 min, and the time for etching the SOI oxide layer by using the BOE is 5-60 s.
9. The method of claim 1, wherein: etching off part of the protective layer above the self-supporting nano film by using a RIE (reactive ion etching) method in the step 10) to obtain a protective layer window, wherein the window area of the protective layer window is 4 mu m2～200μm2。
10. The method of claim 1, wherein: hydrogen peroxide (H) is used in the step 11)2O2) Hydrofluoric acid (HF) to assist the metal nanoparticles in obtaining the silicon nanopore array structure, wherein H2O2The concentration range of (A) is 5-20%, the concentration range of HF is 0.05-1%, and the etching time is 5 s-2 min.
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