CN103208413A - Production method of controllable silicon nanowire array - Google Patents
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- CN103208413A CN103208413A CN2012100082021A CN201210008202A CN103208413A CN 103208413 A CN103208413 A CN 103208413A CN 2012100082021 A CN2012100082021 A CN 2012100082021A CN 201210008202 A CN201210008202 A CN 201210008202A CN 103208413 A CN103208413 A CN 103208413A
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Abstract
The invention provides a production method of a controllable silicon nanowire array. The production method of the controllable silicon nanowire array includes that two silicon substrates with the same crystal orientation are utilized to perform small-angle bonding to form screw dislocation in square grid distribution; stress preferential etching is utilized to perform etching on a vertical corresponding area which is affected by a screw dislocation line in the grid distribution due to uneven silicon surface stress distribution caused by the dislocation to form a graphical silicon island in a square grid shape; and silver catalyst chemical corrosion is utilized to produce the nanowire array on a graphical substrate. The controllable silicon nanowire array which is produced through the production method has the advantages of being high in controllability and reliability and capable of achieving high precision due to the fact that the distribution of the controllable silicon nanowire array is controlled through silicon small-angle bonding. The production method of the controllable silicon nanowire array has the advantages of being simple in process, remarkable in effect, compatible with general semiconductor processes and suitable for industrial production.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of preparation method of controllable silicon nano-wire array.
Background technology
Semiconductor nano material is all demonstrating wide application prospect aspect electronics and the optics.In recent years, be accompanied by people to continuous exploration and the research of field of nanometer technology, have the material of one-dimensional nano structure, as silicon nanowires, attracted increasing people's eyeball.Silicon is most important material in the current semi-conductor industry, and silicon nanowires also has the characteristics such as specific area of significant quantum effect, super large because of it, in fields such as MOS device, transducers good prospects for application is arranged.How with a kind of simple, controlled, mode is prepared high-quality silicon nanowires cheaply, becomes an important topic.
The preparation method of silicon nanowires mainly can be divided into bottom-up (bottom-up) and top-down (top-down) two big classes.Bottom-up method mainly is to rely on nanometer technology, utilizes the catalyst grow nanowire.Though this method can disposablely produce silicon nanowires in enormous quantities, but be difficult to realize the located growth of nano wire, and be essentially different with traditional top-down CMOS integrated circuit processing technology mode, compatibility may become a stumbling-block that hinders its application.And along with the continuous progress of semiconductor process techniques level, the top-down method that relies on technology such as film preparation, photoetching and etching to prepare silicon nanowires gets more and more.
The needs of general top-down technology position preparation to the position of silicon nanowires earlier, carry out the preparation of silicon nanowires by photoetching and etching then.General positioning accuracy is lower or cost is higher in the prior art, and also there are certain difficulty in the etching depth of silicon chip and the control of nano wire size.Therefore, preparation precision height in the existing technology, the silicon nanowires of satisfactory size is complex process often, and production cost is too high.
Summary of the invention
The shortcoming of prior art in view of the above the object of the present invention is to provide a kind of preparation method of controllable silicon nano-wire array, so that the preparation method of the silicon nanowire array that a kind of technology is simple, controllability is good and reliability is high to be provided.
Reach other relevant purposes for achieving the above object, the invention provides a kind of preparation method of controllable silicon nano-wire array, described preparation method may further comprise the steps at least: 1) provide the SOI substrate to reach the silicon substrate that has identical crystal orientation with the top silicon layer of described SOI substrate, bonding described top silicon layer and silicon substrate, wherein, the crystal orientation of described top silicon layer and the crystal orientation of described silicon substrate are default angle, to form the dislocation line of the screw dislocation with distributed in grid at bonded interface; 2) remove at the bottom of the backing of described SOI substrate and insulating barrier exposing the back of the body surface of described top silicon layer, the back of the body surface of the described top of etching silicon layer forms a plurality of groove structures with the zone in the vertical correspondence of described dislocation line influence; 3) respectively form silver nano-grain in this groove structure described, adopt silver-colored catalytic chemistry etch described top silicon layer and silicon substrate to be corroded to form the preparation of silicon nanowire array then.
In the preparation method of controllable silicon nano-wire array of the present invention, the thickness of described top silicon layer is 5nm～100nm.
In the preparation method of controllable silicon nano-wire array of the present invention, the angle m of described default angle is 0 °＜m≤5 °.
In the preparation method of controllable silicon nano-wire array of the present invention, the dislocation line that described dislocation line distributes for the square net shape, wherein, the spacing of two parallel and adjacent dislocation lines is 10nm～200nm.
Preferably, described step 2) adopts the preferential etching method of stress that etching is carried out on the back of the body surface of described top silicon layer in, comprise and adopt HF and CrO
3Mixed solution carries out first step etching and adopts HF, CH
3COOH and HNO
3Mixed solution carries out the step of the second step etching.
In the preparation method of controllable silicon nano-wire array of the present invention, adopt electron beam evaporation technique to form described silver nano-grain in the described step 3).
In the preparation method of controllable silicon nano-wire array of the present invention, the diameter of described silver nano-grain is 1nm～20nm.
In the preparation method of controllable silicon nano-wire array of the present invention, adopt HF and Fe (NO) in the described step 3)
3Mixed solution carries out silver-colored catalytic chemistry corrosion to described top silicon layer.
In the preparation method of controllable silicon nano-wire array of the present invention, described step 2) adopt lithographic technique at the bottom of the backing to remove at the bottom of the backing of described SOI and insulating barrier in.
In the preparation method of controllable silicon nano-wire array of the present invention, adopt in the described step 1) that hydrophobic bond is legal to carry out bonding to described top silicon layer and described silicon substrate.
As mentioned above, the preparation method of controllable silicon nano-wire array of the present invention, has following beneficial effect: adopt two identical silicon substrates of crystal orientation to carry out the low-angle bonding and form the screw dislocation that the square net shape distributes, because dislocation causes silicon face stress distribution inequality, just can utilize the preferential etching of stress then, etching is carried out in zone to the vertical correspondence of dislocation line influence, form the graphical silicon island of square net shape, adopt silver-colored catalytic chemistry corrosion to prepare nano-wire array in this patterned substrate at last.Adopt the silicon nanowire array of the present invention's preparation to have very high controllability and reliability, the distribution of nano-wire array is controlled by silicon silicon low-angle bonding, can reach higher precision.Preparation method's technology of the present invention is simple, and effect is remarkable, and is compatible with general semiconductor technology, is applicable to industrial production.
Description of drawings
Fig. 1～Fig. 2 is shown as the structural representation that preparation method's step 1) of controllable silicon nano-wire array of the present invention presents.
Fig. 3～Fig. 4 is shown as preparation method's step 2 of controllable silicon nano-wire array of the present invention) structural representation that presents.
Fig. 5～Fig. 6 is shown as the structural representation that preparation method's step 3) of controllable silicon nano-wire array of the present invention presents.
Fig. 7 is shown as the schematic perspective view of the prepared silicon nanowire array of preparation method that adopts controllable silicon nano-wire array of the present invention.
Fig. 8 is shown as the floor map of the prepared silicon nanowire array of preparation method that adopts controllable silicon nano-wire array of the present invention.
The element numbers explanation
101～103 SOI substrates
104 silicon substrates
105 dislocation lines
106 groove structures
107 silver nano-grains
108 silicon nanowire arrays
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 to Fig. 8.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
Shown in Fig. 1～8, the invention provides a kind of preparation method of controllable silicon nano-wire array, it is characterized in that described preparation method may further comprise the steps at least:
See also Fig. 1～2, as shown in the figure, at first carry out step 1), provide SOI substrate 101～103 to reach the silicon substrate that has identical crystal orientation with the top silicon layer 103 of described SOI substrate 101～103, the described top of bonding silicon layer 103 and silicon substrate, wherein, the crystal orientation of described top silicon layer 103 and the crystal orientation of described silicon substrate are default angle, to form the dislocation line 105 with latticed screw dislocation at bonded interface.Need to prove, described SOI substrate 101～103 has at the bottom of the backing 101, be incorporated at the bottom of the described backing insulating barrier 102 on 101 and be incorporated into top silicon layer 103 on the described insulating barrier 102, the thickness of the top silicon layer 103 of described SOI substrate 101～103 is 5nm～100nm.
Particularly, top silicon layer 103 and described silicon substrate 104 to described SOI substrate 101～103 carry out hydrophobic treatment, at first adopt RCA wet chemistry ablution that top silicon layer 103 and the described silicon substrate 104 of described SOI substrate 101～103 are cleaned, adopt HF solution to clean then, make its surface have hydrophobic property, make the crystal orientation of described top silicon layer 103 and the crystal orientation of described silicon substrate 104 be default angle then, crystal orientation and described silicon substrate 104 to described top silicon layer 103 carry out bonding, has the screw dislocation of latticed dislocation line 105 to form at bonded interface, wherein, the angle m of described default angle is 0 °＜m≤5 °, m is 1 ° in the present embodiment, described latticed dislocation line 105 is square net shape dislocation line 105, wherein, the spacing of two parallel and adjacent dislocation lines 105 is 10nm～200nm, and its concrete numerical value is determined by the angle of described default angle, in the present embodiment, dislocation line 105 spacings that produce of 1 ° default angle are 22nm.Because screw dislocation can produce corresponding stress distribution in the described top silicon layer 103.
See also Fig. 3～Fig. 4, if shown in, carry out step 2 then), remove at the bottom of the backing of described SOI substrate 101～103 101 and insulating barrier 102 to expose the back of the body surface of described top silicon layer 103, the back of the body surface of corroding described top silicon layer 103 forms a plurality of groove structures 106 with the zone in the vertical correspondence of described latticed dislocation line 105 influences.
Particularly, adopt 101 lithographic techniques at the bottom of the backing remove at the bottom of the backing of described SOI 101 with insulating barrier 102, certainly, in other embodiments, also can adopt the method for smart peeling technology and polishing to remove at the bottom of the backing of described SOI 101 and insulating barrier 102.Because screw dislocation, can produce corresponding stress distribution in the described top silicon layer 103, easier being corroded in the zone of silicon layer 103 under the effect of tensile stress, described top selected for use and adopted the preferential etching method of stress that etching is carried out on the back of the body surface of described top silicon layer 103, comprises and adopts HF and CrO
3Mixed solution carries out first step etching and adopts HF, CH
3COOH and HNO
3Mixed solution carries out the step of the second step etching, in the present embodiment, adopts HF: CrO
3Ratio be to carry out preliminary etching at 3: 1000, adopt HF: CH
3COOH: HNO
3Ratio be to proceed etching to obtain described groove structure 106 at 0.02: 7: 3.
See also Fig. 5～Fig. 8, as shown in the figure, carry out step 3) at last, in described respectively this groove structure 106, form silver nano-grain 107, adopt silver-colored catalytic chemistry etch described top silicon layer 103 to be corroded to form the preparation of silicon nanowire array 108 then.
Particularly, adopt electron beam evaporation technique to form described silver nano-grain 107, because the 106 process corrosion treatments of described groove structure, described silver nano-grain 107 is preferentially reunited in described groove structure 106 depositions, wherein, the diameter of described silver nano-grain 107 is 1nm～20nm.Need to prove that because respectively the tensile stress of the intersecting area of this groove structure 106 is bigger relatively, etch rate is relatively large, therefore other groove structure 106 zones can be etched deeplyer relatively.Can be limited in silver nano-grain 107 in the intersection area of described respectively this groove structure 106 by the sedimentation time of controlling silver.At last, adopt HF and Fe (NO)
3Mixed solution carries out silver-colored catalytic chemistry corrosion to described top silicon layer 103, because the catalytic action of silver, the corrosion mixed solution preferentially is corroded in the place that silver nano-grain 107 contacts with silicon, therefore, zone corresponding below silver nano-grain 107 preferentially is corroded, silicon between the silver nano-grain 107 is retained and finally forms silicon nanowire array 108, as Fig. 7～shown in Figure 8.Certainly, in other embodiments, can adopt different metal nanoparticles to carry out catalyzed corrosion, not enumerate one by one herein.
In sum, the preparation method of controllable silicon nano-wire array of the present invention, adopt two identical silicon substrates of crystal orientation to carry out the low-angle bonding and form the screw dislocation that the square net shape distributes, because dislocation causes silicon face stress distribution inequality, utilize the preferential etching of stress then, etching is carried out in zone to the vertical correspondence of dislocation line influence, and the graphical silicon island that forms the square net shape adopts silver-colored catalytic chemistry corrosion to prepare nano-wire array in this patterned substrate at last.Adopt the silicon nanowire array of the present invention's preparation to have very high controllability and reliability, the distribution of nano-wire array is controlled by silicon silicon low-angle bonding, can reach higher precision.Preparation method's technology of the present invention is simple, and effect is remarkable, and is compatible with general semiconductor technology, is applicable to industrial production.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (10)
1. the preparation method of a controllable silicon nano-wire array is characterized in that, described preparation method may further comprise the steps at least:
1) provide the SOI substrate to reach the silicon substrate that has identical crystal orientation with the top silicon layer of described SOI substrate, bonding described top silicon layer and silicon substrate, wherein, the crystal orientation of described top silicon layer and the crystal orientation of described silicon substrate are default angle, to form the dislocation line of the screw dislocation with distributed in grid at bonded interface;
2) remove at the bottom of the backing of described SOI substrate and insulating barrier exposing the back of the body surface of described top silicon layer, the back of the body surface of the described top of etching silicon layer is to form groove structure in the zone of the vertical correspondence of this dislocation line influence respectively;
3) respectively form silver nano-grain in this groove structure described, adopt silver-colored catalytic chemistry etch described top silicon layer and silicon substrate to be corroded to form the preparation of silicon nanowire array then.
2. the preparation method of controllable silicon nano-wire array according to claim 1, it is characterized in that: the thickness of described top silicon layer is 5nm～100nm.
3. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: the angle m of described default angle is 0 °＜m≤5 °.
4. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: described dislocation line is the dislocation line that the square net shape distributes, and wherein, the spacing of two parallel and adjacent dislocation lines is 10nm～200nm.
5. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: adopt the preferential etching method of stress that etching is carried out on the back of the body surface of described top silicon layer described step 2), comprise and adopt HF and CrO
3Mixed solution carries out first step etching and adopts HF, CH
3COOH and HNO
3Mixed solution carries out the step of the second step etching.
6. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: adopt electron beam evaporation technique to form described silver nano-grain in the described step 3).
7. the preparation method of controllable silicon nano-wire array according to claim 1, it is characterized in that: the diameter of described silver nano-grain is 1nm～20nm.
8. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: adopt HF and Fe (NO) in the described step 3)
3Mixed solution carries out silver-colored catalytic chemistry corrosion to described top silicon layer.
9. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: adopt lithographic technique at the bottom of the backing to remove at the bottom of the backing of described SOI and insulating barrier described step 2).
10. the preparation method of controllable silicon nano-wire array according to claim 1 is characterized in that: adopt in the described step 1) that hydrophobic bond is legal to carry out bonding to described top silicon layer and described silicon substrate.
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Cited By (3)
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| CN105097439A (en) * | 2014-05-23 | 2015-11-25 | 中国科学院上海微系统与信息技术研究所 | Method for controlling accurate positioning and growth of silicon nanowires through micron copper patterns |
| CN107416762A (en) * | 2017-05-16 | 2017-12-01 | 广东工业大学 | A kind of silicon nano hole structure and preparation method thereof |
| CN112736173A (en) * | 2021-04-06 | 2021-04-30 | 至芯半导体(杭州)有限公司 | Composite substrate, preparation method and semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097439A (en) * | 2014-05-23 | 2015-11-25 | 中国科学院上海微系统与信息技术研究所 | Method for controlling accurate positioning and growth of silicon nanowires through micron copper patterns |
| CN107416762A (en) * | 2017-05-16 | 2017-12-01 | 广东工业大学 | A kind of silicon nano hole structure and preparation method thereof |
| CN107416762B (en) * | 2017-05-16 | 2020-03-24 | 广东工业大学 | Silicon nano-pore structure and manufacturing method thereof |
| CN112736173A (en) * | 2021-04-06 | 2021-04-30 | 至芯半导体(杭州)有限公司 | Composite substrate, preparation method and semiconductor device |
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