CN102751232B - Method for preparing SiGe or Ge nanowire by using germanium concentration technology - Google Patents

Method for preparing SiGe or Ge nanowire by using germanium concentration technology Download PDF

Info

Publication number
CN102751232B
CN102751232B CN201210225391.8A CN201210225391A CN102751232B CN 102751232 B CN102751232 B CN 102751232B CN 201210225391 A CN201210225391 A CN 201210225391A CN 102751232 B CN102751232 B CN 102751232B
Authority
CN
China
Prior art keywords
sige
ge
nano wire
layer
deg
Prior art date
Application number
CN201210225391.8A
Other languages
Chinese (zh)
Other versions
CN102751232A (en
Inventor
狄增峰
叶林
赵清太
张苗
Original Assignee
中国科学院上海微系统与信息技术研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院上海微系统与信息技术研究所 filed Critical 中国科学院上海微系统与信息技术研究所
Priority to CN201210225391.8A priority Critical patent/CN102751232B/en
Publication of CN102751232A publication Critical patent/CN102751232A/en
Application granted granted Critical
Publication of CN102751232B publication Critical patent/CN102751232B/en

Links

Abstract

The invention provides a method for preparing a SiGe or Ge nanowire by using a germanium concentration technology. The method comprises the step of obtaining the controlled growth of the SiGe or Ge nanowire ensuring the yield and quality by combining a patterning method and a germanium concentration method. According to the method, a uniform and straight SiGe or Ge nanowire array can be obtained, the SiGe or Ge nanowire with different components can be obtained through the control on oxidation time, and the length of the nanowire formed in the end can reach hundreds of micrometers, the diameter of the nanowire can reach dozens of nanometers, and the patterning design lays a foundation for a nanowire device.

Description

Utilize germanium concentration technique to prepare the method for SiGe or Ge nano wire

Technical field

The present invention relates to a kind of preparation method of nano wire, particularly relate to a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire.

Background technology

For the synthetic of nano structural material with characterize and become one of nearly ten years main survey regions, characteristics such as one dimension semiconductor nano wire is due to quantum limitation effect, the sensitive and low current leakage in surface and have good application prospect at aspects such as electronic device, transducer, connection wires.

Germanium is one of important semi-conducting material, its Bohr radius is 24.3nm, much larger than the Bohr radius of general semi-conducting material, so the novel electro-optical properties such as quantum effect more easily appear in Ge nanoline, aspect the nano-devices such as nano field-effect transistor, there is good application prospect.In addition, the III-V such as germanium and GaAs etc. have close lattice constant, and germanium more easily mates with III-V family material, thus Ge nanoline at novel nano device, nanometer connects the fields such as wire important potential using value.The electron transport of Ge nanoline and array, luminous light (PL), the photoconduction of causing, Ge nanoline field-effect transistor (FET) etc. has also obtained broad research.Ge nanoline becomes one of study hotspot in recent years, and has obtained greater advance preparing in a large number aspect the technology of preparing of Ge nanoline and growth mechanism, can prepare the Ge nanoline that diameter is less than 10nm at present, and length can reach hundreds of micron, even grade.People, in preparing Ge nanoline in a large number, have also proposed corresponding growth mechanism, and as metal catalytic VLS mechanism and Fabricated by Oxide-assisted Growth Mechanism mechanism, this is all for extensive preparation and the application of Ge nanoline provide basis well.

Silicon germanium material aspect microelectronics and optoelectronic device applications also one be subject to extensive concern, can be used for photoelectron detector too, field effect transistor, the aspects such as sun energy battery, and SiGe nano wire is similar to Ge nanoline, along with reducing of nano-scale, show novel electro-optical properties.Therefore, the research of SiGe the fabricate of nanowires method is also one of focus.

The method of preparing at present Ge nanoline mainly contains solution thermal synthesis, chemical vapor deposition (CVD), template, laser ablation and the solwution method of boundary over zero.Laser ablation method is as early realizing the method for preparing in a large number Ge nanoline, has that operation is simple, product yield is large and purity high, but apparatus expensive, preparation temperature is high, and product cost is higher.CVD rule reduces much on preparation temperature, but the diameter distribution of gained Ge nanoline is larger.Although and employing solvent process for thermosynthesizing preparation temperature is also lower, in product, nano particle is more, the purity of Ge nanoline is lower, although adopt template can prepare even and straight Ge nanoline array, output is lower.

Given this to overcome, in prior art, cost is high, temperature is high, purity is low, diameter distribution shortcoming large and that yield poorly becomes current problem demanding prompt solution, how to propose the preparation method of a kind of Ge or SiGe nano wire.

Summary of the invention

The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire, for solving, prior art cost is high, temperature is high, purity is low, diameter distribution is large and the problem that yields poorly.

For achieving the above object and other relevant objects, the invention provides a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire, at least comprise:

1) utilize smart-cut process to prepare SGOI structure;

2) utilize the pending SiGe nano-wire array that etches preliminary dimension on the SiGe layer of ion beam etching technique in described SGOI structure;

3) to described step 2) structure to carry out germanium concentrated, and control the concentrated process conditions of germanium to obtain surface by SiO 2new SiGe nano wire or the Ge nano-wire array of the preliminary dimension that layer wraps up;

4) utilize HF to erode respectively the respectively SiO of this SiGe nano wire or Ge nanowire surface of parcel 2layer, obtains new SiGe nano wire or Ge nano-wire array.

Alternatively, described step 1) also comprises:

1-1) provide a Si substrate, epitaxial growth one deck SiGe layer on a described Si substrate;

1-2) adopt ion implantation technology to carry out H+ Implantation from described SiGe layer surface, and control the ion implantation energy silicon layer that default degree of depth formation one deck is rich in H+ ion in a described Si substrate as peel ply;

1-3) provide the 2nd Si substrate, and prepare one deck insulating buried layer BOX on described the 2nd Si substrate;

1-4) utilize bonding technology that the stepped construction that bonding formation includes the 2nd Si substrate, insulating buried layer BOX, SiGe layer, a Si substrate is successively carried out to the insulating buried layer BOX layer surface on the 2nd Si substrate in the SiGe layer surface on the one Si substrate;

1-5) structure after para-linkage is carried out the high temperature anneal, to peel off the described Si substrate of part from described peel ply;

1-6) utilize TMAH corrosive liquid that a remaining described Si substrate is all eroded to obtain SGOI structure.

Alternatively, described step 1-1) in the thickness of epitaxially grown SiGe layer be 80nm~120nm.

Alternatively, described step 1-1) component of Ge is 12%~30% in SiGe layer.

Alternatively, described step 1-3) in the material of the insulating buried layer BOX for preparing on the 2nd Si substrate be SiO 2or Al 2o 3.

Alternatively, described step 1-5) process conditions that peel off the described Si substrate of part are: be first warmed up to 300 DEG C, be incubated after 3 hours, then be incubated half an hour after half an hour is warmed up to 600 DEG C, whole process is connected with high-purity O of 8000ccm 2.

Alternatively, described step 2) in the width of the pending SiGe nano wire that SiGe layer forms described in etching be 50nm~200nm.

Alternatively, form by SiO 2layer wrap up Ge nano-wire array time, described step 3) also comprises:

3-1) by described step 2) structure put into 600 DEG C of reacting furnaces, then pass into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2;

3-2) pass into the O of 4000ccm 2keep stopping after 30 minutes;

3-3) pass into the N of 5000ccm 2keep stopping after 30 minutes;

3-4) repeating step 3-2 successively) with step 3-3) after 2 times, at N 2under atmosphere, make reacting furnace temperature drop to 900 DEG C from 1050 DEG C in 1 hour;

3-5) pass into the O of 4000ccm 2keep stopping after 30 minutes;

3-6) pass into the N of 5000ccm 2keep stopping after 30 minutes;

3-7) repeating step 3-5 successively) with step 3-6) after 3 times, at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 900 DEG C in 1 hour, complete germanium concentrated, form and include successively the 2nd Si substrate, insulating buried layer BOX and by SiO 2the stepped construction of the described Ge nano-wire array that layer wraps up.

Alternatively, the respectively SiO of this Ge nano wire of parcel 2the thickness of layer is 190nm; Further alternatively, described Ge nano wire is cylindrical, and diameter is 30nm.

Alternatively, form by SiO 2layer wrap up new SiGe nano-wire array time, described step 3) also comprises:

3-1) by described step 2) structure puts into 600 DEG C of reacting furnaces, then passes into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2;

3-2) pass into the O of 4000ccm 2keep stopping after 30 minutes;

3-3) pass into the N of 5000ccm 2keep stopping after 30 minutes;

3-4) at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 1050 DEG C in 2 hours, complete germanium concentrated, form include successively the 2nd Si substrate, insulating buried layer BOX, by SiO 2the stepped construction of the described new SiGe nano-wire array that layer wraps up.

Alternatively, the respectively SiO of this new SiGe nano wire of parcel 2the thickness of layer is 80nm; Further alternatively, described new SiGe nano wire be shaped as cylinder, and its diameter is 70nm; In described new SiGe nano wire, the component of Ge is 40%.

As mentioned above, a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire of the present invention, has following beneficial effect:

The present invention is by combining graphical and the concentrated method of germanium, obtain a kind of SiGe of output and quality and controllable growth of Ge nano wire of ensureing, the method can obtain even and straight SiGe or Ge nano-wire array, and by can obtain SiGe and the Ge nano wire of different component to the control of oxidization time, the final nanowire length forming can reach hundreds of micron, diameter reaches tens nanometers, lays the first stone by the nano-wire devices afterwards that is designed to of figure.

Brief description of the drawings

Fig. 1 a~1f is shown as in the present invention and utilizes smart peeling technology to prepare the process chart of SGOI structure.

Fig. 2 is shown as the three-dimensional structure schematic diagram of the pending SiGe nano-wire array etching in the present invention.

Fig. 3 be shown as that germanium in the present invention forms after concentrated by SiO 2the Ge nano-wire array three-dimensional structure schematic diagram that layer wraps up.

Fig. 4 is shown as and in the present invention, erodes described SiO 2described Ge nano-wire array three-dimensional structure schematic diagram after layer.

Fig. 5 be shown as that germanium in the present invention forms after concentrated by SiO 2the new SiGe nano-wire array three-dimensional structure schematic diagram that layer wraps up.

Fig. 6 is shown as and in the present invention, erodes described SiO 2described new SiGe nano-wire array three-dimensional structure schematic diagram after layer.

Element numbers explanation

1 the one Si substrate

100 peel plies

11 SiGe layers

110 pending SiGe nano wires

111 new SiGe nano wires

112 Ge nano wires

12 SiO 2layer

20 the 2nd Si substrates

21 insulating buried layer BOX

Embodiment

Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.

Refer to Fig. 1 a to 1f and Fig. 2 to Fig. 6.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.

As shown in the figure, the invention provides a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire, at least comprise the following steps:

First, with reference to figure 1a to Fig. 1 f, utilize smart peeling technology (Smart-cut) to prepare SGOI chip architecture, comprise the following steps:

Step 1: as shown in Figure 1a, the one Si substrate 10 is provided, epitaxial growth one deck SiGe layer 11 on a described Si substrate 10, wherein the thickness of SiGe layer 11 is 80nm~120nm, in the present embodiment, the thickness of SiGe layer 11 is elected 100nm as, but be not limited to this, in other embodiments, the thickness of SiGe layer 11 can be adjusted as required.In addition, in SiGe layer 11, the content of Ge is 12%~30%, elects temporarily 30% as, but be not limited to this in the present embodiment, and in other embodiments, the content of Ge can be adjusted as required, hereby statement.

Step 2: as shown in Figure 1 b, adopt ion implantation technology to carry out H+ Implantation from described SiGe layer 11 surface, and control the ion implantation energy silicon layer that default degree of depth formation one deck is rich in H+ ion in a described Si substrate 10 as peel ply 100, H+ Implantation Energy is larger, it is darker that H+ injects peak, in general,, in the time that ion implantation energy is 50Kev~150Kev, the corresponding depth distribution of injecting Si sheet is at 500nm~1200nm.This enforcement intermediate ion Implantation Energy is 60Kev, corresponding is 700nm~800nm from the SiGe layer 11 surface injection degree of depth, because the thickness of SiGe layer 11 is 100nm, so the degree of depth in H+ Implantation the one Si substrate 10 is 600nm~700m, but be not limited to this, in other embodiments, can also select as required different ion implantation energies to reach the different injection degree of depth.

Step 3: as shown in Fig. 1 c, provide the 2nd Si substrate 20, and the insulating buried layer BOX21 that thermal oxide growth a layer thickness is 100nm~150nm on described the 2nd Si substrate 20, in the present embodiment, the thickness of insulating buried layer BOX21 is elected 120nm as.It should be noted that, in the present embodiment, insulating buried layer material is elected SiO temporarily as 2, but be not limited to this, in other embodiments, can also be Al 2o 3, statement hereby.

Step 4: as shown in Figure 1 d, SiGe layer on the one Si substrate slice 10 11 surface are carried out after strict cleaning, activation processing and polishing with the insulating buried layer BOX21 surface on the 2nd Si substrate 20, at room temperature two burnishing surfaces are fit together and make two wafer bondings together, form the stepped construction that includes successively the 2nd Si layer 20, insulating buried layer BOX21, SiGe layer 11, a Si substrate 10, wherein this insulating buried layer BOX21 is as the insulating buried layer in final formation structure.

Step 5: as shown in Fig. 1 e, the structure after para-linkage is carried out annealing in process.Generally in two steps: the first step, the high concentration of injecting in the one Si substrate at high temperature can nucleation and form bubble containing the peel ply 100 of H+ ion, sharply expanding of bubble separates silicon chip at peel ply 100 places of being rich in high concentration H+ sheath, namely peel off; Second step, high-temperature heat treatment improves the bond strength of bonded interface and eliminates the ion implantation damage in bonding structure.Concrete technology condition in the present embodiment is: be first warmed up to 300 DEG C, be incubated after 3 hours, a Si substrate 10 peeled off at peel ply 100 places, then be incubated half an hour after half an hour is warmed up to 600 DEG C, the bond strength that improves bonded interface, whole process is connected with high-purity O of 8000ccm 2.

Step 6: as shown in Figure 1 f, utilize TMAH corrosive liquid that a remaining described Si substrate 10 is all eroded to obtain SGOI structure, TMAH(Tetramethylammonium hydroxide) full name is tetramethyl aqua ammonia, a kind of anisotropic etchant with good corrosive nature, selectivity is good, nontoxic and free from environmental pollution, the most important thing is that TMAH and CMOS technique are compatible mutually, meet the development trend of SOC, TMAH substitutes KOH and other corrosive liquids just gradually, and normally used in technique is 10% and 25% the aqueous solution.Therefore in the present invention, adopt TMAH corrosive liquid to control better its corrosion to a Si substrate 10, obtain high-quality SGOI structure.

Secondly, adopt the mask plate of default figure, utilize on the SiGe layer 11 of ion beam etching technique in described SGOI structure and carry out etching, to form width as 50nm~200nm, length is pending SiGe nano wire 110 arrays of 1 μ m~100 μ m, in the present embodiment, the width of two kinds of pending SiGe nano wires 110 that described etching forms is respectively 175nm and 125nm, length is 1 μ m, in other embodiments, also the pending SiGe nano wire 110 that can be other width and length, for example width is 150nm, length is 2 μ m etc.Therefore the structure, forming in this step is for comprising according to this 2nd Si layer 20, insulating buried layer BOX21 and pending SiGe nano wire 110 arrays.As Fig. 2 is shown as the three-dimensional structure schematic diagram of the pending SiGe nano-wire array etching in this step.

Again, as shown in Figure 3, the described structure that comprises according to this 2nd Si layer 20, insulating buried layer BOX21, pending SiGe nano wire 110 arrays is carried out to germanium and concentrate, and control the concentrated process conditions of germanium to obtain surface by SiO 2layer 12 preliminary dimension of wrapping up new SiGe nano wire 111 arrays or Ge nano wire 112 arrays, also obtain size and component controlled nano-wire array.Concrete technology comprises two kinds of situations:

When forming by SiO 2layer 12 wrap up Ge nano wire 112 array time, the width that the present embodiment is chosen described pending SiGe nano wire 110 is 175nm, technique is as follows:

1) the described structure that comprises according to this 2nd Si layer 20, insulating buried layer BOX21, pending SiGe nano wire 110 arrays is put into 600 DEG C of reacting furnaces, then pass into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2.

2) pass into the O of 4000ccm 2keep stopping after 30 minutes.

3) pass into the N of 5000ccm 2keep stopping after 30 minutes.

4) repeating step 2 successively) with step 3) 2 times after, at N 2under atmosphere, make reacting furnace temperature drop to 900 DEG C from 1050 DEG C in 1 hour.

5) pass into the O of 4000ccm 2keep stopping after 30 minutes.

6) pass into the N of 5000ccm 2keep stopping after 30 minutes.

7) repeating step 5 successively) with step 6) 3 times after, at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 900 DEG C in 1 hour, complete germanium concentrated, form and include successively the 2nd Si substrate 20, insulating buried layer BOX21 and by SiO 2the stepped construction of layer 12 Ge nano wire 112 array wrapping up.Be illustrated in figure 3 that germanium in this step forms after concentrated by SiO 2the Ge nano-wire array three-dimensional structure schematic diagram that layer wraps up.

In the concentrated technique of above-mentioned germanium, carry out thermal oxidative reaction at 1050 DEG C and 900 DEG C respectively, this is owing to carrying out after thermal oxidative reaction at 1050 DEG C, Ge component in described pending SiGe nano wire 110 raises, cause the melting point depression of SiGe, therefore after a period of time, need be in the i.e. further thermal oxidation at 900 DEG C of lower temperature, to improve the purity of the concentrated rear Ge nano wire 112 of germanium, finally on described insulating buried layer BOX21 surface, form pure Ge nano wire 112 arrays and the respectively SiO of this pure Ge nano wire 112 of parcel 2layer 12.In the present embodiment, the Ge nano wire that obtains 112 is for cylindrical, and diameter is 30nm, the respectively SiO of this Ge nano wire 112 of parcel 2the thickness of layer 12 is 190nm.

In the present embodiment, the size of the concentrated concrete process conditions of above-mentioned germanium and the Ge nano wire 112 that forms only in SiGe layer 11 component of Ge be 30%, and the thickness of SiGe layer 11 is suitable for while being 100nm.But be not limited to this, in other embodiments, along with the change of size and the component of Ge in described SiGe layer 11 of the thickness of described SiGe layer 11, described pending SiGe nano wire 110, the size of the described Ge nano wire 112 of above-mentioned process conditions and formation also changes thereupon, and these process conditions are controlled.The quality of the Ge nano wire 112 that therefore, prepared by the method is controlled.

It should be noted that, in above-mentioned germanium concentration technology, pass into N 2effect have two, the one, as protective atmosphere, another act as and makes that in concentrated SiGe layer later or Ge layer, component is even everywhere, this is because the region near surperficial can preferential and O 2reaction, the relative lower floor of content of Ge is higher, thereby in SiGe layer, forms a gradient, is unfavorable for being finally condensed into Ge.

As shown in Figure 5, in the time forming new SiGe nano wire 111 array, the width that the present embodiment is chosen pending SiGe nano wire 110 is 125nm, and technique is as follows:

1) the described structure that comprises according to this 2nd Si layer 20, insulating buried layer BOX21, pending SiGe nano wire 110 arrays is put into 600 DEG C of reacting furnaces, then pass into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2.

2) pass into the O of 4000ccm 2keep stopping after 30 minutes.

3) pass into the N of 5000ccm 2keep stopping after 30 minutes.

4) at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 1050 DEG C in 2 hours, complete germanium concentrated, form include successively the 2nd Si substrate 20, insulating buried layer BOX21, by SiO 2the stepped construction of layer 12 new SiGe nano wire 111 array wrapping up.Be illustrated in figure 5 that germanium in the present invention forms after concentrated by SiO 2the new SiGe nano-wire array three-dimensional structure schematic diagram that layer wraps up.

In the concentrated technique of above-mentioned germanium, only carry out thermal oxidative reaction at 1050 DEG C, the O passing into 2all reduce with the reaction time, therefore, Ge component in described pending SiGe nano wire 110 just raises, and do not have enough conditions to form pure Ge nano wire 112, finally on described insulating buried layer BOX21 surface, form described new SiGe nano wire 111 arrays and the respectively SiO of this new SiGe nano wire 111 of parcel 2layer 12.In the present embodiment, the new SiGe nano wire 111 obtaining is for cylindrical, and diameter is 70nm, and in this new SiGe nano wire 111, the component of Ge is elevated to 40%, the respectively SiO of this new SiGe nano wire 111 of parcel 2the thickness of layer 12 is 80nm.

In the present embodiment, the size of the concentrated concrete process conditions of above-mentioned germanium and the new SiGe nano wire 111 that forms and Ge the component width that only component of Ge is 30% in SiGe layer 11, the thickness of SiGe layer 11 is 100nm and pending SiGe nano wire 110 of new SiGe nano wire 111 be suitable for while being 125nm.But be not limited to this, in other embodiments, along with thickness, the component of Ge in described SiGe layer and the change of described pending SiGe nano wire 110 sizes of described SiGe layer 11, in the size of above-mentioned process conditions, the new SiGe nano wire 111 that forms and the new SixGe1-x nano wire 111 forming, the component 1-x of Ge also changes thereupon, and these process conditions are controlled.The quality of the new SiGe nano wire 111 that therefore, prepared by the method is controlled.

Finally, as shown in Figure 4 and Figure 6, utilize the HF of 5% concentration to erode and be wrapped in the respectively SiO on these Ge nano wire 112 surfaces 2layer 12, corrodes and can obtain Ge nano wire 112 arrays in 6 minutes to 8 minutes; Adopt the HF of same concentration to erode and be wrapped in the respectively SiO on these new SiGe nano wire 111 surfaces 2layer 12, etching time is can obtain new Si by 4 minutes in 2.5 minutes 0.6ge 0.4nano wire 111 arrays.

In sum, a kind of method of utilizing germanium concentration technique to prepare SiGe or Ge nano wire provided by the invention, by graphical and the concentrated method of germanium are combined, obtain a kind of SiGe of output and quality and controllable growth of Ge nano wire of ensureing, the method can obtain even and straight SiGe or Ge nano-wire array, and by can obtain SiGe and the Ge nano wire of different component to the control of oxidization time, the final nanowire length forming can reach hundreds of micron, diameter reaches tens nanometers, lays the first stone by the nano-wire devices afterwards that is designed to of figure.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.

Claims (11)

1. utilize germanium concentration technique to prepare a method for SiGe or Ge nano wire, it is characterized in that, at least comprise:
1) utilize smart-cut process to prepare SGOI structure;
2) utilize the pending SiGe nano-wire array that etches preliminary dimension on the SiGe layer of ion beam etching technique in described SGOI structure;
3) to described step 2) structure to carry out germanium concentrated, and control the concentrated process conditions of germanium to obtain surface by SiO 2new SiGe nano wire or the Ge nano-wire array of the preliminary dimension that layer wraps up;
4) utilize HF to erode respectively the respectively SiO of this new SiGe nano wire or Ge nanowire surface of parcel 2layer, obtains new SiGe nano wire or Ge nano-wire array;
Form by SiO 2layer wrap up Ge nano-wire array time, described step 3) also comprises:
3-1) by described step 2) structure put into 600 DEG C of reacting furnaces, then pass into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2;
3-2) pass into the O of 4000ccm 2keep stopping after 30 minutes;
3-3) pass into the N of 5000ccm 2keep stopping after 30 minutes;
3-4) repeating step 3-2 successively) with step 3-3) after 2 times, at N 2under atmosphere, make reacting furnace temperature drop to 900 DEG C from 1050 DEG C in 1 hour;
3-5) pass into the O of 4000ccm 2keep stopping after 30 minutes;
3-6) pass into the N of 5000ccm 2keep stopping after 30 minutes;
3-7) repeating step 3-5 successively) with step 3-6) after 3 times, at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 900 DEG C in 1 hour, complete germanium concentrated, form and include successively the 2nd Si substrate, insulating buried layer BOX and by SiO 2the stepped construction of the described Ge nano-wire array that layer wraps up;
Form by SiO 2layer wrap up new SiGe nano-wire array time, described step 3) also comprises:
3-1) by described step 2) structure puts into 600 DEG C of reacting furnaces, then passes into the N of 5000ccm 2as protective atmosphere, stop passing into N with 10 DEG C of speed heating reaction furnaces of rising per minute as for after reaching 1050 DEG C 2;
3-2) pass into the O of 4000ccm 2keep stopping after 30 minutes;
3-3) pass into the N of 5000ccm 2keep stopping after 30 minutes;
3-4) at N 2under atmosphere, make reacting furnace temperature be down to 600 DEG C from 1050 DEG C in 2 hours, complete germanium concentrated, form include successively the 2nd Si substrate, insulating buried layer BOX, by SiO 2the stepped construction of the described new SiGe nano-wire array that layer wraps up.
2. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 1, is characterized in that, described step 1) also comprises:
1-1) provide a Si substrate, epitaxial growth one deck SiGe layer on a described Si substrate;
1-2) adopt ion implantation technology to carry out H from described SiGe layer surface +implantation, and control ion implantation energy default degree of depth in a described Si substrate and form one deck and be rich in H +the silicon layer of ion is as peel ply;
1-3) provide the 2nd Si substrate, and prepare one deck insulating buried layer BOX on described the 2nd Si substrate;
1-4) utilize bonding technology that the stepped construction that bonding formation includes the 2nd Si substrate, insulating buried layer BOX, SiGe layer, a Si substrate is successively carried out to the insulating buried layer BOX layer surface on the 2nd Si substrate in the SiGe layer surface on the one Si substrate;
1-5) structure after para-linkage is carried out the high temperature anneal, to peel off the described Si substrate of part from described peel ply; Concrete technology condition is: be first warmed up to 300 DEG C, be incubated after 3 hours, a Si substrate is peeled off at peel ply place, then be incubated half an hour after half an hour is warmed up to 600 DEG C, improve the bond strength of bonded interface, whole process is connected with high-purity O of 8000ccm 2;
1-6) utilize TMAH corrosive liquid that a remaining described Si substrate is all eroded to obtain SGOI structure.
3. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 2, is characterized in that: described step 1-1) in the thickness of epitaxially grown SiGe layer be 80nm~120nm.
4. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 2, is characterized in that: described step 1-1) atomic percent of Ge is 12%~30% in SiGe layer.
5. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 2, is characterized in that: described step 1-3) in the material of the insulating buried layer BOX for preparing on the 2nd Si substrate be SiO 2or Al 2o 3.
6. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 1, is characterized in that: described step 2) in the width of the pending SiGe nano wire that SiGe layer forms described in etching be 50nm~200nm.
7. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 6, is characterized in that: the respectively SiO of this Ge nano wire of parcel 2the thickness of layer is 190nm.
8. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 6, is characterized in that: described Ge nano wire is cylindrical, and diameter is 30nm.
9. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 1, is characterized in that: the respectively SiO of this new SiGe nano wire of parcel 2the thickness of layer is 80nm.
10. the method for utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 1, is characterized in that: described new SiGe nano wire be shaped as cylinder, and its diameter is 70nm.
11. methods of utilizing germanium concentration technique to prepare SiGe or Ge nano wire according to claim 1, is characterized in that: in described new SiGe nano wire, the atomic percent of Ge is 40%.
CN201210225391.8A 2012-07-02 2012-07-02 Method for preparing SiGe or Ge nanowire by using germanium concentration technology CN102751232B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210225391.8A CN102751232B (en) 2012-07-02 2012-07-02 Method for preparing SiGe or Ge nanowire by using germanium concentration technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210225391.8A CN102751232B (en) 2012-07-02 2012-07-02 Method for preparing SiGe or Ge nanowire by using germanium concentration technology

Publications (2)

Publication Number Publication Date
CN102751232A CN102751232A (en) 2012-10-24
CN102751232B true CN102751232B (en) 2014-07-30

Family

ID=47031301

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210225391.8A CN102751232B (en) 2012-07-02 2012-07-02 Method for preparing SiGe or Ge nanowire by using germanium concentration technology

Country Status (1)

Country Link
CN (1) CN102751232B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646910B (en) * 2013-12-24 2016-06-15 中国科学院上海微系统与信息技术研究所 A kind of preparation method of SGOI structure
CN103700582B (en) * 2013-12-27 2016-08-17 中国科学院微电子研究所 A kind of manufacture method of Ge nanoline laminated construction
CN103928297B (en) * 2013-12-28 2017-04-26 华中科技大学 Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure
CN105174268A (en) * 2015-09-21 2015-12-23 中国科学院上海微系统与信息技术研究所 Nanowire and graphene composite material and preparation method thereof
CN106653566A (en) * 2016-11-29 2017-05-10 东莞市广信知识产权服务有限公司 SiGe nanowire making method
CN107146834B (en) * 2017-05-03 2019-01-25 中国科学院上海微系统与信息技术研究所 The preparation method of Ge nanometers of line luminous materials in a kind of face
CN109879275A (en) * 2019-01-30 2019-06-14 宁波大学 A kind of method that the concentration of combination germanium prepares graphene with ion implantation technique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2905197B1 (en) * 2006-08-25 2008-12-19 Commissariat Energie Atomique Method for producing a device comprising a structure provided with one or more microwires or nano-threads based on a compound of si and ge, by germanium condensation
US20080135949A1 (en) * 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SGOI、SODI新结构材料及其相关技术研究;狄增峰;《中国博士学位论文全文数据库》;20070215;第47~48页 *
狄增峰.SGOI、SODI新结构材料及其相关技术研究.《中国博士学位论文全文数据库》.2007,

Also Published As

Publication number Publication date
CN102751232A (en) 2012-10-24

Similar Documents

Publication Publication Date Title
US10355113B2 (en) Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US9214353B2 (en) Systems and methods for laser splitting and device layer transfer
CN204680685U (en) Nano-wire devices and the structure with nano wire
US9018675B2 (en) Heterojunction III-V photovoltaic cell fabrication
US20170309733A1 (en) Methods and devices for fabricating and assembling printable semiconductor elements
Lee et al. Flexible inorganic nanostructure light‐emitting diodes fabricated on graphene films
US9012887B2 (en) Nanowire growth on dissimilar material
Akatsu et al. Germanium-on-insulator (GeOI) substrates—a novel engineered substrate for future high performance devices
CN103430298B (en) There is the silicon on insulated substrate of high resistivity portion and manufacture the method for this class formation in process wafer
US7999344B2 (en) Optoelectronic device with germanium photodetector
JP5735585B2 (en) 2D device array
TWI472477B (en) Silicon nanostructures and method for producing the same and application thereof
CN101595565B (en) Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
Adachi et al. Optical properties of crystalline− amorphous core− shell silicon nanowires
Shen et al. Hierarchical saw-like ZnO nanobelt/ZnS nanowire heterostructures induced by polar surfaces
CN1745468B (en) Large-area nanoenabled macroelectronic substrates and uses therefor
Meitl et al. Transfer printing by kinetic control of adhesion to an elastomeric stamp
EP2064734B1 (en) Method of printing transferable functional structures
US8119434B2 (en) Fast p-i-n photodetector with high responsitivity
US7354809B2 (en) Method for double-sided processing of thin film transistors
Werner et al. From polycrystalline to single crystalline silicon on glass
US7960251B2 (en) Method for producing nanowires using a porous template
US7709352B2 (en) In-place bonding of microstructures
US20100112784A1 (en) Large area semiconductor on glass insulator
Kimukin et al. Surface depletion thickness of p-doped silicon nanowires grown using metal-catalysed chemical vapour deposition

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant