CN107402899A - A kind of extended method of IIC interfaces - Google Patents
A kind of extended method of IIC interfaces Download PDFInfo
- Publication number
- CN107402899A CN107402899A CN201710651803.7A CN201710651803A CN107402899A CN 107402899 A CN107402899 A CN 107402899A CN 201710651803 A CN201710651803 A CN 201710651803A CN 107402899 A CN107402899 A CN 107402899A
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- China
- Prior art keywords
- iic
- interfaces
- iic interfaces
- mcu
- extended method
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
Abstract
The invention discloses a kind of extended method of IIC interfaces, extends IIC interfaces by expansion board, expansion board is provided with N bar IIC signal paths；N is integer, N >=2；The first end of N number of IIC signal paths in described expansion board is connected with N number of IIC interfaces on MCU respectively；Second end of N number of IIC signal paths in described expansion board connects N bar iic bus respectively.The extended method of the IIC interfaces is easy to implement, can improve the load capacity of IIC interfaces.
Description
Technical field
The present invention relates to a kind of extended method of IIC interfaces.
Background technology
IIC is IC bus, is a kind of two-way, binary system, synchronous serial bus.The bus is a kind of multidirectional control
Bus, multiple chips may be connected under same bus structure, and each chip can serve as the voltage input of real-time Data Transmission.Hang
It is divided into main frame and slave in the device on iic bus, main frame is responsible for initializing the data of iic bus and generation allows transmission
Clock signal, slave are possessed uniquely from address, and by the device of host addressing.In view of IIC, using simply, interface resource accounts for
With it is few the characteristics of, more and more popularized in fields such as sensor data acquisitions.
In common application scenarios, typically multiple IIC slave units are directly hung in bus and communicated, but it is in view of total
The driving force of line and the reason such as support capacitive reactance limited so that in bus can carry equipment and bus transfer limited length, no
Can meet the needs of some IIC application scenarios.Therefore, it is necessary to be extended to IIC.
For the method for IIC Interface Expandings, have some patents of invention at present and propose solution.Such as
CN101324875A proposes a kind of based on the method that main equipment one-level iic bus is expanded to a plurality of two level iic bus, and this is special
Profit includes clock expansion module, data control block and direction controlling module, and clock expansion module is by one-level IIC SCL signal
Multichannel is extended to, data control block is used for the selection of two level iic bus, and direction controlling module is written and read the control in direction.
The extended mode based on CPLD OR gates that and for example CN104142905A is proposed, the data register of (n+1) position is set and made
Each and the input that inputs OR gate divides a position of corresponding data register to realize the extension of IIC slave units.And for example
The connected device of clock switch is connected in the method based on clock switch group that CN1599343A is proposed, only clock switch group
The request of iic bus controller can be responded, after the completion of corresponding iic bus read-write operation, closes corresponding clock switch.
The IIC Interface Expandings method proposed at present in patent forms multipath clock using external clock expansion module more, then
Step-by-step behaviour is carried out to the address signal of slave unit by the IIC slave units of gating circuit selection connection, or by CPLD gate circuits
Gated.These modes are directed to same can not change from multiple slave units of address more and connect scene, but for because of IIC
Itself driving not enough causes access device to be limited, or capacitive reactance is limited to cause bus transfer distance must not be too far away because IIC itself is accessed,
Or by hardware limitation, the application scenarios of a variety of bus levels can not be accessed, do not provide suitable solution method；It is and above-mentioned special
Benefit introduces the other devices such as CPLD, FPGA, adds the complexity of hardware cabling and the difficulty of software programming.
Therefore, it is necessary to design a kind of extended method of IIC interfaces.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of extended method of IIC interfaces, the extension side of the IIC interfaces
Method extends IIC interfaces by expansion board, easy to implement.
The technical solution of invention is as follows：
A kind of extended method of IIC interfaces, IIC interfaces are extended by expansion board, expansion board is led to provided with N bar IIC signals
Road；N is integer, N >=2；
The first end of N number of IIC signal paths in described expansion board is connected with N number of IIC interfaces on MCU respectively；
Second end of N number of IIC signal paths in described expansion board connects N bar iic bus respectively.
IIC interfaces on described MCU are the interface of IIC controllers, that is, utilize the IIC interfaces carried on MCU.
IIC interfaces on described MCU are the IIC interfaces simulated by universal I/O port, i.e., simulating IIC by I/O interface connects
Mouthful.
IIC interfaces on described MCU are the IIC interfaces realized by IP kernel, i.e., configure IIC interfaces by IP kernel.
Bidirectional bus buffer is provided with each IIC signal path in expansion board.It is preferred that P82B96 chips.
Described MCU is integrated in core board.
Field programmable gate array is also integrated with core board.If possessing field programmable gate array inside MCU, such as
ZC7020 chips etc., can be realized IIC interface functions by programmable gate array, and MCU not necessarily possesses the function.
To realize the electrical level match of expansion board and MCU, connect directly by pull-up resistor in the first end of N number of IIC signal paths
It is the reference voltage of MCU IIC interfaces to flow voltage V1, V1.
To realize expansion board and the electrical level match of IIC loads, pass through pull-up resistor at the second end of N number of IIC signal paths
It is the reference voltage of the IIC interfaces of load end to meet DC voltage V2, V2.
Preferably, N=4.
Beneficial effect：
The extended method of the IIC interfaces of the present invention, the extension of IIC interfaces is realized by expansion board.The device causes hardware
Collection of the circuit board to descending IIC slave units is more compatible, disclosure satisfy that the extension of IIC slave units, supports up to four kinds not
With the conversion of bus level.In the case where slave unit quantity is few, iic bus level species is few, the buffer chip of expansion board
The property of can be chosen is welded, and will not increase the extra cost of system.
The present invention can solve following technical problem：
1. solves the problem of access IIC slave units are excessive, and cpu i/f resource is inadequate.
2. solution is because of the problem of IIC slave units extend, and hardware circuit board compatibility is inadequate.
3. solve the problems, such as that the quantity of slave unit and communication distance are limited by iic bus 400pF capacitive reactances.
4. solves the skimble-scamble problem of IIC slave unit level logic level.
5. solve the problems, such as that serial multi pass acquisition influences collecting efficiency and real-time.
Brief description of the drawings
Fig. 1 is the general structure block diagram of the extended method of IIC interfaces；
Fig. 2 is the connection diagram of IIC signal paths all the way；
Fig. 3 is overview flow chart；
Fig. 4 is specific tasks call flow chart.
Fig. 5 is that interface 0-3 and power interface define schematic diagram；
Fig. 6 is that some connecting element interface defines schematic diagram.
Embodiment
The present invention is described in further details below with reference to the drawings and specific embodiments：
Embodiment 1：Such as Fig. 1~6, a kind of extended method of IIC interfaces, IIC interfaces are extended by expansion board, in expansion board
Provided with 4 IIC signal paths；The first end of 4 IIC signal paths in described expansion board respectively with 4 IIC on MCU
Interface is connected；Also there is M IIC equipment, M>4.
Second end of 4 IIC signal paths in described expansion board connects 4 iic bus respectively.
IIC interfaces on described MCU are the interface of IIC controllers, i.e., using the IIC interfaces carried on MCU, are specially
2.
IIC interfaces on described MCU are the IIC interfaces simulated by universal I/O port, i.e., simulating IIC by I/O interface connects
Mouthful, specially 1.
IIC interfaces on described MCU are the IIC interfaces realized by IP kernel, i.e., configure IIC interfaces by IP kernel, are had
Body is 1.
Bidirectional bus buffer is provided with each IIC signal path in expansion board.It is preferred that P82B96 chips.
Described MCU is integrated in core board.
Field programmable gate array is also integrated with core board.
To realize the electrical level match of expansion board and MCU, connect directly by pull-up resistor in the first end of 4 IIC signal paths
Voltage V1, V1 are flowed for the reference voltage of MCU IIC interfaces, specially 3.3V.
To realize expansion board and the electrical level match of IIC loads, pass through pull-up resistor at the second end of N number of IIC signal paths
It is the reference voltage of the IIC interfaces of load end to meet DC voltage V2, V2, is such as 12V, also differs and be set to 12V, depending on IIC slave units
Depending on operation level, figure is the bus connection all the way by taking 12V as an example.
The method and apparatus of the multichannel IIC extensions of the present invention are included with lower module：
Core board module, the module are to include the minimum system including CPU.4 independent road IIC interfaces IIC0- can be drawn
IIC3 (can be by the IIC controllers built in MCU, IO simulations or as built in ZC7020 etc. possesses field programmable gate array MCU
IP kernel is realized), it is responsible for sending IIC equipment read-write sequence, returns to ACK, and preserves, parses, handling the data of slave unit.
Plate module is extended, the module is single one piece of circuit board, and it is with core board by the way of winding displacement or connector
It is attached.There are four group interfaces to upper core plate, connect four IIC controllers of core board respectively, have under for connecting
4 groups of power interfaces of varying level bus and multigroup IIC interfaces for connecting IIC slave units.Board memory is in four P82B96
Buffer chip is used for the supported IIC slave units capacitive reactance of lifting system, and is MCU by four kinds of different bus logic level conversions
Level.
P82B96 is bidirectional bus buffer；P82B96 is a bipolarity, inside without latch, bi-directional logic interface unit
Part, it provides standard I2Bridge joint between C devices and remote bus, can by the similar bus of different voltage and current ranks with
I2C buses are bridged.The device can bridge SMBus (350 μ A), 3.3V logical devices, and 15V level and low impedance leads can be with
Extend communication distance, increase antijamming capability.The device is to I2C bus protocols and clock rate do not have particular/special requirement.P82B96
I can be increased2Minimum load number, new bus load number and the remote I mounted on C bus nodes2C bus device numbers, and will not be to this
Ground node impacts.Mounting device count and limitation physically can also greatly reduce.Pass through balanced transmission line (twisted-pair feeder)
Or light-coupled isolation (optical fiber) sends signal, the separation in Tx, Rx structure makes its transmission become simple, and the direct phase of Tx and Rx signals
Without locked when even.
Slave unit module, the module is a variety of intelligent acquisition sensors for supporting iic bus host-host protocols, with aboard
Application scenarios exemplified by, the module includes acceleration transducer, obliquity sensor, temperature sensor and pressure sensor etc..Together
One type or sensor with bus level amplitude are connected to same connector group, are easy to P82B96 chips by corresponding level conversion
By signal output to core board after to suitable threshold value.
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.On the contrary, this
All changes that the embodiment of invention includes falling into the range of the spirit and intension of attached claims, modification and equivalent
Thing.The description of this part is only exemplary and explanatory, should not there is any restriction effect to protection scope of the present invention.This
Outside, those skilled in the art, can be to the spy in embodiment in this document and in different embodiments according to the description of this document
Sign carries out respective combination.
In the description of the invention, it is necessary to which explanation, unless otherwise clearly defined and limited, term " connected ", " connects
Connect " it should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or it is integrally connected；It can be machine
Tool connects or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary.For this area
For those of ordinary skill, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.In addition, the present invention's
In description, unless otherwise indicated, " multiple " are meant that two or more.
Any process or method described otherwise above description in flow chart or herein is construed as, and represents to include
Module, fragment or the portion of the code of the executable instruction of one or more the step of being used to realize specific logical function or process
Point, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discuss suitable
Sequence, including according to involved function by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
As shown in Fig. 2 it is the hardware connection diagram by taking MCU single channel IIC interfaces and its related circuit as an example.Need to illustrate
, using MCU I/O port and power supply electrical level as the iic bus level that 3.3V, sensor are drawn it is 12V in Fig. 2, external four biographies
Sensor, which illustrates, to be only illustrative, and it is solid to be responsible for being had no from IIC number of devices and bus level size for collection in the present invention
Definite value, by taking four sensors and fixed level size as an example merely to for the sake of clear.
As shown in Fig. 2 by taking four IIC slave units as an example.
MCU is the promoter of IIC communications, i.e. IIC main equipment.MCU itself possesses multiple IIC controllers, can by with
Put corresponding registers and automatically generate suitable IIC sequential by chip internal circuits in bus, when IIC amount controllers are inadequate
When, IIC sequential can be simulated by I/O port and complete IIC communication needs；In addition, the MCU for possessing field programmable gate array at some
In, IIC modules can also be realized by IP kernel.When needing gathered data, application program is formed according to the slave unit address of solidification
Corresponding transmission byte, by writing IIC control registers and reading transmission, reception and the transmission of IIC status registers completion data
The judgement of state.
After MCU sends data, data can be transmitted to Sx the and Sy pins of P82B96 chips, and backward bottom is handled through chip
IIC slave units are transmitted.In view of in slave unit iic bus level difference, must be by the pull-up of the descending end interface of P82B96 chips electricity
Resistance is arranged to consistent with IIC slave units, and the pull-up resistor of upstream ends is arranged into consistent with MCU I/O port level, to complete
The level conversion function of iic bus.
MCU, which is sent, will transmit the data in the bus with after the data of address, being connected with IIC slave units, and with this
Bus (acknowledgement character response) can be dragged down from the equipment of address matching, then, MCU and the slave unit just carry out the interaction of next step data.
The method of multichannel IIC data acquisitions is as shown in Figure 3-4.
(1) carry out basic initialization of register by bootloader to work, built for the operation of latter acts system
Embedded hardware environment.
(2) ucosii operating systems are run, and MCU soft and hardwares are further initialized and configured；And according to need
Configure IIC controllers or simulate the pin pattern of I/O interface.
(3) four task blocks are created and carry out the collections of four road iic bus data respectively, after task creation, give ucosii
Operating system carries out the scheduling and management of task.
(4) operating system be dispatched to task one perform after, task one by determine need access equipment from address, and according to
The data of read-write demand (setting bit0) one byte of generation are put into iic bus, if address matches, MCU can detect ACK
Position, then carry out the reading writing working of next step.
(5) after current slave unit interaction terminates, next slave unit for needing to access can be judged and continue bus
Read-write.
(6) task management and scheduling are carried out using real time operating system so that code is more succinct efficient, and maintenance difficulties
Reduce.In existing application scenarios, IIC sends to receive and realized more in same thread, and the access to slave unit must be serial
Order is carried out, inefficient, and the present invention can make four task blocks wait process to be feedback by the way of Foreground and Background combination
In automatic release CPU controls carry out task switching, until just may proceed to perform after being interrupted wake-up.
Claims (10)
1. a kind of extended method of IIC interfaces, it is characterised in that IIC interfaces are extended by expansion board, expansion board is provided with N bars
IIC signal paths；N is integer, N >=2；
The first end of N number of IIC signal paths in described expansion board is connected with N number of IIC interfaces on MCU respectively；
Second end of N number of IIC signal paths in described expansion board connects N bar iic bus respectively.
2. the extended method of IIC interfaces according to claim 1, it is characterised in that the IIC interfaces on described MCU are
The interface of IIC controllers, that is, utilize the IIC interfaces carried on MCU.
3. the extended method of IIC interfaces according to claim 1, it is characterised in that the IIC interfaces on described MCU are
The IIC interfaces simulated by universal I/O port, i.e., IIC interfaces are simulated by I/O interface.
4. the extended method of IIC interfaces according to claim 1, it is characterised in that the IIC interfaces on described MCU are
The IIC interfaces realized by IP kernel, i.e., configure IIC interfaces by IP kernel.
5. the extended method of IIC interfaces according to claim 1, it is characterised in that each IIC signal in expansion board
Bidirectional bus buffer is provided with path.
6. the extended method of IIC interfaces according to claim 1, it is characterised in that described MCU is integrated in core board
In.
7. the extended method of IIC interfaces according to claim 5, it is characterised in that the scene that is also integrated with core board can
Program gate array.
8. the extended method of IIC interfaces according to claim 1, it is characterised in that to realize expansion board and MCU level
Matching, it is the benchmark of MCU IIC interfaces to meet DC voltage V1, V1 by pull-up resistor in the first end of N number of IIC signal paths
Voltage.
9. the extended method of IIC interfaces according to claim 1, it is characterised in that to realize expansion board and IIC loads
Electrical level match, it is the IIC interfaces of load end to meet DC voltage V2, V2 by pull-up resistor at the second end of N number of IIC signal paths
Reference voltage.
10. the extended method of the IIC interfaces according to claim any one of 1-9, it is characterised in that N=4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710651803.7A CN107402899A (en) | 2017-08-02 | 2017-08-02 | A kind of extended method of IIC interfaces |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710651803.7A CN107402899A (en) | 2017-08-02 | 2017-08-02 | A kind of extended method of IIC interfaces |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256544A (en) * | 2008-03-25 | 2008-09-03 | 华为技术有限公司 | Method, apparatus and system for expansion of inside integrated circuit bus |
| CN102117264A (en) * | 2010-12-29 | 2011-07-06 | 中国船舶重工集团公司第七一五研究所 | Fast Walsh transform realization method based on FPGA (Field Programmable Gate Array) |
| CN103179054A (en) * | 2013-03-11 | 2013-06-26 | 鼎点视讯科技有限公司 | Control panel and control method for optical network unit |
| CN203800921U (en) * | 2014-04-15 | 2014-08-27 | 昆山柯斯美光电有限公司 | I2C signal reinforcement apparatus for photoelectric composite cable |
| CN106168934A (en) * | 2016-06-29 | 2016-11-30 | 锐捷网络股份有限公司 | A kind of data transmission method and device |
-
2017
- 2017-08-02 CN CN201710651803.7A patent/CN107402899A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256544A (en) * | 2008-03-25 | 2008-09-03 | 华为技术有限公司 | Method, apparatus and system for expansion of inside integrated circuit bus |
| CN102117264A (en) * | 2010-12-29 | 2011-07-06 | 中国船舶重工集团公司第七一五研究所 | Fast Walsh transform realization method based on FPGA (Field Programmable Gate Array) |
| CN103179054A (en) * | 2013-03-11 | 2013-06-26 | 鼎点视讯科技有限公司 | Control panel and control method for optical network unit |
| CN203800921U (en) * | 2014-04-15 | 2014-08-27 | 昆山柯斯美光电有限公司 | I2C signal reinforcement apparatus for photoelectric composite cable |
| CN106168934A (en) * | 2016-06-29 | 2016-11-30 | 锐捷网络股份有限公司 | A kind of data transmission method and device |
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Application publication date: 20171128 |