CN102255975A - Dual-port-random access memory (RAM)-based embedded common Ethernet/Internet protocol (IP) communication interface device - Google Patents
Dual-port-random access memory (RAM)-based embedded common Ethernet/Internet protocol (IP) communication interface device Download PDFInfo
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Abstract
The invention discloses a dual-port-random access memory (RAM)-based embedded common Ethernet/Internet protocol (IP) communication interface device, which comprises a core board unit and a bottom plate unit, wherein the core board unit is used for receiving, transmitting, analyzing and processing the data information of an Ethernet/IP industrial network and external equipment, providing an indication logical for an indication circuit in the bottom plate unit, fixing system information and providing software support for the whole device; and the bottom plate unit is connected with the core board unit to form a whole by a core board interface circuit, and is used for communicating with the Ethernet/IP network to exchange Ethernet/IP data, communicating with the external equipment to exchange external data, providing a standard circuit interface for the external equipment, interconnecting the communication interface device and the external equipment, indicating the current working condition of the communication interface device and providing power supply and resetting functions for the communication interface device. The dual-port-RAM-based embedded common Ethernet/IP communication interface device has high universality, and can exchange Ethernet/IP data information with any external equipment when the external equipment meets the specifications of the interface circuit in the communication interface device.
Description
Technical field
The present invention relates to the industrial network communication technical field, particularly relate to a kind of universal embedded Ethernet/IP communication interface with extensive versatility.
Background technology
Industrial automation control system develops towards intelligent, information-based, networked direction in recent years.At present in all network technologies, standard network on having come true based on the ethernet technology of ICP/IP protocol, standard TCP/IP Ethernet is extended to the industrial time controlling field, combine with universal industrial protocol CIP (Common Industrial Protoco1), just formed Industrial Ethernet Ethernet/IP.
Because the Ethernet/IP development time is not long, at the early-stage especially in China, so Ethernet/IP is faced with variety of problems in the popularization of China, development cost height, the serious scarcity of technical professional or the like are restricting the development of Ethernet/IP.
The integrated Industrial Ethernet that enters of traditional non-Industrial Ethernet equipment not only needs huge Industrial Ethernet communication protocol code is embedded the into software control system of equipment, even to change the project organization of equipment in a large number, renovation technique complexity and cost are very high, are unfavorable for the integrated of industrial equipment and Industrial Ethernet.
Universal embedded Ethernet/IP communication interface at present also do not occur possessing, make it can be interconnected with the external equipment that satisfies interface circuit 1027 standards arbitrarily based on dual port RAM.
Summary of the invention
The objective of the invention is to overcome the prior art above shortcomings, a kind of universal embedded Ethernet/IP communication interface based on dual port RAM is provided, make it have versatility widely, can carry out interconnected with the external equipment that has the standard interface circuit arbitrarily, and reflect by indicating circuit and the working condition of current communication interface to make things convenient for the staff to carry out the failure monitoring and the investigation of device.
Universal embedded Ethernet/IP communication interface based on dual port RAM provided by the invention comprises core board unit and bottom board unit two parts, wherein,
The core board unit:
By microprocessor and constitute with two-way SDRAM circuit that is connected of microprocessor and FLASH circuit respectively; Described core board unit is used to receive the data message of transmission and analyzing and processing Ethernet/IP Industrial Ethernet and external equipment, for the indicating circuit in the bottom board unit provides the indication logical signal, and cure system information, and provide the software support for whole device;
Bottom board unit comprises:
The core board interface circuit: bottom board unit is connected with the core board unit by the core board interface circuit, makes core board unit and bottom board unit constitute an integral body;
Ethernet circuit: be connected with the Ethernet/IP network bi-directional, be connected with the core board unit is two-way by the core board interface circuit simultaneously, by ethernet circuit, be used for the core board unit and the Ethernet/IP network carries out information interaction, exchange Ethernet/IP network data;
External data switched circuit: be connected with the core board unit is two-way by the core board interface circuit, be connected by interface circuit and external equipment are two-way simultaneously, core board unit and external equipment are communicated, the exchange external data by the external data switched circuit;
Indicating circuit: be connected with the core board unit by the core board interface circuit, provide the indication logical signal by the core board unit, indicate the operating state of current communication interface by indicating circuit, when the communication module operation irregularity, indicating circuit sends abnormal show, shows behind the abnormal restoring to recover normal;
Power circuit: be connected with the core board unit by the core board interface circuit, and be connected with external equipment, provide stabilized power supply for communication interface by power circuit through interface circuit;
Reset circuit: be connected with the core board unit by the core board interface circuit, connect external equipment through interface circuit simultaneously, provide reset function by reset circuit for communication interface, the reset command signal that reset circuit sends according to external equipment awards core board unit reseting logic signal, after reset signal is triggered, communication interface will restart;
Interface circuit: for external equipment provides the preferred circuit interface, make the communication interface can be interconnected with the external equipment that satisfies the interface circuit standard arbitrarily by interface circuit, plug and play be convenient to Installation and Debugging.
Advantage of the present invention and beneficial effect:
By above technical scheme provided by the invention as seen, compared with prior art, the invention provides a kind of embedded Ethernet/IP Generalized Communication Interface device based on dual port RAM, its can with satisfy interface circuit 1027 standards arbitrarily, the external equipment that promptly has the 15X2 needle interface slot of 2.00mm normal pitch carries out interconnecting and switching Ethernet/IP network data, has versatility widely, make things convenient for Installation and Debugging, and provide operating state to point out, the personnel of maintaining easily carry out the failure monitoring and the investigation of device, device recovers operate as normal automatically after fault is got rid of, and has great practical significance.
Description of drawings
Fig. 1 is the overall construction drawing of a kind of embedded Ethernet based on dual port RAM provided by the invention/IP Generalized Communication Interface device;
Fig. 2 is a microprocessor 1011S3C2440 circuit diagram in Fig. 1 core board unit 101;
Fig. 3 is the circuit diagram of FLASH1013 circuit in Fig. 1 core board unit 101;
Fig. 4 is the circuit diagram of SDRAM1012 circuit in Fig. 1 core board unit 101;
Fig. 5 is a core board interface circuit 1021 in Fig. 1 bottom board unit 102;
Fig. 6 is the circuit diagram of ethernet circuit 1022 in Fig. 1 bottom board unit 102;
Fig. 7 is the circuit diagram of outside exchanges data circuit 1023 in Fig. 1 bottom board unit 102;
Fig. 8 is the circuit diagram of indicating circuit 1024 in Fig. 1 bottom board unit 102;
Fig. 9 is the circuit diagram of power circuit 1025 in Fig. 1 bottom board unit 102;
Figure 10 is the circuit diagram of reset circuit 1026 in Fig. 1 bottom board unit 102;
Figure 11 is the circuit diagram of interface circuit 1027 in Fig. 1 bottom board unit 102.
In order to make those skilled in the art person understand the present invention program better, the present invention will be described below in conjunction with drawings and embodiments.
Embodiment
Fig. 1 is the overall construction drawing of a kind of universal embedded Ethernet/IP communication interface based on dual port RAM provided by the invention.
Referring to Fig. 1, the universal embedded Ethernet/IP communication interface based on dual port RAM provided by the invention comprises, core board unit 101 and bottom board unit 102 two parts, wherein,
Core board unit 101:
By microprocessor 1011 and constitute with microprocessor 1011 two-way SDRAM circuit 1012 that are connected and FLASH circuit 1013 respectively; Described core board unit is used to receive the data message of transmission and analyzing and processing Ethernet/IP Industrial Ethernet and external equipment, for the indicating circuit in the bottom board unit provides the indication logical signal, and cure system information, and provide the software support for whole device;
Core board interface circuit 1021: bottom board unit is by 1011 two-way connections of microprocessor in core board interface circuit and the core board unit 101, makes core board unit 101 integral body of formation that links to each other with bottom board unit 102;
Ethernet circuit 1022: be connected with the Ethernet/IP network bi-directional, simultaneously by core board interface circuit 1021 and 101 two-way connections of core board unit, by ethernet circuit 1022, be used for core board unit 101 and carry out information interaction, exchange Ethernet/IP network data with the Ethernet/IP network;
External data switched circuit 1023: be connected with the core board unit is two-way by core board interface circuit 1021, be connected with external equipment is two-way by interface circuit 1027 simultaneously, by external data switched circuit 1023 core board unit 101 and external equipment are communicated, the exchange external data;
Indicating circuit 1024: be connected with the core board unit by core board interface circuit 1021, provide the indication logical signal by core board unit 101, operating state by the current communication interface of indicating circuit 1024 indications, indicating circuit sends abnormal show in the time of the communication module operation irregularity, shows behind the abnormal restoring to recover normal;
Power circuit 1025: be connected with the core board unit by core board interface circuit 1021, and be connected with external equipment, by power circuit 1025, for communication interface provides stabilized power supply through interface circuit 1027;
Reset circuit 1026: be connected with the core board unit by core board interface circuit 1021, connect external equipment through interface circuit 1027 simultaneously, by reset circuit 1026, for communication interface provides reset function, the reset command signal that reset circuit 1026 sends according to external equipment awards the microprocessor 1011 reseting logic signals in the core board unit 101, after reset signal is triggered, communication interface will restart.
Interface circuit 1027: by interface circuit 1027, for external equipment provides the preferred circuit interface, make the communication interface can be interconnected with the external equipment that satisfies interface circuit 1027 standards arbitrarily, plug and play be convenient to Installation and Debugging.
The concrete structure of each element circuit that apparatus of the present invention relate to is as follows:
Microprocessor 1011, referring to Fig. 2, employing is based on 16/32 RISC embedded microprocessor S3C2440A of ARM920T kernel, be used for gathering and issue Ethernet/IP data and external device data to bottom board unit 102, reception is from the reset signal of the reset circuit 1026 of bottom board unit 102, to the operating state that the indicating circuit 1024 of bottom board unit 102 provides the logic index signal to reflect current communication interface, the initializers protocol stack is finished all software processes tasks of communication interface;
On the specific implementation, described microprocessor 1011 is gathered in the bottom board unit 102 external device data in the Ethernet/IP network data and exchanges data circuit in the ethernet circuit 1022, and issues Ethernet/IP data and external data to ethernet circuit 1022 and exchanges data circuit; Collection is from the reset signal of reset circuit 1026 in the bottom board unit 102, and microprocessor 1011 is restarted after receiving reset signal automatically; In addition, microprocessor 1011 is the working condition of scanning communication interface constantly, sends the indicating circuit 1024 of indication logical signal to bottom board unit 102, reflects the operating state of current communication interface;
Need to prove that microprocessor 1011 is after initially powering on, the state of all parameters all needs an initial value, could enter normal operating state under an initial condition like this.When microprocessor 1011 begins to carry out, need will be relevant parameter such as communication interface IP address, I/O swap byte count parameter such as size and write microcontroller, communication interface ability operate as normal like this.Therefore all initiation parameters need be written in the microprocessor 1011 by the external data switched circuit of external equipment by bottom board unit 102, thereby finish initialization.
FLASH circuit 1013, referring to Fig. 3, be connected with control bus and microprocessor are two-way by data/address bus, Samsung K9F2G08U0B-PCB0 is a NAND type FLASH chip, and data storage capacity is 256M, also has the NOR type FLASH of 2M, constituting two FLASH starts, microprocessor 1011 is read and write the program information and the configuration information of communication interface by NAND type FLASH chip, and program stored information can not lost after the communication interface power down;
SDRAM circuit 1012, referring to Fig. 4, having a slice model is the synchronous DRAM SDRAM1012 chip of the 64MB capacity of MT48LC16M16A2P, be connected by address bus, data/address bus and control bus and processor are two-way, for processor provides data-handling capacity at a high speed, be used for running space, data and the stack area of the program of doing in system by jumbo SDRAM1012 chip;
Core board interface circuit 1021 referring to Fig. 5, comprises that the standard of the spacing 2.0mm of 2 groups of 36X2 and two groups of 16X2 patches device, makes core board unit 101 and 102 two-way connections of bottom board unit, constitutes an integral body on electrical characteristic and the physical characteristic;
Ethernet circuit 1022, interface circuit figure referring to Fig. 6 ethernet circuit 1022, comprise: ethernet controller DM9000 is connected with control bus is two-way by data/address bus LDATA0-LDATA15 with microprocessor 1011, be used for to send to microprocessor 10111011 from the data message of Ethernet/IP network, microprocessor 1011 according to the Ethernet/IP standard to judging from the message of Ethernet/IP Industrial Ethernet and filtering (promptly resolving), and the Ethernet/IP data message that reception issues from microprocessor 1011 sends on the Ethernet/IP network, promptly send the message that meets the Ethernet/IP agreement, thereby improve the communication efficiency of communication interface of the present invention to the Ethernet/IP Industrial Ethernet; The two-way swap data that is connected of four pins of TDP, TDN, RDP, RDN of the TXO+ of ethernet controller, TXO-, four pins of RXI+, RXI-and network filter H1102NL, the two-way swap data that is connected of four pins of TXP, TXN, RXP, RXN of TX+, the TX-of ethernet interface circuit device R J45, RX+, four pins of RX-and network filter H1102NL, the Ethernet physical interface is provided, and 3.3V power supply and earth signal provide analog power and simulation earth signal by electric capacity, inductive circuit for ethernet circuit.
External data switched circuit 1023 referring to Fig. 7, with 1011 two-way connections of microprocessor, is used to receive the data that microprocessor 1011 issues and gives external equipment, and will send to microprocessor 1011 from the data of external equipment;
External data switched circuit 1023 shown in Figure 7, adopt the dual port RAM of 8 bit data position 5V supply power voltages that the space of the data sharing between communication interface and the application apparatus is provided, the nGCS5 pin of microprocessor 1011 is as shared chip select line and level transferring chip SN74LVC4245
Pin and dual port RAM
Pin links to each other, have only when chip select line be that low level just allows element work when choosing them.8 position datawire DATA[0:7 of microprocessor 1011] data wire I/O[0:7 by level transferring chip SN74LVC4245 and dual port RAM] L links to each other, and the LnWE pin of microprocessor 1011 links to each other with the R/WL pin of dual port RAM and the DIR pin of level transferring chip as the write signal control line.Control line and dual port RAM are read in the LnOE pin conduct of microprocessor 1011
Pin links to each other.The LADDR[0:10 of microprocessor 1011] with 10 bit address bus A[0:10 of dual port RAM] L links to each other.The interruption of dual port RAM
The L pin and
Pin links to each other with the EINT9 pin with the nWAIT of microprocessor 1011.
Need to prove that the model of dual port RAM is IDT7132, the chip hardware function admirable makes the design of peripheral interface circuit 1027 become very easy.In order to prevent that two ports of same moment appearance from using the situation of same data cell simultaneously, dual port RAM hardware provides three kinds of different address contention mechanism, the i.e. busy mechanism of hardware, interrupt mechanism and token mechanism.Communication interface of the present invention uses busy mechanism of hardware and interrupt mechanism that the address competition is arbitrated.The busy mechanism of hardware, two ports of dual port RAM respectively have a BUSY pin, and when a port attempts to visit one during by the address location of another port access, corresponding BUSY pin can be put low level.Interrupt mechanism, utilize the address for 0x7FE and 0x7FF be the highest two address locations of dual port RAM as interrupt register, for example when left port when the 0x7FF unit writes data dual port RAM with right interrupt pin
Put low level, dual port RAM automatically will data the time in right output port reads the 0x7FF unit
Level is drawn high, and vice versa, utilizes interrupt mechanism can realize two data high-speed exchanges between the CPU easily.The hardware interface circuit of dual port RAM and microprocessor 1011 as shown in Figure 7.
Therefore the interrupt INT pin of dual port RAM and busy BUSY pin will be they external pull-up resistors for opening Lou output when practical application,
Pin provides exterior interrupt for microprocessor 1011,
Pin provides the insertion waiting signal for microprocessor 1011.
Microprocessor 1011 is the 3.3V supply power voltage, and directly linking to each other with the 5V level exists the unmatched situation of level, need utilize the method for level transferring chip to solve the unmatched problem of both sides' level.Level transferring chip is that SN74LVC4245 has 3.3V and 5V two overlaps independently power supply power supply, and both sides have 8 bit data mouths of a pair of symmetry, can realize the mutual commentaries on classics of 3.3V signal and 5V signal.The transmission direction of the DIR pin control data signal of SN74LVC4245, signal allowed to transmit to the 3.3V direction from 5V when the DIR pin was high level, allowed signal to transmit to the 5V direction from 3.3V when the DIR pin is low level.When microprocessor 1011 readout data bus data, the LnWE pin is high level automatically, DIR leg signal direction by dual port RAM to microprocessor 1011, LnWE is low level automatically when microprocessor 10111011 write datas, electricity DIR leg signal direction to dual port RAM, can be controlled the transmission of both sides' data-signal by microprocessor 10111011 like this.
Indicating circuit 1024 referring to Fig. 8, with 1011 unidirectional connections of microprocessor, is used to indicate the operating state of current communication module, sends indication logical signal according to the operating state of current communication module to indicating circuit 1024 by microprocessor 1011.
As shown in Figure 8, the anode of 4 LED is connected with supply voltage 3.3V, the negative electrode of 4 LED links to each other with GPG7, GPG10, GPF6, the GPF5 pin of microprocessor 1011 by the current-limiting resistance of 4 1K, the LED of 4 pins correspondence when output low level is lighted, microprocessor 1011 informs indicating circuit 1024 according to the operating state of current communication interface with init state, device and network connection state etc.
Power circuit 1025, as shown in Figure 9, adopt the 5V power supply, include mains switch and indicator light, warp can be with the low pressure difference linearity source of stable pressure AS1117AR-3.3 chip voltage stabilizing of carrying 1.5A, the 5V supply voltage is through the 2.6A fuse, by inserting the Vin input of AS1117AR-3.3 behind the capacitor filtering, AS1117AR-3.3 GND hold direct ground connection, by two continuous Vout pin output 3.3V burning voltages, the 3.3V voltage of AS1117AR-3.3 output is through the needed 3.3V stabilized power supply of generator behind the capacitor filtering and insert the anode of power supply indicator POWERRED, the negative electrode of power supply indicator POWERRED is through the grounding through resistance of 1K, for communication interface provides the power supply indication.
Reset circuit 1026, referring to Figure 10, with 1011 unidirectional connections of microprocessor, be used to the communication interface that resets, when reset circuit 1026 receives reset signal from external equipment, reset circuit 1026 sends to microprocessor 1011 with reset signal, and microprocessor 1011 restarts after receiving reset signal.
Reset circuit 1026 as shown in figure 10, MAX811 are a fairly simple chips that resets, 27 pins of No. 3 pin connecting interface circuit 1027, and the reset pin nRESET of No. 2 pin connection microprocessors 1011.When No. 3 pins received low level signal from external equipment, No. 3 pins of MAX811 sent a low level signal to microprocessor 1011, and the reset pin of microprocessor 1011 triggers reset function after receiving a low level signal.
Interface circuit 1027 referring to Figure 11, is connected with external equipment is two-way, is used for communication interface and external equipment and carries out interconnected.As shown in figure 11, interface circuit 1027 adopts the 15X2 cushion pin device of standard 2.0mm spacing, carry out exchanges data in order to external equipment and communication interface, patching device 1 pin and 2 pin is power pins, provide power supply by external equipment for communication interface, patch device 3 pin and connect the dual port RAM right-hand member to 7 pin
Pin, provide control logic mutually by control pin external equipment and dual port RAM, patching device 8 to 18 pins is address signal line, with dual port RAM right-hand member address wire A[0:10] R links to each other, provide address gating signal to provide the address signal logic by external equipment for dual port RAM, patching device 19 to 26 pins is data signal line, data wire I/O[0:7 with the dual port RAM right-hand member] R links to each other, with the external equipment exchange data information, patching device 27 pins is reset pin, link to each other with No. 3 pins of reset circuit 1026MAX811 chip, provide the reseting logic signal to drive the reset circuit 1026 of communication interface by external equipment, patching device 28 pin NC is empty pin, patching device 29 pins and 30 pins is the serial port data pin, link to each other with the RXD0 pin with the TXD0 of microprocessor 1011, carry out the serial communication swap data in order to communication interface and PC and carry out firmware upgrade.
On the imbody, embedded Ethernet based on dual port RAM provided by the invention/IP Generalized Communication Interface device, at first in the software and hardware function of back microprocessor 1011 initialization self that powers on, enter operating system by guidance code, start Ethernet/IP protocol stack boot, show the starting state of current communication interface by indicating circuit 1024.
Microprocessor 1011 is by the external equipment initialization information of image data switched circuit 1022 then, initialization information is read in Ethernet/IP protocol stack boot, in order to parameters such as configuration of IP address, input and output I/O data byte sizes, finish function of initializing, show current init state by indicating circuit 1024.After initialization finishes, Ethernet/IP protocol stack boot will start Ethernet/IP protocol stack main program and begin to handle the Ethernet/IP message, analyzing and processing is from the data message of Ethernet/IP network and external equipment, according to the Ethernet/IP protocol specification, to unpack automatically from the data message of Ethernet/IP network, and automatically packing will send to the data message of Ethernet/IP network, show the communications status of current communication interfaces and external equipment and Ethernet/IP network by indicating circuit 1024.
The present invention is in said process, microprocessor 1011 is initialization self software and hardware at first, utilize the operation of start-up code pilot operationp system, according to initialization information initialization Ethernet/IP object model, messaging parameter, scan period and peripheral ethernet circuit 1022, exchanges data circuit etc. are set, thereby finish the communication interface initialization procedure.Carry out Ethernet/IP configuration, configuration then, after by Ethernet/IP network configuration, configuration, communication interface is even connected the Ethernet/IP network, and communication interface just enters unlimited datacycle swap status afterwards.
For the device that the invention described above provides, this installs when the communication interface operation irregularity, and by indicating circuit 1024 state that shows abnormality immediately, the user is the failure judgement reason timely, can effectively investigate the problem that communication process occurs.In conjunction with circuit shown in Figure 10, when taking place, fault can send abnormal prompt, and the prompting user fixes a breakdown as early as possible.In addition, communication interface automatically replies normal operating conditions immediately after fault is got rid of, indicating circuit 1024 of the present invention, and response speed is fast, circuit is simple, and with low cost, high efficiency.
For device provided by the invention, in designing with external device communication, adopted the shared storage of dual port RAM as external equipment and communication interface microprocessor 1011, simplicity of design, exchanges data real-time height, and utilize standard to patch device as interface circuit 1027, thereby has versatility widely, communication module can be interconnected with the external equipment that meets communication module interface circuit 1027 standards arbitrarily, strengthened the practicality of communication module greatly, plug and play, the utilization ratio of device height can be realized the quick access of external equipment to the Ethernet/IP network.In the exchanges data circuit design, use level transferring chip to solve the unmatched problem of level between dual port RAM and the microprocessor 1011 as isolated component, make the microprocessor 1011 can be owing to the level mismatch problem causes hardware damage, method is simply efficient, has good level conversion effect.
In sum, compared with prior art, the invention provides a kind of universal embedded Ethernet/IP communication interface based on dual port RAM, it has versatility widely, can with satisfy interface circuit 1027 standards arbitrarily, the external equipment that promptly has the 15X2 needle interface slot of 2.00mm normal pitch carries out interconnected, plug and play, be convenient to Installation and Debugging, the operating state that in time reflects current communication interface by indicating circuit 1024, the personnel of maintaining easily carry out the failure monitoring and the investigation of device, and device recovers operate as normal automatically after fault is got rid of, and has great practical significance.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. the universal embedded Ethernet/IP communication interface based on dual port RAM is characterized in that this device comprises core board unit and bottom board unit two parts, wherein,
The core board unit:
By microprocessor and constitute with two-way SDRAM circuit that is connected of microprocessor and FLASH circuit respectively; Described core board unit is used to receive the data message of transmission and analyzing and processing Ethernet/IP Industrial Ethernet and external equipment, for the indicating circuit in the bottom board unit provides the indication logical signal, and cure system information, and provide the software support for whole device;
Bottom board unit comprises:
The core board interface circuit: bottom board unit is connected with the core board unit by the core board interface circuit, makes core board unit and bottom board unit constitute an integral body;
Ethernet circuit: be connected with the Ethernet/IP network bi-directional, be connected with the core board unit is two-way by the core board interface circuit simultaneously, by ethernet circuit, be used for the core board unit and the Ethernet/IP network carries out information interaction, exchange Ethernet/IP network data;
External data switched circuit: be connected with the core board unit is two-way by the core board interface circuit, be connected by interface circuit and external equipment are two-way simultaneously, core board unit and external equipment are communicated, the exchange external data by the external data switched circuit;
Indicating circuit: be connected with the core board unit by the core board interface circuit, provide the indication logical signal by the core board unit, indicate the operating state of current communication interface by indicating circuit, when the communication module operation irregularity, indicating circuit sends abnormal show, shows behind the abnormal restoring to recover normal;
Power circuit: be connected with the core board unit by the core board interface circuit, and be connected with external equipment, provide stabilized power supply for communication interface by power circuit through interface circuit;
Reset circuit: be connected with the core board unit by the core board interface circuit, connect external equipment through interface circuit simultaneously, provide reset function by reset circuit for communication interface, the reset command signal that reset circuit sends according to external equipment awards core board unit reseting logic signal, after reset signal is triggered, communication interface will restart;
Interface circuit: for external equipment provides the preferred circuit interface, make the communication interface can be interconnected with the external equipment that satisfies the interface circuit standard arbitrarily by interface circuit, plug and play be convenient to Installation and Debugging.
2. device as claimed in claim 1 is characterized in that,
Microprocessor in the described core board unit, the Ethernet/IP that is used to gather from ethernet circuit imports data and issues output Ethernet/IP data, collection is from the external device data of external data switched circuit and issue dateout, the reset signal that receiving reset circuit provides is finished reset function, to the operating state that indicating circuit provides the logic index signal to reflect current communication interface, initialization and executive software protocol stack are finished all software processes tasks of communication interface;
Described FLASH circuit adopts the FLASH chip to constitute, it is the program storage of communication interface, system information during the storage programming, assurance system transfer some back program information not lose, and microprocessor is by the program information and the configuration information of FLASH chip read-write communication interface;
Described SDRAM circuit adopts the SDRAM chip to constitute, and is synchronous DRAM, does not lose by constantly refreshing storage array assurance data, for communication interface provides program running space and high-speed data disposal ability;
3. device as claimed in claim 1 or 2, it is characterized in that described core board interface circuit comprises that the standard of the spacing 2.0mm of 2 groups of 36X2 and two groups of 16X2 patches device, making that core board unit and bottom board unit are two-way is connected, and constitutes an integral body on electrical characteristic and the physical characteristic.
4. device as claimed in claim 1 or 2, it is characterized in that described ethernet circuit comprises: Ethernet net controller DM9000, by two-way connection of FPDP LDATA0-LDATA15 of microprocessor in core board interface circuit and the core board unit, the TXO+ of DM9000, TXO-, RXI+, the TDP of four pins of RXI-and network filter H1102NL, TDN, RDP, the two-way connection of RDN pin, the bridge that is used for microprocessor and ethernet network swap data, the TX+ of Ethernet interface device R J45, TX-, RX+, the TXP of four pins of RX-and network filter, TXN, RXP, four two-way connections of pin of RXN, for the communication interface access network based on ethernet provides interface circuit, 3.3V power supply and earth signal pass through electric capacity, inductive circuit provides analog power and simulation earth signal for ethernet circuit.
5. device as claimed in claim 1 or 2, it is characterized in that described external data switched circuit comprises: a slice dual port RAM chip and a slice level transferring chip SN74LVC4245, dual port RAM chip model is IDT7132, a dual port RAM chip is equipped with two and overlaps independently address, data and control line, allow two independent CPUs or controller simultaneously this memory chip to be carried out the visit of randomness, shared data memory as microprocessor and external equipment, in order to the data message between exchange microprocessor and the external equipment, and provide the address contention arbitration logic by dual port RAM hardware, avoid owing to the error in data problem that the same address location data write of dual port RAM situation is taken place cause; Dual port RAM chip left end address bus is connected with left end control bus and microprocessor are unidirectional, provide address and logic control signal by microprocessor, for avoiding the unmatched situation of level, the two-way connection of B end data bus of the left end data/address bus of dual port RAM chip and level transferring chip SN74LVC4245, the A end data bus of level transferring chip SN74LVC4245 is connected with the data/address bus of microprocessor is two-way, in order to swap data between dual port RAM chip and the microprocessor, the nGCS5 of microprocessor and LnWE pin select pin with the sheet of level transferring chip SN74LVC4245 respectively
DIR links to each other with the direction pin, and in order to the work-based logic of control level conversion chip, the address bus of dual port RAM right-hand member, data/address bus and control bus are interconnected by interface circuit and external equipment, provide address, data and logic control signal by external equipment.
6. device as claimed in claim 1 or 2, it is characterized in that described indicating circuit comprises: the LED lamp of 4 parallel connections, each paths of LEDs lamp is by unidirectional connection of microprocessor in current-limiting resistance and core board interface circuit and the core board unit, provide logical signal by microprocessor, the working condition that reflects current communication interface, during the communication interface operation irregularity, LED lamp display abnormality, the LED lamp recovers normal demonstration after fault is got rid of.
7. described device as claimed in claim 1 or 2, it is characterized in that described power circuit comprises: adopt the 5V power supply, warp can be with the low pressure difference linearity source of stable pressure AS1117AR-3.3 chip voltage stabilizing of carrying 1.5A, the 5V supply voltage is through the 2.6A fuse, by inserting the Vin input of AS1117AR-3.3 behind the capacitor filtering, the GND of AS1117AR-3.3 holds direct ground connection, by two continuous Vout pin output 3.3V burning voltages, the 3.3V voltage of AS1117AR-3.3 output is through the needed 3.3V stabilized power supply of generator behind the capacitor filtering and insert the anode of power supply indicator POWERRED, the negative electrode of power supply indicator POWERRED is through the grounding through resistance of 1K, for communication interface provides the power supply indication.
8. device as claimed in claim 1 or 2, it is characterized in that described reset circuit comprises: chip MAX811 resets, the input of chip MAX811 of resetting links to each other with the interface circuit unit, provide the reseting logic signal by external equipment, the reset pin nRESET pin of output by the microprocessor in core board interface circuit and the core board unit of chip MAX811 of resetting links to each other, provides reset capability for microprocessor when external equipment triggering reseting logic signal.
9. device as claimed in claim 5, it is characterized in that described interface circuit comprises: the 15X2 cushion pin device of standard 2.0mm spacing, carry out exchanges data in order to external equipment and communication interface, patching device 1 pin and 2 pin is power pins, provide power supply by external equipment for communication interface, patch device 3 pin and be the control pin to 7 pin, external equipment provides control logic mutually by control pin and communication interface, patching device 8 to 18 pins is address signal line, provide dual port RAM right-hand member address bus address signal by external equipment, patching device 19 to 26 pins is data signal line, external equipment and dual port RAM right-hand member data/address bus exchange data information, patching device 27 pins is reset pin, provide the reseting logic signal to drive the reset circuit of communication interface by external equipment, patching device 28 pins is empty pin, patching device 29 and 30 pins is the serial port data pin, serial port pin by the microprocessor in core board interface circuit and the core board unit links to each other, and carries out the serial communication swap data in order to communication interface and PC and carries out firmware upgrade.
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| CN201110161643.0A CN102255975B (en) | 2011-06-16 | 2011-06-16 | Dual-port-random access memory (RAM)-based embedded common Ethernet/Internet protocol (IP) communication interface device |
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| CN103064311A (en) * | 2012-12-12 | 2013-04-24 | 南充市鹰派科技有限公司 | Electronic warfare system |
| CN103293995A (en) * | 2013-06-09 | 2013-09-11 | 南车株洲电力机车研究所有限公司 | Field bus communication module based on microcontroller |
| CN104539273A (en) * | 2014-12-06 | 2015-04-22 | 佛山市雅洁源科技股份有限公司 | Plug wire control mainboard structure for direct drinking water device |
| CN105867190A (en) * | 2016-04-15 | 2016-08-17 | 北京博瑞爱飞科技发展有限公司 | Interface system and interface control method of unmanned aerial vehicle |
| CN113079480A (en) * | 2021-04-12 | 2021-07-06 | 广东轻工职业技术学院 | Wireless communication interface device |
| CN114402568A (en) * | 2019-08-02 | 2022-04-26 | 欧姆龙株式会社 | Network system, information processing apparatus, and information processing method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103064311A (en) * | 2012-12-12 | 2013-04-24 | 南充市鹰派科技有限公司 | Electronic warfare system |
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| CN103293995B (en) * | 2013-06-09 | 2016-01-20 | 南车株洲电力机车研究所有限公司 | Based on the fieldbus communications module of microcontroller |
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| CN105867190A (en) * | 2016-04-15 | 2016-08-17 | 北京博瑞爱飞科技发展有限公司 | Interface system and interface control method of unmanned aerial vehicle |
| CN114402568A (en) * | 2019-08-02 | 2022-04-26 | 欧姆龙株式会社 | Network system, information processing apparatus, and information processing method |
| CN113079480A (en) * | 2021-04-12 | 2021-07-06 | 广东轻工职业技术学院 | Wireless communication interface device |
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| CN102255975B (en) | 2014-05-21 |
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