CN107396009A - Pulse frequency modulated type image sensor circuit and its processing method - Google Patents

Pulse frequency modulated type image sensor circuit and its processing method Download PDF

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CN107396009A
CN107396009A CN201710743790.6A CN201710743790A CN107396009A CN 107396009 A CN107396009 A CN 107396009A CN 201710743790 A CN201710743790 A CN 201710743790A CN 107396009 A CN107396009 A CN 107396009A
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input
fixed reference
reference potential
switch
integral node
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CN107396009B (en
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王向展
吴强
陈同少
刘洋
于奇
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

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  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The present invention relates to integrated circuit technique.The present invention solves the problems, such as complicated during existing PFM types imaging sensor high accuracy, there is provided a kind of pulse frequency modulated type image sensor circuit and its processing method, its technical scheme can be summarized as：Pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, comparator, first integral node reset switch, counter, circuit output end, ground wire, external control signal input, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential input.The invention has the advantages that the difficulty and complexity of circuit design are reduced, suitable for pulse frequency modulated type imaging sensor.

Description

Pulse frequency modulated type image sensor circuit and its processing method
Technical field
The present invention relates to the process circuit of integrated circuit technique, the more particularly to imaging sensor of pulse frequency modulated type.
Background technology
The advantages that cmos image sensor is with its high integration, low-power consumption and low cost, be widely used to space remote sensing, The traditional field such as industrial machine vision and commercial digital shooting.Exemplary CMOS image sensor is entered in the form of voltage or electric current The output of row signal, and wherein CMOS active pixel sensor is with more superior combination property and in occupation of main flow, its course of work It is as follows：First, photodetector produces corresponding photoelectric current to the luminous intensity of environment；Then, photoelectric current is carried out to integrating capacitor Charging (or electric discharge) integration obtains corresponding integral voltage；Then, integral voltage has source class to go to control output voltage by control Or electric current；Finally, quantization output is carried out to output voltage on last stage or electric current by subsequent process circuit.Dynamic range (DR, One of Dynamic Range) important indicator as cmos image sensor performance, it is defined as follows：Dynamic range is image The ratio between the maximum accessible signal of sensor and minimum accessible signal amplitude.Because the capacitance of integrating capacitor is limited, when When integration current caused by photodetector is more than a certain fixed value, integrating capacitor reaches saturation state, i.e., can not continue to more Big optical signal produces correct output result, in addition, with the development of ic manufacturing technology, the work of IC manufacturing Skill size is less and less, and the supply voltage on whole integrated circuit is more and more lower, the scope of voltage variable in integrating capacitor It will reduce with the renewal of technique, cause dynamic range to reduce, be unfavorable for the performance enhancement of whole cmos image sensor.
With the development of cmos image sensor technology and perfect, many designers are gradually by cmos image sensor application Into numerous sciemtifec and technical spheres, but design of the different application environments to cmos image sensor has different index requests. For example, in emerging artificial vision field, in order to detect the optical signal under natural environment, it is necessary to cmos image sensor have compared with Big dynamic range.The dynamic range of light can reach 140dB under natural environment state, and most of traditional voltage-type or Person's current-mode CMOS imaging sensor only has 60~70dB linear response range, therefore Larger Dynamic scope is referred to as cmos image biography The problem of a urgent need to resolve in sensor research field.It is currently associated in order to realize the cmos image sensor of Larger Dynamic scope Researcher mainly proposes two ways to increase the dynamic range of cmos image sensor.One kind is to change conventional voltage type Or the linear response of current-mode CMOS imaging sensor is logarithmic response, and then increase dynamic range, but this pattern Cmos image sensor is because it is under the mode of operation of logarithm, it is difficult to significantly eliminate fixed pattern noise (FPN, Fixed Pattern Noise), the severe exacerbation of final output image quality is caused, such a technology needs further perfect；Other one Kind is exported using impulse modulation (PM, Pulse Modulation) principle, because it does not recycle magnitude of voltage or electric current Value characterizes the numerical value of useful signal, thus its be not present conventional voltage type or current-mode CMOS imaging sensor faced it is dynamic The problem of state scope is limited.
What PM types cmos image sensor can summarize is divided into pulse width modulation type (PWM, Pulse Width Modulation) and pulse frequency modulated type (PFM, Pulse Frequency Modulation) two classes, it is typical basic As shown in Figure 1, 2, Reset is reseting controling signal to pixel unit circuit structure in wherein Fig. 1, Vint be integral node voltage and Cint is integral node electric capacity, and Vref is the reference voltage of comparator, and Vo is output signal；Vint is integral node electricity in Fig. 2 Pressure and Cint are integral node electric capacity, and Vref is the reference voltage of comparator, and Vo is output signal.PWM types cmos image senses Device pixel cell generally comprises a photodetector Det1, an integrating capacitor Cint and a comparator, PWM types CMOS figures As sensor is to be visited with detecting the time difference (i.e. the time of integration) between reset signal and comparator energizing signal to characterize photoelectricity The size that device Det1 produces electric current is surveyed, the intensity of light is bigger, and electric current caused by photodetector Det1 is bigger, PWM type pixels The time difference of output is smaller, and vice versa；PFM type cmos image sensor pixel cells generally comprise a photodetector Det1, an integrating capacitor Cint, a comparator and a delay unit, PFM type cmos image sensors are defeated to detect Go out to hold the frequency of digital pulse signal to characterize the size that photodetector Det1 produces electric current, whenever on integrating capacitor Cint When integral voltage reaches the value of datum, the output state of comparator carries out upset and produces a pulse, and the intensity of light is bigger, Electric current caused by photodetector Det1 is bigger, and the output pulse frequency of PFM type pixels is higher, and vice versa.Due to PFM type figures As sensor using the pulse number that comparator exports as quantized result characterizes the light intensity of actual environment, and PFM types image passes Sensor can not possibly always export integer pulse just within the fixed time of integration, in the latter stage of the fixed time of integration, integration Residual voltage often occurs on node (output of non-trigger comparator is overturn).Especially in the strong environment of dim light, PFM types The pulse number of imaging sensor output is less, in some instances it may even be possible to the situation of several pulses occurs, the residual voltage meeting now occurred Larger deviation is caused, is unfavorable for being ultimately imaged under low photoenvironment.
(document 1, H.Kayahan et al. " the A new digital readout integrated such as H.Kayahan circuit(DROIC)with pixel parallel A/D conversion and reduced quantization Noise, " Infrared Physics＆Technology, vol.63, pp.125-132, Mar.2014.) one kind is proposed to residual The method that remaining voltage extend counting, this method are to quantify the period by additionally increasing to carry out the amount to residual voltage Change, and then increase the signal to noise ratio of output result.Its work schedule is as shown in figure 3, wherein CLKint and CLKres is respectively to integrate Period and the control signal of extension of time section, high level are effective；Vint and Vcom is respectively integral node electric capacity and comparator The voltage of output end, specific works mode are：In integration time period TINTPeriod, the circuit in the program is the same as traditional PFM structures one Sample, carry out counting to get X positions weight quantization data by the number for overturning comparator output end voltage；In back to back extension Period TRESIDUEPeriod, continue to keep the charging (or electric discharge) of integral node electric capacity, until integration time period TINTAt the end of product The residual voltage value divided on electric capacity is electrically charged (or electric discharge) and arrives comparator fixed reference potential value, while using fixed clock CLK Y positions weight quantization data are obtained to drive same counter to carry out counting quantization to required time；Finally, periphery auxiliary electricity is utilized Road and the composite calulation that final output data are completed according to calculation formula, its calculation formula are as follows：
Wherein NcountIt is by integration time period TINTThe X positions weight quantization data inside obtained are calculated, TRESIDUEBe by Y positions weight quantization data combination fixed clock CLK computation of Period is drawn.This method adds additional an extension of time section TRESIDUECarry out extension counting, it is desirable to provide extra control signal, while the time of a part is also slatterned, drag slowly imaging Speed；On the other hand, two period (i.e. integration time period TINTWith extension of time section TRESIDUE) quantized data need according to Above-mentioned formula synthesizes final output result, therefore adds additional the peripheral auxiliary circuits for being used to synthesize final data, and it is not Extra area is only taken up, and increases the complexity and difficulty of system-on-chip designs.
(document 2, Shahbaz Abbasi et al. " the A PFM Based Digital such as Shahbaz Abbasi Pixel with Off-Pixel Residue Measurement for Small Pitch FPAs".IEEE Transactions on Circuits and Systems II:Express Briefs.Volume:PP,Issue:99, 2016.) a kind of signal to noise ratio (SNR, Signal to Noise Rate) Enhancement Method suitable for small-sized pixel is proposed, should Method is by adding column analog-to-digital converter (ADC, Analog to Digital Converter) in pixel outside to realize pair The quantization of residual voltage.Its specific works mode is：The highest significant position of traditional PFM structure divisions quantizer input signal electric current (MSB, Most Significant Bit), column analog-to-digital converter structure division to the residual voltage that PFM is exported quantify To least significant bit (LSB, Least Significant Bit), finally by subsequent process circuit by MSB data and LSB numbers Final quantization output result is obtained according to synthesis.Although this method does not increase extra circuit inside pixel, it is in each column Analog-digital converter and register (being used to store quantized result of the analog-digital converter to residual voltage) are added in pixel, it is natural Extra chip area can be taken；This method is all additionally required a peripheral auxiliary circuits as the method in document 1 above To carry out final Data Synthesis, area is not only accounted for, while also can be that comparison is high to the design requirement of its speed, is added whole The design difficulty of individual system.
(document 3, Y.Chen et al. " the A New Wide Dynamic Range CMOS Pulse- such as Y.Chen Frequency-Modulation Digital Image Sensor with In-Pixel Variable Reference Voltage " 51st Midwest Symposium on Circuits and Systems, pp.129-132, Aug.2008) carry A kind of method for becoming reference voltage is gone out, this method is the reference voltage input terminal introducing one in pixel internal comparator with reference to electricity Hold Cref to adjust the reference voltage of comparator, pass through the adjustment circuit of control of Electric potentials one (the i.e. charge/discharge electricity of comparator output terminal Road and a phase inverter, charge/discharge circuit is mainly formed by PMOS switch M1 and nmos switch M2 in accompanying drawing 4), produce one at any time Between increase and the increased reference voltage of amplitude, its concrete structure is as shown in Figure 4.To small photogenerated current, due to adjustment circuit pair Reference capacitance Cref charging interval is longer, and the reference voltage of comparator higher (with the resetting voltage of integral node electric capacity more It is close), integral node voltage need to only change less scope can trigger comparator output end overturn, therefore can increase The upset number of comparator, reduce influence of the residual voltage to final output result, while widened the dynamic range of pixel, increase The signal to noise ratio of output is added.But this method has similar reseting procedure with traditional PFM types imaging sensor, i.e. comparator exports Terminal voltage carries out once inside out and integral node once will be resetted.And integral node electric capacity, which reset, to be needed necessarily Time.Integral node still has photogenerated current inflow within this time of reset, and the electric charge that integrating capacitor is flowed into during this can It is eliminated, in turn results in certain error, therefore carry out reset to integral node electric capacity more times to cause final output knot There is larger distortion in fruit；On the other hand, the variable reference voltage in this method passes through its internal transistor by charge/discharge circuit Drain terminal electric current carry out charge/discharge and adjust, therefore variable reference voltage is not an accurately linear ramp, by it as joining When examining voltage to carry out the quantization of signal, the poor linearity of its output result.
The content of the invention
Present invention aim to address it is complicated during current PFM types imaging sensor high accuracy the problem of, there is provided it is a kind of Pulse frequency modulated type image sensor circuit and its processing method.
The present invention solves its technical problem, and the technical scheme of use is pulse frequency modulated type image sensor circuit, bag Include power input, photodetector, integral node electric capacity, comparator, first integral node reset switch, counter, circuit Output end and ground wire, it is characterised in that also including external control signal input, one group of gating controlling switch, logic module and One group of fixed reference potential input, the positive pole of the photodetector are connected with ground wire, and its negative pole passes through first integral node Reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetector it is negative Pole connects；It is each to gate controlling switch and each fixed reference in one group of gating controlling switch and one group of fixed reference potential end Voltage input end corresponds, and the negative-phase input of comparator and the negative pole of photodetector connect, its normal phase input end difference Connected by each gating controlling switch with corresponding fixed reference potential input, the output end of comparator and counter Counting input end connects；The reset terminal of the counter is connected with external control signal input, and its integral node resets control The control terminal that end switchs with first integral node reset is connected, and its output end is and defeated with logic module as circuit output end Enter end connection, each output end of logic module with it is each gating controlling switch correspond, each output end respectively with corresponding gating The control terminal connection of controlling switch；
In one group of fixed reference potential end, each fixed reference potential end input fixed reference potential and its His fixed reference potential of fixed reference potential input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers one Pulse, make first integral node reset switch conduction, wherein, N is the positive integer more than or equal to 2；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, Remaining shut-off；
When external control signal input input reseting controling signal makes counter resets, the integral node of counter is answered Position control terminal triggers a pulse, makes first integral node reset switch conduction, and the output end of unison counter exports initially again Position signal；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports When adding L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, first gating is returned to Controlling switch carries out circulation conducting, when the count value that the output end of counter exports is mN or initial reset signal, then logic Module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is positive integer more than or equal to 1, m be more than Positive integer equal to 1.
Specifically, symmetric form comparator or dynamic latch type of the comparator for two stage comparator or based on OTA compare Device or controllable Schmidt trigger.
Further, the first integral node reset switch is PMOS switch or nmos switch or cmos switch or bootstrapping Switch.
Specifically, the fixed reference potential value of each fixed reference potential end input is in integral node and resets electricity Being depressed into the minimum of the normal phase input end of comparator can be between input voltage, the fixed reference potential of each fixed reference potential end input Order arranges, and is increasedd or decreased successively according to fixed variable quantity.
Further, in one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
Pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, Comparator, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control Signal input part, one group of gating controlling switch, logic module and one group of fixed reference potential input, the photodetector Positive pole is connected with ground wire, and its negative pole is switched by first integral node reset and is connected with power input, integral node electric capacity One end is connected with ground wire, the negative pole connection of the other end and photodetector；One group of gating controlling switch and one group of fixation ginseng Examine in voltage end, each controlling switch that gates corresponds with each fixed reference potential input, the negative-phase input of comparator with The negative pole connection of photodetector, its normal phase input end pass through each gating controlling switch and corresponding fixed reference electricity respectively Input connection is pressed, the output end of comparator and the counting input end of counter connect；The reset terminal of the counter and outside Control signal input is connected, and its integral node reseting controling end is connected with the control terminal that first integral node reset switchs, its Output end is connected as circuit output end, and with the input of logic module, and each output end of logic module controls with each gating Switch corresponds, and control terminal of each output end respectively with corresponding gating controlling switch connects, external control signal input It is connected with the RESET input of logic module；
In one group of fixed reference potential end, each fixed reference potential end input fixed reference potential and its His fixed reference potential of fixed reference potential input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers one Pulse, make first integral node reset switch conduction, wherein, N is the positive integer more than or equal to 2；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, Remaining shut-off；
When external control signal input input reseting controling signal makes counter resets, the integral node of counter is answered Position control terminal triggers a pulse, makes first integral node reset switch conduction；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports When adding L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, first gating is returned to Controlling switch carries out circulation conducting, makes counting when the count value that the output end of counter exports receives for mN or the RESET input During the reseting controling signal that device resets, then logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
Specifically, symmetric form comparator or dynamic latch type of the comparator for two stage comparator or based on OTA compare Device or controllable Schmidt trigger.
Further, the first integral node reset switch is PMOS switch or nmos switch or cmos switch or bootstrapping Switch.
Specifically, the fixed reference potential value of each fixed reference potential end input is in integral node and resets electricity Being depressed into the minimum of the normal phase input end of comparator can be between input voltage, the fixed reference potential of each fixed reference potential end input Order arranges, and is increasedd or decreased successively according to fixed variable quantity.
Further, in one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
Pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, Comparator, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control Signal input part, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential are defeated Enter end, the positive pole of the photodetector is connected with ground wire, and its negative pole is switched and second by first integral node reset respectively Integral node reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, and the other end is visited with photoelectricity Survey the negative pole connection of device；In one group of gating controlling switch and one group of fixed reference potential end, it is each gate controlling switch with it is each Fixed reference potential input corresponds, and the negative-phase input of comparator and the negative pole of photodetector connect, and its positive is defeated Enter end respectively by each gating controlling switch connected with corresponding fixed reference potential input, the output end of comparator and The counting input end connection of counter；The reset terminal of the counter is connected with external control signal input, its integral node The control terminal that reseting controling end switchs with first integral node reset is connected, and its output end is as circuit output end, and and logic The input connection of module, the control terminal of the second integral node reset switch are connected with external control signal input, patrolled Each output end and each gating controlling switch for collecting module correspond, the control with corresponding gating controlling switch respectively of each output end End connection processed；
In one group of fixed reference potential end, each fixed reference potential end input fixed reference potential and its His fixed reference potential of fixed reference potential input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers one Pulse, make first integral node reset switch conduction；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, Remaining shut-off；
When external control signal input input reseting controling signal makes counter resets, second integral node can be made Reset switch turns on, the output end output initial reset signal of unison counter；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports When adding L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, first gating is returned to Controlling switch carries out circulation conducting, when the count value that the output end of counter exports is mN or initial reset signal, then logic Module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is positive integer more than or equal to 1, m be more than Positive integer equal to 1.
Specifically, symmetric form comparator or dynamic latch type of the comparator for two stage comparator or based on OTA compare Device or controllable Schmidt trigger.
Further, the first integral node reset switch and/or second integral node reset switch are PMOS switch Or nmos switch or cmos switch or bootstrapped switch.
Specifically, the fixed reference potential value of each fixed reference potential end input is in integral node and resets electricity Being depressed into the minimum of the normal phase input end of comparator can be between input voltage, the fixed reference potential of each fixed reference potential end input Order arranges, and is increasedd or decreased successively according to fixed variable quantity.
Further, in one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N. Pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, comparator, One integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also inputted including external control signal End, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential input, institute The positive pole for stating photodetector is connected with ground wire, and its negative pole is switched respectively by first integral node reset and second integral node Reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetector it is negative Pole connects；It is each to gate controlling switch and each fixed reference in one group of gating controlling switch and one group of fixed reference potential end Voltage input end corresponds, and the negative-phase input of comparator and the negative pole of photodetector connect, its normal phase input end difference Connected by each gating controlling switch with corresponding fixed reference potential input, the output end of comparator and counter Counting input end connects；The reset terminal of the counter is connected with external control signal input, and its integral node resets control The control terminal that end switchs with first integral node reset is connected, and its output end is and defeated with logic module as circuit output end Enter end connection, the control terminal of the second integral node reset switch is connected with external control signal input, logic module Each output end corresponds with each gating controlling switch, and control terminal of each output end respectively with corresponding gating controlling switch connects Connect, the RESET input connection of external control signal input and logic module；
In one group of fixed reference potential end, each fixed reference potential end input fixed reference potential and its His fixed reference potential of fixed reference potential input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers one Pulse, make first integral node reset switch conduction；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, Remaining shut-off；
When external control signal input input reseting controling signal makes counter resets, second integral node can be made Reset switch turns on；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports When adding L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, first gating is returned to Controlling switch carries out circulation conducting, makes counting when the count value that the output end of counter exports receives for mN or the RESET input During the reseting controling signal that device resets, then logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
Specifically, symmetric form comparator or dynamic latch type of the comparator for two stage comparator or based on OTA compare Device or controllable Schmidt trigger.
Further, the first integral node reset switch and/or second integral node reset switch are PMOS switch Or nmos switch or cmos switch or bootstrapped switch.
Specifically, the fixed reference potential value of each fixed reference potential end input is in integral node and resets electricity Being depressed into the minimum of the normal phase input end of comparator can be between input voltage, the fixed reference potential of each fixed reference potential end input Order arranges, and is increasedd or decreased successively according to fixed variable quantity.
Further, in one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N. The processing method of pulse frequency modulated type image sensor circuit, applied to above-mentioned pulse frequency modulated type imaging sensor electricity Road, it is characterised in that comprise the following steps：
Step 1, external control signal input input reseting controling signal, integral node electric capacity reset to reset level, Counter is resetted according to the reseting controling signal inputted, and logic module resets, and controls first gating controlling switch to lead It is logical, remaining closing；
Step 2, the reseting controling signal of input disconnect integral node electric capacity and power input, start counting up；
Step 3, in the presence of photodetector, the voltage on integral node electric capacity changes, when the voltage with work as When the fixed reference potential of preceding conducting is equal, the output voltage of comparator is overturn, into step 4；
Step 4, the output count value of counter add L, the current gating controlling switch shut-off of logic module control, simultaneously turn on Next gating controlling switch, returns to step 3；
Step 5, when the count value of counter is mN, the integral node reseting controling end of counter exports a pulse, Make the switch S0 conductings of first integral node reset, integral node electric capacity is resetted, and logic module resets, and controls first Controlling switch conducting is gated, remaining closing, returns to step 3.
The invention has the advantages that pass through above-mentioned pulse frequency modulated type image sensor circuit, it can be seen that use Change the reference voltage of the normal phase input end input of comparator, can ensure not increasing the same of integral node electric capacity number of resets When, the output of comparator is more frequently overturn, not only reduce the residual voltage on integral node electric capacity, slow down residual Image quality caused by remaining voltage is degenerated, while avoids complicated peripheral auxiliary circuits to synthesize final output data, is dropped The low difficulty and complexity of circuit design.
Brief description of the drawings
Fig. 1 is the base pixel unit cellular construction schematic diagram of PWM type imaging sensors；
Fig. 2 is the base pixel unit cellular construction schematic diagram of PFM type imaging sensors；
Fig. 3 is the work schedule schematic diagram of the extensometer quantification circuit described in document 1；
Fig. 4 is the structural representation for becoming reference voltage circuit described in document 3；
Fig. 5 is the structural representation of the first pulse frequency modulated type image sensor circuit in the embodiment of the present invention；
Fig. 6 is the structural representation of second of pulse frequency modulated type image sensor circuit in the embodiment of the present invention；
Fig. 7 is the structural representation of the third pulse frequency modulated type image sensor circuit in the embodiment of the present invention；
Fig. 8 is the structural representation of the 4th kind of pulse frequency modulated type image sensor circuit in the embodiment of the present invention；
Structure when Fig. 9 is the third pulse frequency modulated type image sensor circuit concrete example in the embodiment of the present invention Schematic diagram；
Figure 10 is the work schedule and output result schematic diagram of pulse frequency modulated type image sensor circuit in Fig. 9；
Wherein, Vint is integral node voltage, and Cint is integral node electric capacity, and Vref is the reference voltage of comparator, Vo For output signal, S0 switchs for first integral node reset, and Det1 is photodetector, and M1 is PMOS switch, and M2 opens for NMOS Close, M1 and M2 composition charge/discharge circuits, Cref is reference capacitance, and CLKint is the control signal of integration time period, and CLKres is The control signal of extension of time section, Vcom are the voltage of comparator output terminal, and CLK is fixed clock, and Sr is second integral node Reset switch, Reset are the reseting controling signal of external control signal input input, and Vc1 is the first fixed reference potential, Vc2 is the second fixed reference potential, and Vc3 is the 3rd fixed reference potential, and VcN is N fixed reference potentials, and Sc1 is the first choosing Logical controlling switch, Sc2 are the second gating controlling switch, and Sc3 is the 3rd gating controlling switch, and ScN is that N gates controlling switch, VCC is power input, and Vvref is the voltage of the reference voltage terminal voltage, i.e. normal phase input end of comparator, and Vcint is integration Voltage on electric capacity Cint, Vs0 switch the voltage in S0 control terminal, OUT0, OUT1 and OUT2 for first integral node reset The signal of three output line output respectively in the output end of 3 digit counters.
Embodiment
Below in conjunction with the accompanying drawings and embodiment, technical scheme is described in detail.
The first pulse frequency modulated type image sensor circuit of the present invention, including power input, photoelectricity are visited Survey device, integral node electric capacity, comparator, first integral node reset switch, counter, circuit output end, ground wire, outside control Signal input part, one group of gating controlling switch, logic module and one group of fixed reference potential input, the positive pole of photodetector It is connected with ground wire, its negative pole is switched by first integral node reset and is connected with power input, one end of integral node electric capacity It is connected with ground wire, the negative pole connection of the other end and photodetector；One group of gating controlling switch and one group of fixed reference potential end In, each controlling switch that gates corresponds with each fixed reference potential input, the negative-phase input of comparator and photodetection The negative pole connection of device, its normal phase input end pass through each gating controlling switch and corresponding fixed reference potential input respectively Connection, the output end of comparator and the counting input end of counter connect；The reset terminal of counter inputs with external control signal End connection, its integral node reseting controling end are connected with the control terminal that first integral node reset switchs, and its output end is as electricity Road output end, and be connected with the input of logic module, each output end of logic module corresponds with each gating controlling switch, Control terminal of each output end respectively with corresponding gating controlling switch connects；Here, in one group of fixed reference potential end, each The fixed reference potential of fixed reference potential end input is all different from the fixed reference potential of other fixed reference potentials input；Meter In number device, its counting input end often inputs counting input end and often inputs N number of pulse, and its integral node reseting controling end triggers one Individual pulse, make first integral node reset switch conduction, wherein, N is the positive integer more than or equal to 2；Each gating controlling switch by The control of logic module, synchronization only have a gating controlling switch conducting, remaining shut-off；When external control signal input When input reseting controling signal makes counter resets, the integral node reseting controling end of counter triggers a pulse, makes first Integral node reset switch turns on, the output end output initial reset signal of unison counter；Logic module controls for each gating Switch is ranked up, when the count value that the output end of detection counter exports adds L, the next gating controlling switch of sequential selection Conducting, if without next gating controlling switch, return to first gating controlling switch and carry out circulation conducting, it is defeated when counter When the count value for going out end output is mN or initial reset signal, then logic module is returned directly to first gating controlling switch progress Circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
Second of pulse frequency modulated type image sensor circuit of the present invention, including power input, photoelectricity are visited Survey device, integral node electric capacity, comparator, first integral node reset switch, counter, circuit output end, ground wire, outside control Signal input part, one group of gating controlling switch, logic module and one group of fixed reference potential input, the positive pole of photodetector It is connected with ground wire, its negative pole is switched by first integral node reset and is connected with power input, one end of integral node electric capacity It is connected with ground wire, the negative pole connection of the other end and photodetector；One group of gating controlling switch and one group of fixed reference potential end In, each controlling switch that gates corresponds with each fixed reference potential input, the negative-phase input of comparator and photodetection The negative pole connection of device, its normal phase input end pass through each gating controlling switch and corresponding fixed reference potential input respectively Connection, the output end of comparator and the counting input end of counter connect；The reset terminal of counter inputs with external control signal End connection, its integral node reseting controling end are connected with the control terminal that first integral node reset switchs, and its output end is as electricity Road output end, and be connected with the input of logic module, each output end of logic module corresponds with each gating controlling switch, The control terminal connection with corresponding gating controlling switch respectively of each output end, external control signal input and logic module are answered Position input connection；Here, in one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input It is all different from the fixed reference potential of other fixed reference potentials input；In counter, its counting input end often inputs N number of arteries and veins Punching, its integral node reseting controling end i.e. trigger a pulse, make first integral node reset switch conduction, wherein, N be more than Positive integer equal to 2；Each gating controlling switch is controlled by logic module, and synchronization, which only has a gating controlling switch, leads It is logical, remaining shut-off；When external control signal input input reseting controling signal makes counter resets, the integration section of counter Point reseting controling end triggers a pulse, makes first integral node reset switch conduction；Logic module is each gating controlling switch It is ranked up, when the count value that the output end of detection counter exports adds L, the next gating controlling switch of sequential selection is led It is logical, if without next gating controlling switch, return to first gating controlling switch and carry out circulation conducting, when the output of counter When the count value of end output is mN or the RESET input receives the reseting controling signal for making counter resets, then logic module is straight Take back to first gating controlling switch and carry out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is more than or equal to 1 Positive integer.
The third pulse frequency modulated type image sensor circuit of the present invention, including power input, photoelectricity are visited Survey device, integral node electric capacity, comparator, first integral node reset switch, counter, circuit output end, ground wire, outside control Signal input part, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential are defeated Enter end, the positive pole of photodetector is connected with ground wire, and its negative pole is switched respectively by first integral node reset and second integral Node reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetector Negative pole connection；It is each to gate controlling switch and each fixation in one group of gating controlling switch and one group of fixed reference potential end Reference voltage input terminal corresponds, and the negative-phase input of comparator and the negative pole of photodetector connect, its normal phase input end Connected respectively by each gating controlling switch with corresponding fixed reference potential input, the output end of comparator and counting The counting input end connection of device；The reset terminal of counter is connected with external control signal input, and its integral node resets control The control terminal that end switchs with first integral node reset is connected, and its output end is and defeated with logic module as circuit output end Enter end connection, the control terminal of the second integral node reset switch is connected with external control signal input, logic module Each output end corresponds with each gating controlling switch, and control terminal of each output end respectively with corresponding gating controlling switch connects Connect；Here, in one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input is solid with other The fixed reference potential for determining reference voltage input is different；In counter, its counting input end often inputs N number of pulse, and it integrates section Point reseting controling end triggers a pulse, makes first integral node reset switch conduction；Each gating controlling switch is by logic mould The control of block, synchronization only have a gating controlling switch conducting, remaining shut-off；When the input of external control signal input is multiple Position control signal is when making counter resets, can make second integral node reset switch conduction, and the output end of unison counter is defeated Go out initial reset signal；Logic module is ranked up for each gating controlling switch, when the meter that the output end of detection counter exports When numerical value adds L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, first is returned to Gating controlling switch carries out circulation conducting, when the count value that the output end of counter exports is mN or initial reset signal, then Logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is Positive integer more than or equal to 1.
4th kind of pulse frequency modulated type image sensor circuit of the present invention, including power input, photoelectricity are visited Survey device, integral node electric capacity, comparator, first integral node reset switch, counter, circuit output end, ground wire, outside control Signal input part, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential are defeated Enter end, the positive pole of photodetector is connected with ground wire, and its negative pole is switched respectively by first integral node reset and second integral Node reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetector Negative pole connection；It is each to gate controlling switch and each fixed reference in one group of gating controlling switch and one group of fixed reference potential end Voltage input end corresponds, and the negative-phase input of comparator and the negative pole of photodetector connect, its normal phase input end difference Connected by each gating controlling switch with corresponding fixed reference potential input, the output end of comparator and counter Counting input end connects；The reset terminal of counter is connected with external control signal input, its integral node reseting controling end with First integral node reset switch control terminal connection, its output end as circuit output end, and with the input of logic module Connection, the control terminal of second integral node reset switch are connected with external control signal input, logic module it is each defeated Go out end to correspond with each gating controlling switch, control terminal of each output end respectively with corresponding gating controlling switch connects, outside The RESET input of portion's control signal input and logic module connects；Here, in one group of fixed reference potential end, each is solid The fixed reference potential for determining reference voltage end input is all different from the fixed reference potential of other fixed reference potentials input；Count In device, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers a pulse, makes first integral Node reset switch conduction；Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch Conducting, remaining shut-off；When external control signal input input reseting controling signal makes counter resets, the second product can be made Partial node reset switch turns on；Logic module is ranked up for each gating controlling switch, when the output end of detection counter exports Count value when adding L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return to the One gating controlling switch carries out circulation conducting, when the count value that the output end of counter exports receives for mN or the RESET input During to the reseting controling signal for making counter resets, then logic module is returned directly to first gating controlling switch and carries out circulation and lead It is logical, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
Embodiment
The first pulse frequency modulated type image sensor circuit in the embodiment of the present invention, its structural representation is referring to figure 5, including power input VCC, photodetector Det1, integral node electric capacity Cint, comparator, first integral node reset open Close S0, counter, circuit output end, ground wire, external control signal input, one group of gating controlling switch (including the first gating Controlling switch Sc1, the second gating controlling switch Sc2 ..., N gatings controlling switch ScN), logic module and one group of fixation ginseng Voltage input end is examined, photodetector Det1 positive pole is connected with ground wire, and its negative pole switchs S0 by first integral node reset It is connected with power input VCC, integral node electric capacity Cint one end is connected with ground wire, and the other end is with photodetector Det1's Negative pole connects；It is each to gate controlling switch and each fixed reference electricity in one group of gating controlling switch and one group of fixed reference potential end Input is pressed to correspond, the negative-phase input of comparator is connected with photodetector Det1 negative pole, its normal phase input end point Do not connected by each gating controlling switch with corresponding fixed reference potential input, the output end and counter of comparator Counting input end connection；The reset terminal of counter is connected with external control signal input, its integral node reseting controling end It is connected with first integral node reset switch S0 control terminal, its output end is and defeated with logic module as circuit output end Enter end connection, each output end of logic module with it is each gating controlling switch correspond, each output end respectively with corresponding gating The control terminal connection of controlling switch；Here, in one group of fixed reference potential end, the fixation of each fixed reference potential end input Reference voltage is all different from the fixed reference potential of other fixed reference potentials input, i.e. the first fixed reference potential Vc1, second Fixed reference potential Vc2 ... and N fixed reference potentials VcN is respectively different；In counter, its counting input end often inputs N Individual pulse, its integral node reseting controling end trigger a pulse, make the switch S0 conductings of first integral node reset, wherein, N For the positive integer more than or equal to 2；Each gating controlling switch is controlled by logic module, and synchronization only has a gating control and opened Conducting is closed, remaining shut-off；When external control signal input input reseting controling signal Reset makes counter resets, count The integral node reseting controling end of device triggers a pulse, makes the switch S0 conductings of first integral node reset, unison counter Output end exports initial reset signal；Logic module is ranked up for each gating controlling switch, when the output end of detection counter When the count value of output adds L, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return Circulation conducting is carried out to first gating controlling switch, when the count value that the output end of counter exports is believed for mN or initial reset Number when, then logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is just whole more than or equal to 1 Number, m are the positive integer more than or equal to 1.
Second of pulse frequency modulated type image sensor circuit in the embodiment of the present invention, its structural representation is referring to figure 6, including power input VCC, photodetector Det1, integral node electric capacity Cint, comparator, first integral node reset open Close S0, counter, circuit output end, ground wire, external control signal input, one group of gating controlling switch (including the first gating Controlling switch Sc1, the second gating controlling switch Sc2 ..., N gatings controlling switch ScN), logic module and one group of fixation ginseng Examine voltage input end (including the first fixed reference potential Vc1, the second fixed reference potential Vc2 ..., N fixed reference potentials VcN), photodetector Det1 positive pole is connected with ground wire, and its negative pole switchs S0 by first integral node reset and power supply is defeated Enter to hold VCC to connect, integral node electric capacity Cint one end is connected with ground wire, and the negative pole of the other end and photodetector Det1 connects Connect；In one group of gating controlling switch and one group of fixed reference potential end, each controlling switch that gates inputs with each fixed reference potential End is corresponded, and the negative-phase input of comparator is connected with photodetector Det1 negative pole, and its normal phase input end passes through respectively Each gating controlling switch connects with corresponding fixed reference potential input, the output end of comparator and the counting of counter Input connects；The reset terminal of counter is connected with external control signal input, its integral node reseting controling end and first Integral node reset switch S0 control terminal connection, its output end connect as circuit output end, and with the input of logic module Connect, each output end of logic module is corresponded with each gating controlling switch, and each output end is opened with corresponding gating control respectively The RESET input of the control terminal connection of pass, external control signal input and logic module connects；Here, one group of fixed reference In voltage end, the fixation that is inputted with other fixed reference potentials of fixed reference potential of each fixed reference potential end input Reference voltage is different；In counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers one Individual pulse, make the switch S0 conductings of first integral node reset, wherein, N is the positive integer more than or equal to 2；Each gating controlling switch Controlled by logic module, synchronization only has a gating controlling switch conducting, remaining shut-off；When external control signal inputs When end input reseting controling signal Reset makes counter resets, the integral node reseting controling end of counter triggers a pulse, Make the switch S0 conductings of first integral node reset；Logic module is ranked up for each gating controlling switch, when detection counter When the count value of output end output adds L, the next gating controlling switch conducting of sequential selection, if being opened without next gating control Close, then return to first gating controlling switch and carry out circulation conducting, when the count value that the output end of counter exports is mN or multiple When position input receives the reseting controling signal Reset for making counter resets, then logic module is returned directly to first gating Controlling switch carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
The third pulse frequency modulated type image sensor circuit in the embodiment of the present invention, its structural representation is referring to figure 7, including power input VCC, photodetector Det1, integral node electric capacity Cint, comparator, first integral node reset open Close S0, counter, circuit output end, ground wire, external control signal input, second integral node reset switch Sr, one group of choosing Logical controlling switch (including the first gating controlling switch Sc1, the second gating controlling switch Sc2 ..., N gating controlling switches ScN), logic module and one group of fixed reference potential input (including the first fixed reference potential Vc1, the second fixed reference electricity Press Vc2 ..., N fixed reference potential VcN), photodetector Det1 positive pole is connected with ground wire, and its negative pole passes through respectively First integral node reset switchs S0 and second integral node reset switch Sr is connected with power input VCC, integral node electricity The one end for holding Cint is connected with ground wire, and the other end is connected with photodetector Det1 negative pole；One group of gating controlling switch And in one group of fixed reference potential end, each controlling switch that gates corresponds with each fixed reference potential input, comparator Negative-phase input is connected with photodetector Det1 negative pole, its normal phase input end respectively by each gating controlling switch with Corresponding fixed reference potential input connection, the output end of comparator and the counting input end of counter connect；Counter Reset terminal is connected with external control signal input, and its integral node reseting controling end is with first integral node reset switch S0's Control terminal is connected, and its output end is connected as circuit output end, and with the input of logic module, and the second integral node is answered Bit switch Sr control terminal is connected with external control signal input, each output end of logic module and each gating controlling switch one One correspondence, control terminal of each output end respectively with corresponding gating controlling switch connect；Here, one group of fixed reference potential end In, the fixed reference that fixed reference potential and other fixed reference potentials of the input of each fixed reference potential end input is electric Pressure is different；In counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers a pulse, Make the switch S0 conductings of first integral node reset；Each gating controlling switch is controlled by logic module, and synchronization only has one Controlling switch conducting is gated, remaining shut-off；When external control signal input input reseting controling signal Reset answers counter During position, the switch Sr conductings of second integral node reset, the output end output initial reset signal of unison counter can be made；Logic Module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports adds L, under sequential selection One gating controlling switch conducting, if without next gating controlling switch, return to first gating controlling switch and circulated Conducting, when the count value that the output end of counter exports is mN or initial reset signal, then logic module is returned directly to first Individual gating controlling switch carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is the positive integer more than or equal to 1.
The 4th kind of pulse frequency modulated type image sensor circuit in the embodiment of the present invention, its structural representation is referring to figure 8, including power input VCC, photodetector Det1, integral node electric capacity Cint, comparator, first integral node reset open Close S0, counter, circuit output end, ground wire, external control signal input, second integral node reset switch Sr, one group of choosing Logical controlling switch (including the first gating controlling switch Sc1, the second gating controlling switch Sc2 ..., N gating controlling switches ScN), logic module and one group of fixed reference potential input (including the first fixed reference potential Vc1, the second fixed reference electricity Press Vc2 ..., N fixed reference potential VcN), photodetector Det1 positive pole is connected with ground wire, and its negative pole passes through respectively First integral node reset switchs S0 and second integral node reset switch Sr is connected with power input VCC, integral node electricity The one end for holding Cint is connected with ground wire, and the other end is connected with photodetector Det1 negative pole；One group of gating controlling switch and one In group fixed reference potential end, each controlling switch that gates corresponds with each fixed reference potential input, the negative of comparator Input is connected with photodetector Det1 negative pole, its normal phase input end respectively by each gating controlling switch with it is corresponding The connection of fixed reference potential input, the counting input end of the output end of comparator and counter connects；The reset of counter End is connected with external control signal input, the control of its integral node reseting controling end and first integral node reset switch S0 End connection, its output end are connected as circuit output end, and with the input of logic module, and the second integral node reset is opened The control terminal for closing Sr is connected with external control signal input, and each output end of logic module gates controlling switch 1 a pair with each Should, control terminal of each output end respectively with corresponding gating controlling switch connects, external control signal input and logic module The RESET input connection；Here, in one group of fixed reference potential end, the fixed reference of each fixed reference potential end input Voltage is all different from the fixed reference potential of other fixed reference potentials input；In counter, its counting input end often inputs N number of Pulse, its integral node reseting controling end trigger a pulse, make the switch S0 conductings of first integral node reset；Each gating control System switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, remaining shut-off；When outside control letter When number input input reseting controling signal Reset makes counter resets, the switch Sr conductings of second integral node reset can be made； Logic module is ranked up for each gating controlling switch, and when the count value that the output end of detection counter exports adds L, order is selected Next gating controlling switch conducting is selected, if without next gating controlling switch, first gating controlling switch is returned to and carries out Circulation conducting, make the resets of counter resets when the count value that the output end of counter exports receives for mN or the RESET input During control signal Reset, then it is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is more than or equal to 1 Positive integer, m are the positive integer more than or equal to 1
In above-mentioned four kinds of pulse frequency modulateds type image sensor circuit, comparator can be two stage comparator or be based on OTA symmetric form comparator or dynamic latch type comparator or controllable Schmidt trigger etc.；And first integral node reset is opened It can be PMOS switch or nmos switch or cmos switch or bootstrapped switch to close S0 and/or second integral node reset switch Sr Deng.
And the fixed reference potential value of each fixed reference potential end input is in integral node resetting voltage to comparing The minimum of the normal phase input end of device can be between input voltage, and the fixed reference potential order of each fixed reference potential end input is arranged Row, and increasedd or decreased successively according to fixed variable quantity.
In one group of fixed reference potential end, the quantity at fixed reference potential end is preferably greater than or equal to N, with equal to N It is optimal.
Visible according to above-mentioned four kinds of pulse frequency modulateds type image sensor circuit, its difference is, if has the second product Whether partial node reset switch Sr and the RESET input of logic module are connected with external control signal input, when with second During integral node reset switch Sr, reseting controling signal Reset directly reactions can be made to integral node electric capacity Cint, to make system Reaction faster, without when counter integral node reseting controling end trigger pulse, and when the reset of logic module inputs When end is connected with external control signal input, it can make reseting controling signal Reset directly reactions to logic module, also may be used So that system response is faster, and counter is not needed to export initial reset signal when resetting again.
In addition, in logic module and counter, it can also have a variety of connected modes to be used to realize counter output Judgement when count value is mN, for example, after the RESET input of logic module and external control signal input are disconnected with counting Device integral node reseting controling end connection, or directly again in logic module set second the RESET input, by its with The integral node reseting controling end connection of counter, so, counter can be utilized to be exported at it when count value is mN and pass through product The pulse of partial node reseting controling end output resets logic module, it is not necessary to which the output to counter counts logic module again Value is judged, it is of course also possible to directly carry out detection judgement by output count value of the logic module to counter.
As can be seen here, above-mentioned four kinds of pulse frequency modulateds type image sensor circuit is inherently identical, and it is distinguished It is only that the reaction speed of the reseting controling signal Reset to the input of outside control signal input.
In use, the output end of counter is connected with output bus, its specific processing step is as follows：
Step 1, external control signal input input reseting controling signal Reset, and integral node electric capacity Cint is reset to Reset level, counter are resetted according to the reseting controling signal Reset inputted, and logic module resets, and control first Controlling switch conducting is gated, remaining closing；
Step 2, the reseting controling signal Reset of input disconnect integral node electric capacity Cint and power input VCC, open Begin to count；
Step 3, in the presence of photodetector Det1, the voltage on integral node electric capacity Cint changes, when this When voltage is equal with the fixed reference potential currently turned on, the output voltage of comparator is overturn, into step 4；
Step 4, the output count value of counter add L, the current gating controlling switch shut-off of logic module control, simultaneously turn on Next gating controlling switch, returns to step 3；
Step 5, when the count value of counter is mN, the integral node reseting controling end of counter exports a pulse, Make the switch S0 conductings of first integral node reset, integral node electric capacity Cint is resetted, and logic module resets, control the One gating controlling switch conducting, remaining closing, returns to step 3.
In this example by taking the third pulse frequency modulated type image sensor circuit as an example, and its N value is limited as 3, L 1, All controlling switches (gating controlling switch, first integral node reset switch S0 and second integral node reset switch Sr) are PMOS switch, counter are 3 digit counters, and one group gating controlling switch includes the first gating controlling switch Sc1, the second gating The gating controlling switch Sc3 of controlling switch Sc2 and the 3rd, corresponding fixed reference potential is respectively the first fixed reference potential Vc1, the second fixed reference potential Vc2 and the 3rd fixed reference potential Vc3, its structural representation are as shown in Figure 9.
It is the work schedule and output result of pulse frequency modulated type image sensor circuit in above-mentioned Fig. 9 referring to Figure 10 Figure, wherein, Vs0 refers to the voltage in first integral node reset switch S0 control terminal, and 1 represents step A, and 2 represent step B, 3 Represent step C, here, illustratively, the output end of 3 digit counters generally comprises three output lines, then in Fig. 10, respectively with OUT0, OUT1 and OUT2 mark the signal of three output line output, and its specific processing step is as follows：
Step A (corresponding steps 1)：External reset.This stage reseting controling signal Reset is low level, and integral node is electric Hold Cint and high level, effect of the counter in reseting controling signal Reset are reset to by second integral node reset switch Sr Under, complete the initial reset process of counter.According to the initial reset signal of counter, the corresponding control of logic module output Signal turns on the first gating controlling switch Sc1, and remaining gating controlling switch Sc2~ScN disconnects.
Step B (corresponding step 2~4)：Count and quantify.This stage reseting controling signal Reset is high level.Visited in photoelectricity Survey in the presence of device Det1, the electric charge of the storage on integral node electric capacity Cint is by photodetector Det1 according to certain speed Released.When the magnitude of voltage Vcint on integral node electric capacity Cint is slightly below reference voltage level Vvref now, compare The output voltage of device is overturn, and the count value of counter adds one, and then Logic control module adjusts next gating switch and led It is logical, into counting next time.
Step C (corresponding steps 5)：Internal reset.When the count value of counter often increases N, the integral node of counter Reseting controling end exports a low level pulse signal, makes the switch S0 conductings of first integral node reset, to integral node electric capacity Cint is resetted.Now logic module knows that the count value of nonce counter is mN, then leads the first gating controlling switch Sc1 It is logical, and then enter to count next time and quantify and internal reset circulation.

Claims (9)

1. pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, ratio Compared with device, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control and believe Number input, one group of gating controlling switch, logic module and one group of fixed reference potential input, the photodetector is just Pole is connected with ground wire, and its negative pole is switched by first integral node reset and is connected with power input, and the one of integral node electric capacity End is connected with ground wire, the negative pole connection of the other end and photodetector；One group of gating controlling switch and one group of fixed reference In voltage end, each controlling switch that gates corresponds with each fixed reference potential input, the negative-phase input and light of comparator The negative pole connection of electric explorer, its normal phase input end pass through each gating controlling switch and corresponding fixed reference potential respectively Input connects, and the output end of comparator and the counting input end of counter connect；The reset terminal of the counter is controlled with outside Signal input part connection processed, its integral node reseting controling end are connected with the control terminal that first integral node reset switchs, and its is defeated Go out end and be used as circuit output end, and be connected with the input of logic module, each output end of logic module is opened with each gating control Close and correspond, control terminal of each output end respectively with corresponding gating controlling switch connects；
In one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input is solid with other The fixed reference potential for determining reference voltage input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers an arteries and veins Punching, makes first integral node reset switch conduction, wherein, N is the positive integer more than or equal to 2；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, remaining Shut-off；
When external control signal input input reseting controling signal makes counter resets, the integral node of counter resets control A pulse is triggered at end processed, makes first integral node reset switch conduction, the output end output initial reset letter of unison counter Number；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports adds L When, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return to first gating control Switch carries out circulation conducting, when the count value that the output end of counter exports is mN or initial reset signal, then logic module It is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is more than or equal to 1 Positive integer.
2. pulse frequency modulated type image sensor circuit according to claim 1, it is characterised in that the comparator is two Level comparator or symmetric form comparator or dynamic latch type comparator or controllable Schmidt trigger based on OTA；
The first integral node reset switch is PMOS switch or nmos switch or cmos switch or bootstrapped switch；
The fixed reference potential value of each fixed reference potential end input is in integral node resetting voltage to comparator The minimum of normal phase input end can be between input voltage, the fixed reference potential order of each fixed reference potential end input arranges, And increasedd or decreased successively according to fixed variable quantity；
In one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
3. pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, ratio Compared with device, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control and believe Number input, one group of gating controlling switch, logic module and one group of fixed reference potential input, the photodetector is just Pole is connected with ground wire, and its negative pole is switched by first integral node reset and is connected with power input, and the one of integral node electric capacity End is connected with ground wire, the negative pole connection of the other end and photodetector；One group of gating controlling switch and one group of fixed reference In voltage end, each controlling switch that gates corresponds with each fixed reference potential input, the negative-phase input and light of comparator The negative pole connection of electric explorer, its normal phase input end pass through each gating controlling switch and corresponding fixed reference potential respectively Input connects, and the output end of comparator and the counting input end of counter connect；The reset terminal of the counter is controlled with outside Signal input part connection processed, its integral node reseting controling end are connected with the control terminal that first integral node reset switchs, and its is defeated Go out end and be used as circuit output end, and be connected with the input of logic module, each output end of logic module is opened with each gating control Close correspond, each output end respectively with it is corresponding gating controlling switch control terminal connect, external control signal input with The RESET input connection of logic module；
In one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input is solid with other The fixed reference potential for determining reference voltage input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers an arteries and veins Punching, makes first integral node reset switch conduction, wherein, N is the positive integer more than or equal to 2；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, remaining Shut-off；
When external control signal input input reseting controling signal makes counter resets, the integral node of counter resets control A pulse is triggered at end processed, makes first integral node reset switch conduction；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports adds L When, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return to first gating control Switch carries out circulation conducting, answers counter when the count value that the output end of counter exports receives for mN or the RESET input During the reseting controling signal of position, then logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is Positive integer more than or equal to 1, m are the positive integer more than or equal to 1.
4. pulse frequency modulated type image sensor circuit according to claim 3, it is characterised in that the comparator is two Level comparator or symmetric form comparator or dynamic latch type comparator or controllable Schmidt trigger based on OTA；
The first integral node reset switch is PMOS switch or nmos switch or cmos switch or bootstrapped switch；
The fixed reference potential value of each fixed reference potential end input is in integral node resetting voltage to comparator The minimum of normal phase input end can be between input voltage, the fixed reference potential order of each fixed reference potential end input arranges, And increasedd or decreased successively according to fixed variable quantity；
In one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
5. pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, ratio Compared with device, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control and believe Number input, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential input End, the positive pole of the photodetector are connected with ground wire, and its negative pole is switched respectively by first integral node reset and the second product Partial node reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetection The negative pole connection of device；In one group of gating controlling switch and one group of fixed reference potential end, it is each gate controlling switch with it is each solid Determine reference voltage input terminal one-to-one corresponding, the negative-phase input of comparator and the negative pole of photodetector connect, the input of its positive End is connected by each gating controlling switch with corresponding fixed reference potential input respectively, the output end and meter of comparator The counting input end connection of number device；The reset terminal of the counter is connected with external control signal input, and its integral node is answered Position control terminal be connected with the control terminal that first integral node reset switchs, its output end as circuit output end, and with logic mould The input connection of block, the control terminal of the second integral node reset switch are connected with external control signal input, logic Each output end of module corresponds with each gating controlling switch, the control with corresponding gating controlling switch respectively of each output end End connection；
In one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input is solid with other The fixed reference potential for determining reference voltage input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers an arteries and veins Punching, makes first integral node reset switch conduction；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, remaining Shut-off；
When external control signal input input reseting controling signal makes counter resets, second integral node reset can be made Switch conduction, the output end output initial reset signal of unison counter；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports adds L When, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return to first gating control Switch carries out circulation conducting, when the count value that the output end of counter exports is mN or initial reset signal, then logic module It is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is the positive integer more than or equal to 1, and m is more than or equal to 1 Positive integer.
6. pulse frequency modulated type image sensor circuit according to claim 5, it is characterised in that the comparator is two Level comparator or symmetric form comparator or dynamic latch type comparator or controllable Schmidt trigger based on OTA；
First integral node reset switch and/or second integral node reset switch for PMOS switch or nmos switch or Cmos switch or bootstrapped switch；
The fixed reference potential value of each fixed reference potential end input is in integral node resetting voltage to comparator The minimum of normal phase input end can be between input voltage, the fixed reference potential order of each fixed reference potential end input arranges, And increasedd or decreased successively according to fixed variable quantity；
In one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
7. pulse frequency modulated type image sensor circuit, including power input, photodetector, integral node electric capacity, ratio Compared with device, first integral node reset switch, counter, circuit output end and ground wire, it is characterised in that also include outside control and believe Number input, second integral node reset switch, one group of gating controlling switch, logic module and one group of fixed reference potential input End, the positive pole of the photodetector are connected with ground wire, and its negative pole is switched respectively by first integral node reset and the second product Partial node reset switch is connected with power input, and one end of integral node electric capacity is connected with ground wire, the other end and photodetection The negative pole connection of device；In one group of gating controlling switch and one group of fixed reference potential end, it is each gate controlling switch with it is each solid Determine reference voltage input terminal one-to-one corresponding, the negative-phase input of comparator and the negative pole of photodetector connect, the input of its positive End is connected by each gating controlling switch with corresponding fixed reference potential input respectively, the output end and meter of comparator The counting input end connection of number device；The reset terminal of the counter is connected with external control signal input, and its integral node is answered Position control terminal be connected with the control terminal that first integral node reset switchs, its output end as circuit output end, and with logic mould The input connection of block, the control terminal of the second integral node reset switch are connected with external control signal input, logic Each output end of module corresponds with each gating controlling switch, the control with corresponding gating controlling switch respectively of each output end The RESET input of end connection, external control signal input and logic module connects；
In one group of fixed reference potential end, the fixed reference potential of each fixed reference potential end input is solid with other The fixed reference potential for determining reference voltage input is different；
In the counter, its counting input end often inputs N number of pulse, and its integral node reseting controling end triggers an arteries and veins Punching, makes first integral node reset switch conduction；
Each gating controlling switch is controlled by logic module, and synchronization only has a gating controlling switch conducting, remaining Shut-off；
When external control signal input input reseting controling signal makes counter resets, second integral node reset can be made Switch conduction；
The logic module is ranked up for each gating controlling switch, when the count value that the output end of detection counter exports adds L When, the next gating controlling switch conducting of sequential selection, if without next gating controlling switch, return to first gating control Switch carries out circulation conducting, answers counter when the count value that the output end of counter exports receives for mN or the RESET input During the reseting controling signal of position, then logic module is returned directly to first gating controlling switch and carries out circulation conducting, wherein, L is Positive integer more than or equal to 1, m are the positive integer more than or equal to 1.
8. pulse frequency modulated type image sensor circuit according to claim 7, it is characterised in that the comparator is two Level comparator or symmetric form comparator or dynamic latch type comparator or controllable Schmidt trigger based on OTA；
First integral node reset switch and/or second integral node reset switch for PMOS switch or nmos switch or Cmos switch or bootstrapped switch；
The fixed reference potential value of each fixed reference potential end input is in integral node resetting voltage to comparator The minimum of normal phase input end can be between input voltage, the fixed reference potential order of each fixed reference potential end input arranges, And increasedd or decreased successively according to fixed variable quantity；
In one group of fixed reference potential end, the quantity at fixed reference potential end is more than or equal to N.
9. the processing method of pulse frequency modulated type image sensor circuit, applied to such as claim 1 or 2 or 3 or 4 or 5 or 6 Or the pulse frequency modulated type image sensor circuit described in 7 or 8, it is characterised in that comprise the following steps：
Step 1, external control signal input input reseting controling signal, integral node electric capacity reset to reset level, counted Device is resetted according to the reseting controling signal inputted, and logic module resets, and controls first gating controlling switch conducting, its Remaining closing；
Step 2, the reseting controling signal of input disconnect integral node electric capacity and power input, start counting up；
Step 3, in the presence of photodetector, the voltage on integral node electric capacity changes, when the voltage with when leading When logical fixed reference potential is equal, the output voltage of comparator is overturn, into step 4；
Step 4, the output count value of counter add L, the current gating controlling switch shut-off of logic module control, simultaneously turn on next Individual gating controlling switch, returns to step 3；
Step 5, when the count value of counter is mN, the integral node reseting controling end of counter exports a pulse, makes the One integral node reset switch S0 is turned on, and integral node electric capacity is resetted, and logic module resets, and controls first gating Controlling switch turns on, and remaining closing, returns to step 3.
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