CN107395218A - R-T unit and design method based on FPGA and radio frequency agile transceiver - Google Patents
R-T unit and design method based on FPGA and radio frequency agile transceiver Download PDFInfo
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- CN107395218A CN107395218A CN201710557486.2A CN201710557486A CN107395218A CN 107395218 A CN107395218 A CN 107395218A CN 201710557486 A CN201710557486 A CN 201710557486A CN 107395218 A CN107395218 A CN 107395218A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
Abstract
The invention belongs to technical field of radio, discloses a kind of R-T unit and design method based on FPGA and radio frequency agile transceiver, including：Radio frequency agile transceiver AD936X and FPGA control module.Its specific design method includes：Software merit rating AD936X design parameter is assessed with AD936X, generates corresponding configuration file；Configuration file is loaded into AD936X corresponding register by SPI using FPGA control modules；Base band sends signal and is transferred to by ODDR transmission modes from FPGA control modules in AD936X, after processing, is launched by radio frequency sendaisle；After echo-signal is received by radio frequency reception channel, through AD936X processing, then it is transmitted back to by IDDR transmission modes in FPGA control modules and does Data Post.The present invention improves the integrated level of transceiver, simplifies circuit design while the data for realizing real-time high-efficiency communicate.
Description
Technical field
The invention belongs to technical field of radio, more particularly to a kind of transmitting-receiving dress based on FPGA and radio frequency agile transceiver
Put and design method.
Background technology
Flexibility and opening of the software and radio technique due to its height, solve traditional communication in integrated level, performance
With the deficiency in repeatable programming, it is used widely in terms of wireless communication technology.In software and radio technique, scene can
Gate array (FPGA) is programmed because in flexible design, disposal ability is strong and the characteristics of repeatability programming etc., in software
There is the advantage of uniqueness in the communication system of radio.And the radio frequency that AD936X is a series of high integration that ADI companies release is received
Send out solution, be internally integrated the frequency synthesizer of analog filtering, frequency mixer, data converter, transmitting and receiving channel with
And the module such as programmable-gain, DC offset calibration, the transmission-receiving function of radiofrequency signal is realized well, greatly reduces radio frequency
The equipment volume of transmitting-receiving subassembly.
Therefore, a set of R-T unit based on FPGA and radio frequency agile transceiver AD936X is established, designs and is applied to
The design method of FPGA and AD936X intercommunication, possess the spies such as high integration, high-performance, software is configurable for realization
The wireless transceiver system of property has very important impetus.
The content of the invention
It is an object of the invention to provide a kind of R-T unit and design method based on FPGA and radio frequency agile transceiver,
To solve the problems such as circuit structure of present communication system complexity repeats programmatic difference.
The present invention is achieved in that a kind of R-T unit based on FPGA and radio frequency agile transceiver, described to be based on
The R-T unit of FPGA and radio frequency agile transceiver includes：
Radio frequency agile transceiver AD936X, for handling the data message sent and received；
FPGA control modules, for configuration file to be loaded into AD936X corresponding register by SPI, its configuration file
It is to assess software by AD936X to generate by design requirement；AD936X is transferred to by ODDR transmission modes for signal will to be sent
In, and the receives echo-signal after AD936X is handled is transferred back in FPGA by IDDR transmission modes.
Further, the AD936X is integrated for radio frequency, mixed signal sum type matrix necessary to realizing transceiver function
Block, include frequency synthesizer, frequency mixer, digital data interface, analog-digital converter, digital analog converter, wave filter and low noise
Amplifier.
Further, the data transfer based on SPI follows a kind of 24 bit formats, wherein the 1st expression data transfer direction, the
2 to 6 represent to need the byte numbers that transmit, the 7th to 16 writing address for representing transmission data, and the 17th to 24 represent will be by
Transmit to the data of specified register address.
The present invention provides a kind of design method of the R-T unit based on FPGA and radio frequency agile transceiver, described to set
Meter method comprises the following steps：
Step 1, the design parameter of radio frequency agile transceiver is corresponded to AD936X assessment software merit ratings, and generation is matched somebody with somebody accordingly
Put file；
Step 2, FPGA control modules are in communication with each other by SPI and AD936X, and the FPGA control modules are by configuration file
It is loaded into AD936X register；
Step 3, base band transmission signal is transferred in AD936X by FPGA control modules by ODDR transmission modes, through place
Launched after reason by radio frequency sendaisle；
Step 4, echo-signal is received by AD936X radio frequency reception channel, after AD936X is handled, then is passed through
IDDR transmission modes transfer back in FPGA control modules and do Data Post.
Further, in the step 1, AD936X design parameter is determined, software merit rating is assessed using AD936X and correspondingly penetrated
The register of frequency agile transceiver, generate the configuration file being made up of accordingly control command；The AD936X is applied to a variety of
Communication standard, including FDD and tdd systems；Design parameter includes：Base band frequency of phase locking, send filtering, receive filter
Ripple, digital data interface, auxiliary digital analog converter, submodule converter, Peripheral Interface, radio frequency transmission frequency, radio frequency reception
Frequency, hybrid gain control, baseband filtering calibration, DC offset calibration, the orthogonal verification of transmission.
Further, the FPGA control modules in the step 2 are in communication with each other by SPI and AD936X, by configuration file
Control command be loaded into successively in AD936X register；Communication process includes reading and writes two kinds of operations, writes and refers to FPGA controls
Module writes the control command in configuration file in AD936X corresponding registers successively；Reading refers to that AD936X designs in configuration
In parametric procedure, when being configured to some phaselocked loop parts or check part, after the completion of needing to wait for locking or checking procedure, ability
Continue subsequent operation, in order to judge whether locking or checking procedure are completed, the state value of these registers need to be read out；
The particular state of the AD936X registers includes：Base band phase locked loop lock-out state, receive verification state, send school
Test state, receiving terminal phase lock loop locks state, transmitting terminal phase lock loop locks state, receiving filter align mode, transmission filtering
Device align mode, base band DC offset calibration state, send orthogonal verification state.
Further, FPGA control modules are included by the SPI and AD936X idiographic flows being in communication with each other in the step 2：
(1) AD936X configuration files are stored in FPGA control modules；
(2) control command of AD936X configuration files is loaded into AD936X registers successively by SPI interface format, and
Judge data transfer direction；
(3) if data transfer direction reads out the state value of corresponding AD936X registers, and judge it to read
Whether locking or verification are completed.If not completing locking or verification, return and continue reading state instruction, if having completed locking or school
Test, then return to AD936X configuration files and write next control command；
(4) if data transfer direction is writes, control command is write in AD936X registers, then is judged in configuration file
Control command whether write.If control command does not write, return to AD936X configuration files and write next control command,
If writing, configuration AD936X registers are completed.
Further, the signal transmission process in the step 3 includes：Base band send signal by ODDR transmission modes from
FPGA control modules are transferred in AD936X, after mixing, interpolation, filtering process, are launched by radio frequency sending port.
Further, the signal receive process in the step 4 include：Echo-signal is led to by AD936X radio frequency reception
Road is received, and FPGA controls are transmitted back to after the processing such as AD936X mixing, extraction, filtering, then by IDDR transmission modes
Data Post is done in module.
Further, the AD936X is integrated with sendaisle and the reception of one or two independent control on monolithic device
Passage is used for forming the communication structures that single-shot list is received or double hairs pair are received, and multiple AD936X can also be used to form the logical of MIMO
Believe structure；
The communication structure being made up of single AD936X, baseband signal are made up of all the way ODDR and IDDR transmission modes
Parallel data, transmitted between FPGA control modules and AD936X；The communication structure being made up of multiple AD936X, base band transmission letter
Number respectively by ODDR and IDDR transmission mode channeling parallel datas, and in FPGA control modules and corresponding multiple
Transmitted between AD936X.
Advantages of the present invention and good effect are：AD936X realizes the transmitting-receiving process process from base band to radio frequency, integrates
Analog filtering, frequency mixer, data converter, frequency synthesizer and programmable-gain, the direct current biasing of transmitting and receiving channel
The RF front-end modules such as calibration, configurable digital interface is provided for FPGA, and the R-T unit is except basic peripheral circuit, base band
Processing module and radio frequency leading portion processing module are integrated in FPGA and AD936X, greatly reduce the complexity and equipment of circuit
Volume；Meanwhile AD936X is integrated with one or two radio-frequency receiving-transmitting passage, the communication that single-shot list is received or two hairs two are received may make up
Structure, multiple AD936X may make up the communication structure of MIMO.Design method of the present invention is applied to various transceivers,
Design parameter can be changed according to the requirement of system, design baseband processing arrangements, flexible configuration AD936X, there is very strong adaptation
Property and flexibility.
Brief description of the drawings
Fig. 1 is the R-T unit structural representation provided in an embodiment of the present invention based on FPGA and radio frequency agile transceiver；
In figure：1st, FPGA control modules；2nd, radio frequency agile transceiver.
Fig. 2 is the design method stream of the R-T unit provided in an embodiment of the present invention based on FPGA and radio frequency agile transceiver
Journey schematic diagram.
Fig. 3 is that write operation and reading are grasped during FPGA control modules provided in an embodiment of the present invention are in communication with each other with AD9361
The timing diagram of work；
In figure：(a) write operation timing diagram during FPGA control modules are in communication with each other with AD9361；(b) FPGA controls mould
The timing diagram of read operation during block is in communication with each other with AD9361.
Fig. 4 is the operating process that FPGA control modules provided in an embodiment of the present invention are in communication with each other by SPI and AD9361
Figure.
Fig. 5 is that baseband signal provided in an embodiment of the present invention sends and receives schematic flow sheet；
In figure：(a) the transmission flow schematic diagram of baseband signal；(b) the reception schematic flow sheet of baseband signal.
Fig. 6 is that single AD9361 provided in an embodiment of the present invention data under dual-port full-duplex mode send and receive
Timing diagram；
In figure：(a) the single AD9361 timing diagrams that data are sent under dual-port full-duplex mode；(b) single AD9361
The timing diagram of data receiver under dual-port full-duplex mode.
Fig. 7 is the part of transmission signal on AD-FMCOMMS5-EBZ evaluation boards prevention at radio-frequency port provided in an embodiment of the present invention
Time domain beamformer.
Fig. 8 is the frequency spectrum of transmission signal on AD-FMCOMMS5-EBZ evaluation boards prevention at radio-frequency port provided in an embodiment of the present invention
Figure.
Fig. 9 is the time domain waveform and 4 roadbed bands that base band provided in an embodiment of the present invention sends I, Q road partial data in signal
The time domain beamformer of I, Q road partial data in reception signal；
In figure：(a) base band sends the time domain beamformer of I, Q road partial data in signal, wherein, 4 roadbed bands send signal
All same；(b) in 4 road baseband receiving signals I, Q road partial data time domain beamformer.
Figure 10 is provided in an embodiment of the present invention through Costas loops correcting frequency offset or 4 road baseband receiving signals mutually to the rear
The time domain beamformer of middle I, Q road partial data.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention
It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to
Limit the present invention.
The application principle of the present invention is explained in detail below in conjunction with the accompanying drawings.
R-T unit provided in an embodiment of the present invention based on FPGA and radio frequency agile transceiver specifically includes two parts：
The evaluation board AD- of Xilinx Zynq-7000All Programmable Soc ZC706 development platforms and AD9361
FMCOMMS5-EBZ。
Xilinx Zynq-7000All Programmable Soc ZC706 development platforms use Xilinx companies technique
Newest Soc Platform Solutions, the solution, which is integrated with, double-core ARM Cortex A9 processors and possesses high-performance power consumption
The 28nm FPGAs of ratio, release new solution for developer and one flexible platform is provided.
AD-FMCOMMS5-EBZ evaluation boards are a High Speed Analog modules, and it includes two panels AD9361 RF transceivers, can
Simplify and accelerate the prototype of 4*4 multichannels input multiple-channel output (MIMO) wireless transceiver application.
ZC706 development boards are connected with AD-FMCOMMS5-EBZ evaluation boards by FMC (FPGA mezzanine connectors), form one
Individual 4*4 MIMO wireless transceiver systems.
As shown in figure 1, the R-T unit provided in an embodiment of the present invention based on FPGA and radio frequency agile transceiver includes：
Radio frequency agile transceiver AD936X, for handling the data message sent and received；
FPGA control modules, for configuration file to be loaded into AD936X corresponding register by SPI, its configuration file
It is to assess software by AD936X to generate by design requirement；AD936X is transferred to by ODDR transmission modes for signal will to be sent
In, and the receives echo-signal after AD936X is handled is transferred back in FPGA by IDDR transmission modes.
As shown in Fig. 2 the design of the R-T unit provided in an embodiment of the present invention based on FPGA and radio frequency agile transceiver
Method specifically includes following steps：
Step 1, the design parameter of radio frequency agile transceiver is corresponded to AD9361 assessment software merit ratings by design requirement, it is raw
Into corresponding configuration file (S201).
In embodiment, according to design requirement, it is thus necessary to determine that data communication standard, digital data interface transformat, base band
The local oscillator clock frequency of the filter parameter of data clock rate, transmitting and receiving channel, transmitting and receiving channel, launches and connects
Receive the design parameters such as the gain reduction coefficient of gain amplifier of passage.Specifically, AD9361 operating frequency range is 70MHz
To 6.0GHz, cover most of charter and unlicensed band, the bandwidth chahnel scope of support is less than 200kHz to 56MHz.
In the present embodiment, setting communication standard is fdd mode, and FPDP is single-ended CMOS forms, baseband clock frequency 28MHz,
The local oscillator clock of transmitting and receiving channel is 540MHz, recycles AD9361 to assess the configuration text that Software Create corresponds to design parameter
Part.
Step 2, FPGA control modules are in communication with each other by SPI and two AD9361, and the FPGA control modules are according to penetrating
Frequency access structure, configuration file is loaded into two AD9361 register respectively (S202).
As shown in Fig. 3 (a) and Fig. 3 (b), FPGA control modules include FPGA to two with the process that AD9361 is in communication with each other
AD9361 reading and two kinds of operations are write, and the SPI interface format that read and write operation follows is：Write order follows a kind of 24
Form, wherein the 1st expression data transfer direction, the 2nd to 6 represents to need the byte number transmitted, and the 7th to 16 represents transmission
The writing address of data, the 17th to 24 represents that the data of specified register address will be transferred to；Read command follows similar
Form, difference are that last 8 represent to read the numerical value in register from AD9361.
As shown in figure 4, specifically, the FPGA control modules of ZC706 development boards are commented by SPI and AD-FMCOMMS5-EBZ
Estimating the process that two on plate AD9361 are in communication with each other includes：
(1) the AD9361 configuration files in step 1 are stored in FPGA control modules (S401)；
(2) control command of AD9361 configuration files is distinguished successively by SPI interface format using FPGA control modules
It is loaded into two panels AD9361 registers (S402), and judges the data transfer direction (S403) of control command；
In embodiment, because two AD9361 in AD-FMCOMMS5-EBZ evaluation boards share same SPI, FPGA controls
Module can take out the control command in configuration file successively, and serially be loaded into two AD9361 deposit respectively by SPI
In device.AD9361 writes corresponding data or reads corresponding number according to data transfer direction and the writing address of transmission data
According to.
(3) when the data transfer direction of control command is reads, then by the current state value of corresponding AD9361 registers point
Do not read out from two panels AD9361 (S404), and judge whether two panels AD9361 locking or verification have been completed
(S405).If not completing locking or verification, the state value for continuing to read register is returned, if having completed to lock or verify,
Then return to AD9361 configuration files and write next control command；
, wherein it is desired to the buffer status being read includes：Base band phase locked loop lock-out state, receive verification state, send
Verification state, receiving terminal phase lock loop locks state, transmitting terminal phase lock loop locks state, receiving filter align mode, transmission filter
Ripple device align mode, base band DC offset calibration state, send orthogonal verification state.
(4) control command is then write to two panels AD9361 deposit successively to write when the data transfer direction of control command
In device (S406), then judge whether the control command in configuration file writes (S407).If control command does not write, return
AD9361 configuration files simultaneously write next control command, if writing, configuration AD9361 registers are completed.
Step 3, as shown in Fig. 5 (a), FPGA control modules transmit base band transmission signal to 4 road output ports, pass through
ODDR transmission modes are transferred in two AD9361, are carried out after being processed by two AD9361 4 radio frequency sendaisles
Launch (S203).
In embodiment, it is to use qpsk modulation signal caused by Matlab softwares that base band, which sends signal, soft with Matlab first
Part produce one group of quaternary random data, wherein sample frequency is 28MHz, and signal code speed is 4Mbps, through differential coding,
After the processing such as molding filtration (rolloff-factor 0.8), caused I, Q two paths of data is respectively stored in FPGA control modules
In ROM.After the completion of the configuration process in step S202, the I, Q signal in ROM to passing through 4 road output ports to (i.e. 4 respectively
Road signal all same), wherein two paths of signals to being transferred to first AD9361 parallel data port by ODDR transmission modes,
Referring to Fig. 6 a, its each signal transmission order is T1_I, T1_Q, T2_I, T2_Q, and two paths of signals is to passing through ODDR transmission modes in addition
Second AD9361 parallel data port is transferred to, two paths of data is respectively through AD9361 interpolation, filtering, mixing and amplification etc.
Reason, is launched from two AD9361 4 radio frequency sendaisles.
As shown in Figure 7 and Figure 8, the prevention at radio-frequency port transmitting of AD-FMCOMMS5-EBZ evaluation boards can be observed from instrument
The time domain beamformer and spectrogram of signal, and the time domain beamformer and spectrogram all same of 4 transmission signals.From time domain waveform
Envelope can determine whether out base band send signal substantially waveform, from frequency spectrum can be seen that transmission signal centered on frequency be 540MHz,
Signal with a width of 7.2MHz.
Step 4, as shown in Fig. 5 (b), echo-signal is received by two AD9361 4 radio frequency reception channels,
Respectively after AD9361 is handled, then 4 tunnel reception signals are passed back by IDDR transmission modes, be re-fed into FPGA control modules and do number
According to post processing (S204).
In embodiment, after echo-signal is received by two AD9361 4 radio frequency reception channels, by being mixed,
Filtering, the processing such as extract, be respectively sent to two AD9361 parallel data port, ginseng is as shown in Fig. 6 (b), each and line number
It is R1_I, R1_Q, R2_I, R2_Q according to the signal transmission order of port, two-way port signal is respectively passed back by IDDR transmission modes
Totally 4 road baseband receiving signals, and the frequency deviation or phase deflection correction of baseband receiving signals are done in FPGA control modules, then do follow-up
Data processing.
As shown in Fig. 9 (a) and 9 (b), in signal transmission process, two AD9361 4 roadbeds are sent to from FPGA control modules
It is identical I, Q road signal that band, which sends signal,；In signal receive process, collected from FPGA control modules from two AD9361
The oscillogram for the 4 road baseband receiving signals sent can be seen that because reception signal has frequency deviation or skew, and its waveform produces
Distortion, and phase ambiguity phenomenon also be present in I, Q road signal received.Therefore, 4 road baseband receiving signals difference will can be received
Through Costas loop processeds, the frequency deviation or skew of correction signal.As shown in Figure 10, after about 1000 points, loop convergence, I, Q
It is consistent that road waveform sends signal waveform with base band substantially.Correcting frequency offset or the signal of skew can solve phase ambiguity through differential decoding
Problem, then do follow-up data processing.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of design method of the R-T unit based on FPGA and radio frequency agile transceiver, it is characterised in that described to be based on
The design method of the R-T unit of FPGA and radio frequency agile transceiver comprises the following steps：
Step 1, the design parameter of radio frequency agile transceiver is corresponded to AD936X assessment software merit ratings, generate corresponding configuration text
Part；
Step 2, FPGA control modules are in communication with each other by SPI and AD936X, and configuration file is loaded into by the FPGA control modules
In AD936X register；
Step 3, base band transmission signal is transferred in AD936X by FPGA control modules by ODDR transmission modes, after processing
Launched by radio frequency sendaisle；
Step 4, echo-signal is received by AD936X radio frequency reception channel, after AD936X is handled, then passes through IDDR
Transmission mode transfers back in FPGA control modules and does Data Post.
2. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In, in the step 1, determine AD936X design parameter, using AD936X assess software merit rating correspond to radio frequency agile transceiver
Register, generate the configuration file that is made up of accordingly control command；The AD936X is applied to a variety of communication standards, including
FDD and tdd systems；Design parameter includes：Base band frequency of phase locking, transmission is filtered, accepted filter, numerical data connects
Mouth, auxiliary digital analog converter, submodule converter, Peripheral Interface, radio frequency transmission frequency, radio frequency reception frequency, hybrid gain
Control, baseband filtering calibration, DC offset calibration, the orthogonal verification of transmission.
3. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In, the FPGA control modules in the step 2 are in communication with each other by SPI and AD936X, by the control command in configuration file according to
In secondary loading AD936X register；Communication process includes reading and writes two kinds of operations, writes and refers to that FPGA control modules will configure text
Control command in part is write in AD936X corresponding registers successively；Reading refers to AD936X in design parameter process is configured,
When being configured to some phaselocked loop parts or check part, after the completion of needing to wait for locking or checking procedure, follow-up behaviour could be continued
Make, in order to judge whether locking or checking procedure are completed, the state value of these registers need to be read out；
The particular state of the AD936X registers includes：Base band phase locked loop lock-out state, receive verification state, send verification shape
State, receiving terminal phase lock loop locks state, transmitting terminal phase lock loop locks state, receiving filter align mode, transmitting filter school
Quasi- state, base band DC offset calibration state, send orthogonal verification state.
4. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In FPGA control modules are included by the SPI and AD936X idiographic flows being in communication with each other in the step 2：
(1) AD936X configuration files are stored in FPGA control modules；
(2) control command of AD936X configuration files is loaded into AD936X registers successively by SPI interface format, and judged
Data transfer direction；
(3) if data transfer direction reads out the state value of corresponding AD936X registers, and judge its locking to read
Or whether verification is completed；If not completing locking or verification, return and continue reading state instruction, if having completed to lock or having verified,
Then return to AD936X configuration files and write next control command；
(4) if data transfer direction is writes, control command is write in AD936X registers, then judge the control in configuration file
Whether system order writes；If control command does not write, return to AD936X configuration files and write next control command, if writing
It is complete, then configure AD936X registers and complete.
5. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In the signal transmission process in the step 3 includes：Base band sends signal by ODDR transmission modes from FPGA control modules
It is transferred in AD936X, after mixing, interpolation, filtering process, is launched by radio frequency sending port.
6. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In the signal receive process in the step 4 include：Echo-signal is received by AD936X radio frequency reception channel, warp
After the processing such as AD936X mixing, extraction, filtering, then after being transmitted back to by IDDR transmission modes and doing data in FPGA control modules
Processing.
7. the design method of the R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver, its feature exist
In the AD936X is integrated with the sendaisle of one or two independent control on monolithic device and receiving channel is used for forming
Single-shot list is received or the double communication structures received of double hairs, and multiple AD936X can also be used to form the communication structure of MIMO；
The communication structure being made up of single AD936X, baseband signal are made up of parallel all the way ODDR and IDDR transmission modes
Data, transmitted between FPGA control modules and AD936X；The communication structure being made up of multiple AD936X, baseband signal point
Not by ODDR and IDDR transmission mode channeling parallel datas, and FPGA control modules and corresponding multiple AD936X it
Between transmit.
8. a kind of design method of R-T unit as claimed in claim 1 based on FPGA and radio frequency agile transceiver based on
FPGA and radio frequency agile transceiver R-T unit, it is characterised in that the transmitting-receiving based on FPGA and radio frequency agile transceiver
Device includes：
Radio frequency agile transceiver AD936X, for handling the data message sent and received；
FPGA control modules, for by configuration file by SPI be loaded into AD936X corresponding register in, its configuration file be by
AD936X assesses software and generated by design requirement；It is transferred to for signal will to be sent by ODDR transmission modes in AD936X, and
Receives echo-signal after AD936X is handled is transferred back in FPGA by IDDR transmission modes.
9. the R-T unit based on FPGA and radio frequency agile transceiver as claimed in claim 8, it is characterised in that described
AD936X is integrated for radio frequency, mixed signal and digital module necessary to realizing transceiver function, include frequency synthesizer,
Frequency mixer, digital data interface, analog-digital converter, digital analog converter, wave filter and low-noise amplifier.
10. the R-T unit based on FPGA and radio frequency agile transceiver as claimed in claim 8, it is characterised in that based on SPI
Data transfer follow a kind of 24 bit formats, wherein the 1st expression data transfer direction, the 2nd to 6 represents to need the word transmitted
Joint number, the 7th to 16 writing address for representing transmission data, the 17th to 24 expression will be transferred to specified register address
Data.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN109474921A (en) * | 2018-12-11 | 2019-03-15 | 深圳市皓华网络通讯股份有限公司 | A kind of ad hoc network emergency communication system and its communication means |
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| CN110704366A (en) * | 2019-09-11 | 2020-01-17 | 无锡江南计算技术研究所 | Pin multiplexing device and method based on IDDR and ODDR circuits inside FPGA |
| CN111708001A (en) * | 2020-06-17 | 2020-09-25 | 桂林理工大学 | Laser radar data acquisition system with remote data transmission function |
| CN114039643A (en) * | 2021-10-22 | 2022-02-11 | 上海航天电子有限公司 | Smartfusion 2-based channel time delay automatic calibration method |
| CN114268382A (en) * | 2022-02-28 | 2022-04-01 | 四川鸿创电子科技有限公司 | Method, device and equipment for automatically calibrating AD9361 board card and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108809362A (en) * | 2018-07-17 | 2018-11-13 | 中国船舶重工集团公司第七〇九研究所 | A kind of wide bandwidth SAW reader emitter and its method |
| CN109474921B (en) * | 2018-12-11 | 2021-03-02 | 深圳市皓华网络通讯股份有限公司 | Ad hoc network emergency communication system and communication method thereof |
| CN109474921A (en) * | 2018-12-11 | 2019-03-15 | 深圳市皓华网络通讯股份有限公司 | A kind of ad hoc network emergency communication system and its communication means |
| CN110071739A (en) * | 2019-03-11 | 2019-07-30 | 西安思丹德信息技术有限公司 | A kind of communication system and method based on frequency hopping, GMSK and DS |
| CN110071739B (en) * | 2019-03-11 | 2021-09-14 | 西安思丹德信息技术有限公司 | Communication system and method based on frequency hopping, GMSK and DS |
| CN110704366A (en) * | 2019-09-11 | 2020-01-17 | 无锡江南计算技术研究所 | Pin multiplexing device and method based on IDDR and ODDR circuits inside FPGA |
| CN111708001A (en) * | 2020-06-17 | 2020-09-25 | 桂林理工大学 | Laser radar data acquisition system with remote data transmission function |
| CN114039643A (en) * | 2021-10-22 | 2022-02-11 | 上海航天电子有限公司 | Smartfusion 2-based channel time delay automatic calibration method |
| CN114039643B (en) * | 2021-10-22 | 2024-04-05 | 上海航天电子有限公司 | Channel delay automatic calibration method based on Smartfusion2 |
| CN114268382A (en) * | 2022-02-28 | 2022-04-01 | 四川鸿创电子科技有限公司 | Method, device and equipment for automatically calibrating AD9361 board card and storage medium |
| CN114268382B (en) * | 2022-02-28 | 2022-05-13 | 四川鸿创电子科技有限公司 | Method, device and equipment for automatically calibrating AD9361 board card and storage medium |
| CN116208182A (en) * | 2023-02-02 | 2023-06-02 | 上海毫微太科技有限公司 | Digital intermediate frequency signal processing device, method, equipment and medium |
| CN116208182B (en) * | 2023-02-02 | 2024-02-13 | 上海毫微太科技有限公司 | Digital intermediate frequency signal processing device, method, equipment and medium |
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