CN105716480A - Radar fuse based on radio frequency agile transceiver and design method of radar fuse - Google Patents
Radar fuse based on radio frequency agile transceiver and design method of radar fuse Download PDFInfo
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- CN105716480A CN105716480A CN201610079510.1A CN201610079510A CN105716480A CN 105716480 A CN105716480 A CN 105716480A CN 201610079510 A CN201610079510 A CN 201610079510A CN 105716480 A CN105716480 A CN 105716480A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C15/00—Arming-means in fuzes; Safety means for preventing premature detonation of fuzes or charges
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Abstract
The invention belongs to the field of radio engineering, and discloses a radar fuse based on a radio frequency agile transceiver AD9361 and a design method of the radar fuse. The design method comprises the steps that performance parameters of the radio frequency agile transceiver AD9361 are configured; a transmitted signal is acquired by the radio frequency agile transceiver AD9361 and transmitted through a transmitting channel of the radio frequency agile transceiver AD9361; an echo signal is received by the radio frequency agile transceiver AD9361, received through a receiving channel of the radio frequency agile transceiver AD9361 and then sent to a controller FPGA; and the controller FPGA acquires an operating parameter value of a target according to the received echo signal, and if the operating parameter value of the target meets the detonation condition, a detonation signal is output by the controller FPGA. The radar fuse and the design method can be widely applied to control of the detonation time, selection of the optimal attack point and completing of detonation control according to a preset strategy.
Description
Technical field
The present invention relates to technical field of radio, particularly relate to a kind of radar fuze based on radio frequency agile transceiver AD9361 and method for designing thereof, can be widely applied to the control of Detonating Time, select the point of attack of the best, complete initiation control according to predetermined policy.
Background technology
Fuse is to utilize target information, environmental information, platform information and the network information, ignites or the warhead charge that ignites by predetermined policy, and the optional point of attack, provides continuation of the journey or increases the control system of journey engine ignition instruction and damage effectiveness information.Fuse implements, as armament systems, the control core that terminal is injured, and has a very important role in the antagonism of armament systems (or system).Fuse is in armament systems terminal and injures the First Line that " raw with dead " resists, and its information crosslinking with armament systems is the key technology being badly in need of development under information war.
At present conventional fuse is based on analog circuit and realizes, the fuze system realized based on analog circuit manually correction parameter in debugging process, can obtain good performance under certain condition.But the fuze system that analog circuit realizes there is also the drawback of the following aspects:
(1) system does not possess programmability, and flexibility ratio is poor, and a kind of fuze system can only for specific target, when target property changes, fuze system is difficult to adapt to new target property, and this has resulted in the decline of systematic function, it is difficult to tackle war environment complicated and changeable at present.
(2) fuze system that analog circuit realizes is built by discrete component, this just inevitably causes the volume of whole system excessively huge, in the today requiring miniaturization, huge fuze system is difficult to meet the restriction of missile borne system steric requirements, constrains reducing further of the volume of body own.
Summary of the invention
For the problems referred to above, it is an object of the invention to provide a kind of radar fuze based on radio frequency agile transceiver AD9361 and method for designing thereof, construct an opening, standardization, modularity, reconfigurable general purpose fuze platform.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that and are achieved.
Technical scheme one:
A kind of radar fuze based on radio frequency agile transceiver AD9361, described radio frequency agile transceiver AD9361 is integrated with analog-digital converter, digital to analog converter, frequency mixer, wave filter, power amplifier, described radar fuze is included radio frequency agile transceiver AD9361 and controller FPGA, described radio frequency agile transceiver AD9361 and is communicated with controller FPGA by serial peripheral equipment interface SPI.
The feature of technical scheme one and being further improved to:
The interface data of described serial peripheral equipment interface SPI is 24 bit data format, and wherein, front 6 bit data are for arranging the byte number in bus direction and transmitted data；Middle 10 bit data are for transmitting the writing address of data；Rear 8 bit data are for transmitting register parameters value to be written.
Technical scheme two:
A kind of radar fuze method for designing based on radio frequency agile transceiver AD9361, described method for designing is applied in the radar fuze comprising radio frequency agile transceiver AD9361 and controller FPGA composition, and described method for designing includes:
Step 1, configures the performance parameter of described radio frequency agile transceiver AD9361；
Step 2, described radio frequency agile transceiver AD9361 obtains and launches signal, being launched by the transmission channel of described radio frequency agile transceiver AD9361 by described transmitting signal, described transmitting signal is pre-stored within controller FPGA, and described transmitting signal is used for detecting target；
Step 3, described radio frequency agile transceiver AD9361 receives echo-signal, described echo-signal is received by the reception passage of described radio frequency agile transceiver AD9361, is then forwarded to controller FPGA；
Step 4, described controller FPGA obtains the motion parameter of target according to the echo-signal received, if the motion parameter of described target meets initiation conditions, then described controller FPGA exports time break, and described initiation conditions and described time break are pre-stored within described controller FPGA.
The feature of technical scheme two and being further improved to:
(1) in step 1, the performance parameter of described radio frequency agile transceiver AD9361 at least includes: the baseband clocks parameter of radio frequency agile transceiver AD9361, the filter parameter of transmission channel, receive the filter parameter of passage, the local oscillation signal frequency of transmission channel frequency mixer, receive the local oscillation signal frequency of channel mixer, the gain reduction coefficient of transmission channel gain amplifier, receive the gain reduction coefficient of channel gain amplifier.
(2) in step 2, described transmitting signal is pseudorandom encoded signal, and the complex expression of described pseudorandom encoded signal is:
Wherein, f0For frequency of carrier signal,For phase modulation function.
(3), in step 2, described transmitting signal is launched by the transmission channel of described radio frequency agile transceiver AD9361, specifically includes:
Described transmitting signal is sent to radio frequency agile transceiver AD9361 by controller FPGA, carry out digital-to-analogue conversion, interpolation, filtering, mixing, processing and amplifying through radio frequency agile transceiver AD9361 transmission channel, realize signal by radio frequency agile transceiver AD9361 and launch.
(4), in step 3, described echo-signal is received by the reception passage of described radio frequency agile transceiver AD9361, specifically includes:
Described radio frequency agile transceiver AD9361 receives echo-signal, described echo-signal through receiving passage and carry out being mixed, filter, extracting, analog-to-digital conversion process, be sent to controller FPGA.
(5), in step 4, described controller FPGA obtains the motion parameter of target according to the echo-signal received, and specifically includes:
The described controller FPGA echo-signal to receiving carries out matched filtering and Doppler's accumulation, obtains the motion parameter of target, and described motion parameter comprises distance parameter, speed parameter and angle parameter；
Prestoring, in described controller FPGA, threshold value of detonating, if the weighted mean of described distance parameter, described speed parameter and described angle parameter is more than described threshold value of detonating, then described controller FPGA exports time break.
Present invention have the advantage that
First, the radio-frequency transmissions of the present invention and reception part are realized by AD9361 chip, compared to conventional analog circuits implementation, by ingredients multiple in fuze system as: digital to analog converter (ADC), analog-digital converter (DAC), frequency mixer, wave filter, gain control, radio frequency amplifier section are integrated in one chip AD9361, reduce system bulk on the one hand, reduce system power dissipation.On the other hand, the various parameters of AD9361 are realized by the method for software arrangements, can revise systematic parameter at any time according to target property, to tackle the battlefield surroundings of complexity, convenient in application, flexible, have very strong adaptability.
Second, the various functions (such as waveform generation, state modulator, digital sample, modulation /demodulation, signal extraction process etc.) of fuse are completed by the present invention with software, are formed and have high degree of flexibility, open electronic fuse system.System is based on if sampling and Digital Signal Processing, the signal of fuse is produced, target echo detection under waveform modulated and demodulation, interference and background clutter, function of detonating control etc., the PLD (FPGA) and radio frequency agile transceiver (AD9361) that are integrated in fuze system realize.Corresponding mathematical model and algorithm is realized, so that different operation conditions, intersection state, high low latitude background environment and disturbed condition are had adaptivity and functional expansionary by fuse hardware platform based on FPGA programming software.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The schematic flow sheet of a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 that Fig. 1 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
AD9361 is the radio frequency agile transceiver that a high-performance, multichannel one chip are integrated, this device integrated RF front end is integrated with mixed signal baseband part flexibly, is integrated with analog-digital converter (ADC), digital to analog converter (DAC), mixing, the function such as filtering.Thering is provided configurable digital interface for processor, importing thus simplifying design.AD9361 operating frequency range is 70MHz to 6GHz, contains major part charter and unlicensed band, and the bandwidth chahnel of support ranges for 200kHz to 56MHz.
The embodiment of the present invention provides a kind of radar fuze based on radio frequency agile transceiver AD9361, described radio frequency agile transceiver AD9361 is integrated with analog-digital converter, digital to analog converter, frequency mixer, wave filter, power amplifier, described radar fuze is included radio frequency agile transceiver AD9361 and controller FPGA, described radio frequency agile transceiver AD9361 and is communicated with controller FPGA by serial peripheral equipment interface SPI.The interface data of described serial peripheral equipment interface SPI is 24 bit data format, and wherein, front 6 bit data are for arranging the byte number in bus direction and transmitted data；Middle 10 bit data are for transmitting the writing address of data；Rear 8 bit data are for transmitting register parameters value to be written.
The embodiment of the present invention also provides for a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361, described method for designing is applied in the radar fuze comprising radio frequency agile transceiver AD9361 and controller FPGA composition, as it is shown in figure 1, described method for designing includes:
Step 1, configures the performance parameter of described radio frequency agile transceiver AD9361.
In step 1, the performance parameter of described radio frequency agile transceiver AD9361 at least includes:
The baseband clocks parameter of radio frequency agile transceiver AD9361, the filter parameter of transmission channel, receive the filter parameter of passage, the local oscillation signal frequency of transmission channel frequency mixer, receive the local oscillation signal frequency of channel mixer, the gain reduction coefficient of transmission channel gain amplifier, receives the gain reduction coefficient of channel gain amplifier.
Concrete, the performance parameter of described radio frequency agile transceiver AD9361 is carried out software arrangements and includes: (1) enables the clock signal of radio frequency agile transceiver AD9361, and the baseband clocks parameter of radio frequency agile transceiver AD9361 is configured.By phase lock loop locks baseband clock frequency.
(2) utilize radio frequency agile transceiver AD9361 special filter design software to be designed launching and receiving signalling channel filter parameter, its cut-off frequency, filter order are set, obtain transmission channel and receive the design of filter parameter of passage.
(3) configuration RF Phase-Lock Loop parameter, is configured transmitting mixer and reception frequency mixer parameter, configures transmitting mixer local oscillation signal frequency and receive frequency mixer local oscillation signal frequency.
(4) gain amplifier of transmission channel and reception passage is configured, its gain reduction coefficient is set.So far radio frequency agile transceiver AD9361 parameter configuration is complete.
Exemplary, to being configured that of radio frequency agile transceiver AD9361 depositor
Radio frequency agile transceiver AD9361 is communicated with controller FPGA by a Serial Peripheral Interface (SPI) (SPI).This interface allows controller FPGA by a kind of simple address data serial bus agreement, arranges radio frequency agile transceiver AD9361 register parameters.SPI interface data follow a kind of 24 bit formats.First 6 are used for arranging bus direction and needing the byte number of transmission.Ensuing 10 is the writing address of data.Last 8 is register parameters value to be written.
The clock configuration of radio frequency agile transceiver AD9361 includes baseband clocks configuration and the configuration of local oscillator clock.
Baseband clocks configures: the clock signal that baseband clocks is relevant for generating all base band.These include the sampling clock of ADC and DAC, data-interface clock signal and all data frame signal.Programmable frequency ranges for 700MHz to 1400MHz, is specifically dependent upon data rate and the sampling rate requirement of system.According to designing requirement, arranging baseband clock frequency is 1280MHz, by consulting register configuration handbook, can obtain register address and baseband clocks computing formula, bring into and calculate parameter accordingly, obtain register parameters value, by SPI interface, AD9361 is configured.
Local oscillator clock configures: radio frequency agile transceiver AD9361 contains two identical local oscillator clock synthesizers, and for generating the local oscillator clock needed for RF signal path, one is used for receptor, and one is used for emitter.Programmable frequency ranges for 70MHz to 6GHz, is specifically dependent upon target property parameter value.The local oscillator clock frequency arranging receptor and emitter in the embodiment of the present invention is 2.4GHz, by consulting depositor handbook, calculates relevant parameter, and eventually through SPI interface, related register is configured.
The wave filter configuration of radio frequency agile transceiver AD9361: the I road of controller FPGA generation and Q road signal are before entering the internal DAC of radio frequency agile transceiver AD9361, first pass through 128 tap finite completely able to programme long shock response (FIR) wave filter without interpolation options, to realize I road and Q road signal are filtered, to remove sampling artifacts.When being filtered device configuration, use the radio frequency agile transceiver AD9361 Matlab software package provided to passband width, attenuation outside a channel, be configured by frequency, obtain the filter coefficient value of required configuration, by consulting depositor handbook, obtain corresponding register address, and by SPI interface, filter coefficient value is write corresponding depositor, to realize the configuration of FIR filter.
Step 2, described radio frequency agile transceiver AD9361 obtains and launches signal, is launched by the transmission channel of described radio frequency agile transceiver AD9361 by described transmitting signal.
Described transmitting signal is pre-stored within controller FPGA, and described transmitting signal is used for detecting target.
Exemplary, produce the Coded Signals of 156 with Matlab software, be quantified as 12bit signed number evidence, and the data of generation are stored in the ROM of FPGA, by FPGA by data except delivering to AD9361, to realize signal transmitting.
In step 2, described transmitting signal is pseudorandom encoded signal, and the complex expression of described pseudorandom encoded signal is:
Wherein, f0For frequency of carrier signal,For phase modulation function.
For Coded Signals,Only 0 and the two kinds possible value of π, available binary phase sequenceRepresent, it is also possible to use binary sequenceRepresent.
In the present invention, produced Coded Signals is 13 Barker code signal { Kw}=[1,1,1,1,1 ,-1 ,-1,1,1 ,-1,1 ,-1,1], utilize Matlab software to produce 156 points, data bit width is the Barker code signal of 12, and is stored in the memorizer of controller FPGA by the Barker code signal of generation, to realize the generation of Coded Signals.
In step 2, described transmitting signal is launched by the transmission channel of described radio frequency agile transceiver AD9361, specifically includes:
Described transmitting signal is sent to radio frequency agile transceiver AD9361 by controller FPGA, carry out digital-to-analogue conversion, interpolation, filtering, mixing, processing and amplifying through radio frequency agile transceiver AD9361 transmission channel, realize signal by radio frequency agile transceiver AD9361 and launch.
Step 3, described radio frequency agile transceiver AD9361 receives echo-signal, described echo-signal is received by the reception passage of described radio frequency agile transceiver AD9361, is then forwarded to controller FPGA.
In step 3, described echo-signal is received by the reception passage of described radio frequency agile transceiver AD9361, specifically includes:
Described radio frequency agile transceiver AD9361 receives echo-signal, described echo-signal through receiving passage and carry out being mixed, filter, extracting, analog-to-digital conversion process, be sent to controller FPGA.
Step 4, described controller FPGA obtains the motion parameter of target according to the echo-signal received, if the motion parameter of described target meets initiation conditions, then described controller FPGA exports time break.
Described initiation conditions and described time break are pre-stored within described controller FPGA.
In step 4, described controller FPGA obtains the motion parameter of target according to the echo-signal received, and specifically includes:
The described controller FPGA echo-signal to receiving carries out matched filtering and Doppler's accumulation, obtains the motion parameter of target, and described motion parameter comprises distance parameter, speed parameter and angle parameter.
Prestoring, in described controller FPGA, threshold value of detonating, if the weighted mean of described distance parameter, described speed parameter and described angle parameter is more than described threshold value of detonating, then described controller FPGA exports time break.
The echo-signal received is sequentially carried out Digital Down Convert, matched filtering and Doppler's accumulation by described controller FPGA.
Concrete, the process of Digital Down Convert is as follows:
Digital frequency converter has digital mixer, numerically-controlled oscillator (NCO) and low pass filter three part composition, and the real signal after digitized is divided into two-way by the present invention, and cos (w is multiplied by a roadcN), it is down-converted to 0 intermediate frequency, forms the signal identical with primary signal phase place；Sin (w is multiplied by another roadcN), it is down-converted to 0 intermediate frequency, forms the signal orthogonal with original signal.Its mathematic(al) representation is:
Wherein fcFor the carrier frequency (mid frequency) of intermediate-freuqncy signal, TsBeing the sampling interval, the real signal that S (n) exports after representing ADC, y (n) exports after Digital Down Convert.
Concrete, the process of matched filtering is as follows:
The method of matched filtering has a lot, substantially can be summarized as three kinds: directly related method, quickly diaphragm filter and frequency domain analysis, the method being based on Fourier transform that the present invention adopts, its basic thought is through FFT to frequency domain by signal, then it is multiplied by the frequency domain weighting coefficient (system matches function) required by matched filtering, transforms to time domain then through IFFT and obtain compression result.Range pulse is compressed, owing to distance adaptation function is fixing, it is possible in advance adaptation function is stored in Rom memorizer, directly reads from Rom memorizer during actual treatment, is then multiplied with the result after input signal FFT.
Concrete again, the process of Doppler's accumulation is as follows:
Doppler accumulates employing fast Fourier transform (FFT) and processes, it is exactly that in distance, echo-signal is divided into many distance unit, then pass through the echo launched M time, same range gate carries out coherent accumulation (doppler filtering), so not only can improve signal to noise ratio, it is also possible to measure target velocity.Scheme adopts many group filter parallel to process the measurement realizing speed.The mode adopting FIR filter individually designed in each wave filter processes, and the wave filter that the purpose of do so is FIR structure can carry out individually designed according to different speed, and each wave filter is individually controllable to the suppression of 0.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in computer read/write memory medium, this program upon execution, performs to include the step of said method embodiment；And aforesaid storage medium includes: the various media that can store program code such as ROM, RAM, magnetic disc or CDs.
The above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (8)
1. the radar fuze based on radio frequency agile transceiver AD9361, described radio frequency agile transceiver AD9361 is integrated with analog-digital converter, digital to analog converter, frequency mixer, wave filter, power amplifier, it is characterized in that, described radar fuze is included radio frequency agile transceiver AD9361 and controller FPGA, described radio frequency agile transceiver AD9361 and is communicated with controller FPGA by serial peripheral equipment interface SPI.
2. a kind of radar fuze based on radio frequency agile transceiver AD9361 according to claim 1, it is characterized in that, the interface data of described serial peripheral equipment interface SPI is 24 bit data format, and wherein, front 6 bit data are for arranging the byte number in bus direction and transmitted data；Middle 10 bit data are for transmitting the writing address of data；Rear 8 bit data are for transmitting register parameters value to be written.
3., based on a radar fuze method for designing of radio frequency agile transceiver AD9361, described method for designing is applied in the radar fuze comprising radio frequency agile transceiver AD9361 and controller FPGA composition, it is characterised in that described method for designing includes:
Step 1, configures the performance parameter of described radio frequency agile transceiver AD9361；
Step 2, described radio frequency agile transceiver AD9361 obtains and launches signal, being launched by the transmission channel of described radio frequency agile transceiver AD9361 by described transmitting signal, described transmitting signal is pre-stored within controller FPGA, and described transmitting signal is used for detecting target；
Step 3, described radio frequency agile transceiver AD9361 receives echo-signal, described echo-signal is received by the reception passage of described radio frequency agile transceiver AD9361, is then forwarded to controller FPGA；
Step 4, described controller FPGA receives described echo-signal, and the motion parameter of target is obtained according to the echo-signal received, if the motion parameter of described target meets initiation conditions, then described controller FPGA exports time break, and described initiation conditions and described time break are pre-stored within described controller FPGA.
4. a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 according to claim 3, it is characterised in that in step 1, the performance parameter of described radio frequency agile transceiver AD9361 at least includes:
The baseband clocks parameter of radio frequency agile transceiver AD9361, the filter parameter of transmission channel, receive the filter parameter of passage, the local oscillation signal frequency of transmission channel frequency mixer, receive the local oscillation signal frequency of channel mixer, the gain reduction coefficient of transmission channel gain amplifier, receives the gain reduction coefficient of channel gain amplifier.
5. a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 according to claim 3, it is characterised in that in step 2, described transmitting signal is pseudorandom encoded signal, and the complex expression of described pseudorandom encoded signal is:
Wherein, f0For frequency of carrier signal,For phase modulation function.
6. a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 according to claim 3, it is characterised in that in step 2, is launched described transmitting signal by the transmission channel of described radio frequency agile transceiver AD9361, specifically includes:
Described transmitting signal is sent to radio frequency agile transceiver AD9361 by controller FPGA, after radio frequency agile transceiver AD9361 transmission channel carries out digital-to-analogue conversion, interpolation, filtering, mixing, processing and amplifying, carries out signal transmitting.
7. a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 according to claim 3, it is characterised in that in step 3, is received described echo-signal by the reception passage of described radio frequency agile transceiver AD9361, specifically includes:
Described radio frequency agile transceiver AD9361 receives echo-signal, and described echo-signal, through receiving passage and carry out being mixed, filter, extracting, after analog-to-digital conversion process, is sent to controller FPGA.
8. a kind of radar fuze method for designing based on radio frequency agile transceiver AD9361 according to claim 3, it is characterised in that in step 4, described controller FPGA obtains the motion parameter of target according to the echo-signal received, and specifically includes:
The described controller FPGA echo-signal to receiving carries out matched filtering and Doppler's accumulation, obtains the motion parameter of target, and the motion parameter of described target comprises the distance parameter of target, speed parameter and angle parameter；
Prestoring, in described controller FPGA, threshold value of detonating, if the weighted mean of angle parameter is more than described threshold value of detonating described in described distance parameter and described speed parameter, then described controller FPGA exports time break.
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| CN107395218A (en) * | 2017-07-10 | 2017-11-24 | 西安电子科技大学 | R-T unit and design method based on FPGA and radio frequency agile transceiver |
| CN109120285A (en) * | 2018-09-13 | 2019-01-01 | 深圳天之励诚科技有限公司 | A kind of solution of Tetra terminal power amplifier linearization |
| CN110266349A (en) * | 2019-07-11 | 2019-09-20 | 上海航天测控通信研究所 | A kind of Small Universal double frequency continuous wave answering machine |
| CN110991030A (en) * | 2019-11-28 | 2020-04-10 | 北京电子工程总体研究所 | Method and system for simulating universal complex war introduction system |
| CN110991030B (en) * | 2019-11-28 | 2023-10-13 | 北京电子工程总体研究所 | Method and system for simulating general complex warfare system |
| CN113720222A (en) * | 2021-08-30 | 2021-11-30 | 山西宇翔信息技术有限公司 | Radio fuze and phase correction method, platform and readable storage medium thereof |
| CN113720222B (en) * | 2021-08-30 | 2023-06-16 | 山西宇翔信息技术有限公司 | Radio fuse, phase correction method thereof, platform and readable storage medium |
| CN114577076A (en) * | 2022-04-07 | 2022-06-03 | 北京宏动科技股份有限公司 | Method for eliminating impulse fuse noise |
| CN114577076B (en) * | 2022-04-07 | 2023-09-01 | 北京宏动科技股份有限公司 | Method for eliminating impulse fuse noise |
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