CN109474921B - Ad hoc network emergency communication system and communication method thereof - Google Patents

Ad hoc network emergency communication system and communication method thereof Download PDF

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Publication number
CN109474921B
CN109474921B CN201811513957.0A CN201811513957A CN109474921B CN 109474921 B CN109474921 B CN 109474921B CN 201811513957 A CN201811513957 A CN 201811513957A CN 109474921 B CN109474921 B CN 109474921B
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radio frequency
transceiver
circuit
switch
receiving
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CN109474921A (en
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吴增鸣
姜飞
张自豹
聂万里
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Shenzhen Howah Network Communication Co ltd
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Shenzhen Howah Network Communication Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
    • H04W4/90—Services for handling of emergency or hazardous situations, e.g. earthquake and tsunami warning systems [ETWS]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/18—Self-organising networks, e.g. ad-hoc networks or sensor networks

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  • Computer Networks & Wireless Communication (AREA)
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  • Environmental & Geological Engineering (AREA)
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Abstract

The invention discloses an ad hoc network emergency communication system and a communication method thereof, wherein the system comprises: the core network connection end comprises a first transceiver, a first FPGA digital circuit, a first agile transceiver, a plurality of first radio frequency circuits and a plurality of first antennas corresponding to the radio frequency circuits; and the base station connecting end comprises a second transceiver, a second FPGA digital circuit, a second agile transceiver, a plurality of second radio frequency circuits and a plurality of second antennas corresponding to the plurality of radio frequency circuits. The invention has the advantages that under the conditions that underground optical fibers cannot be laid, the optical fibers are dug and broken, and temporary large-scale activities are emergent and the like in a specific environment, the wireless technology is adopted, the operation is simple, and no professional is needed to open the system; the requirement on the environment is low, and the system signal strength can be intelligently and adaptively adjusted at any time and any place, so that the target area is covered by network signals of 3G, 4G, 5G and the like.

Description

Ad hoc network emergency communication system and communication method thereof
Technical Field
The invention relates to the technical field of emergency communication, in particular to an ad hoc network emergency communication system and a communication method thereof.
Background
At present, a core network (EPC) is connected to a base station or a user coverage end (BBU + RRU mode), a core network (EPC) packet network interface is generally adopted to be connected to the base station or the user coverage end (BBU + RRU mode) through a wired optical fiber mode or a microwave transmission system mode to cover 3G, 4G, and 5G user network signals, however, under some emergency communication conditions, such as construction break, natural disasters, and the like, optical fibers cannot be laid in special scenes, or transmission cannot be recovered through the optical fibers in a short time, but in reality, demands for rapidly recovering network signal coverage, or holding large-scale activities, holiday celebration activities, and the like to temporarily increase traffic data capacity exist.
Referring to fig. 1, fig. 1 is a schematic view of an application scenario of an ad hoc network emergency communication system in the prior art, a conventional microwave transmission system includes (two microwave devices and two pairs of microwave antennas), a core network (EPC) packet network is connected to a microwave device feeder line through six types of lines or optical fibers to connect to a microwave antenna, a base station connection end is connected to a microwave device through a microwave antenna feeder line, and 3G, 4G, 5G are covered to a tower user coverage antenna by six types of lines or optical fibers accessed to a base station (BTS) or (BBU + RRU), so that the microwave system has the following disadvantages: the method has the advantages that the opening time is long, a professional is required to open the communication system, at least 5-10 hours are required according to the environment, the packet loss rate is high and reaches 5%, the requirement on the opening environment is high, the intermediate transmission path is slightly shielded, the communication system cannot be opened, and the emergency communication market scene is not suitable.
Disclosure of Invention
The invention aims to provide an ad hoc network emergency communication system and a communication method thereof, and solves the problems that in the prior art, the switching-on time is long, a professional needs to switch on, the packet loss rate is as high as 5% after at least 5-10 hours according to the environment, the switching-on environment is high, an intermediate transmission path is slightly shielded, and the emergency communication system is not suitable for emergency communication market scenes.
The technical scheme of the invention is realized as follows:
in one aspect, the present invention provides an ad hoc network emergency communication system, including:
the core network connection end comprises a first transceiver, a first FPGA digital circuit, a first agile transceiver, a plurality of first radio frequency circuits and a plurality of first antennas corresponding to the radio frequency circuits, one end of the first transceiver is connected to a preset core network, one end of the first FPGA digital circuit is connected to the other end of the first transceiver, one end of the first agile transceiver is connected to the other end of the first FPGA digital circuit, one end of each first radio frequency circuit is connected to the other end of the first agile transceiver, and the other end of each first radio frequency circuit is connected to the corresponding first antenna;
the base station comprises a base station connecting end, wherein the base station connecting end comprises a second transceiver, a second FPGA digital circuit, a second agile transceiver, a plurality of second radio frequency circuits and a plurality of second antennas corresponding to the radio frequency circuits, one end of the second transceiver is connected to a preset base station or a user coverage end, one end of the second FPGA digital circuit is connected to the other end of the second transceiver, one end of the second agile transceiver is connected to the other end of the second FPGA digital circuit, one end of each second radio frequency circuit is connected to the other end of the second agile transceiver, the other end of each second radio frequency circuit is connected to the corresponding second antenna, and the plurality of second antennas are respectively connected to the plurality of first antennas in a wireless mode.
In the ad hoc network emergency communication system according to the present invention, the core network connection terminal further includes a first RJ45 interface, and one end of the first transceiver is connected to the core network through the first RJ45 interface.
In the ad hoc network emergency communication system of the present invention, the base station connection terminal further comprises a second RJ45 interface, and one end of the second transceiver is connected to the base station or the user coverage terminal through the second RJ45 interface.
In the ad hoc network emergency communication system, the core network connection end further includes a first processor and a first boost circuit, the first processor is respectively connected to the plurality of first radio frequency circuits and to the first FPGA digital circuit, and the first processor is further connected to the plurality of first radio frequency circuits through the first boost circuit.
In the ad hoc network emergency communication system, the base station connection end further includes a second processor and a second boost circuit, the second processor is respectively connected to the plurality of second radio frequency circuits and to the second FPGA digital circuit, and the second processor is further connected to the plurality of second radio frequency circuits through the second boost circuit.
In the ad hoc network emergency communication system, each first radio frequency circuit comprises a first adaptive logic circuit, a first transmission digital attenuator, a first transmission gain amplifying tube, a first radio frequency switch chip, a first high linearity pushing tube, a first radio frequency amplifier group, a first adjusting attenuator, a first circulator, a first main path filter, a first transmission detector, a first comparator, a first low noise amplifier, a first primary switch, a first branch filter, a first secondary switch, a first primary reception gain amplifying tube, a first reception digital attenuator, a first secondary reception gain amplifying tube and a first reception detector;
the first end of the first adaptive logic circuit is connected to the first agile transceiver through a preset transmitting port, the first end of the first transmitting digital attenuator is connected to the second end of the first adaptive logic circuit, one end of the first transmitting gain amplifying tube is connected to the second end of the first transmitting digital attenuator, the first end of the first radio frequency switch chip is connected to the other end of the first transmitting gain amplifying tube, one end of the first high linearity push tube is connected to the second end of the first radio frequency switch chip, one end of the first radio frequency amplifier group is connected to the other end of the first high linearity push tube, one end of the first adjusting attenuator is connected to the other end of the first radio frequency amplifier group, and the other end of the first adjusting attenuator is connected to the first agile transceiver through a preset connecting port, a first end of the first circulator is connected to the other end of the first rf amplifier group, one end of the first main path filter is connected to a second end of the first circulator, the other end of the first main path filter is connected to the first antenna through a predetermined antenna port, a third end of the first circulator is connected to one end of the first low noise amplifier, the other end of the first low noise amplifier is connected to a first end of a first primary switch, a second end of the first primary switch is connected to one end of the first branch filter, the other end of the first branch filter is connected to a first end of the first secondary switch, a second end of the first secondary switch is connected to one end of the first primary receiving gain amplifying tube, and the other end of the first primary receiving gain amplifying tube is connected to a first end of the first receiving digital attenuator, the second end of the first receiving digital attenuator is connected to the first end of the first secondary receiving gain amplifying tube, and the second end of the first secondary receiving gain amplifying tube is connected to the first agile transceiver through a preset receiving port;
one end of the first comparator is connected to the third end of the first adaptive logic circuit, and the first emission detector is respectively connected to the other end of the first comparator, the other end of the first radio frequency amplifier group, the third end of the first emission digital attenuator, the third end of the first radio frequency switch chip and the first processor;
one end of the first receiving detector is connected to the third end of the first secondary receiving gain amplifying tube, the first processor is further connected to the other end of the first receiving detector, the third end of the first receiving digital attenuator, the third end of the first primary switch, the third end of the first secondary switch and one end of the first booster circuit, and the other end of the first booster circuit is connected to the other end of the first radio frequency amplifier group.
In the ad hoc network emergency communication system, each second radio frequency circuit comprises a second adaptive logic circuit, a second transmitting digital attenuator, a second transmitting gain amplifying tube, a second radio frequency switch chip, a second high linearity pushing tube, a second radio frequency amplifier group, a second adjusting attenuator, a second circulator, a second main path filter, a second transmitting detector, a second comparator, a second low noise amplifier, a second primary switch, a second branch filter, a second secondary switch, a second primary receiving gain amplifying tube, a second receiving digital attenuator, a second secondary receiving gain amplifying tube and a second receiving detector;
the first end of the second adaptive logic circuit is connected to the second agile transceiver through a preset transmitting port, the first end of the second transmitting digital attenuator is connected to the second end of the second adaptive logic circuit, one end of the second transmitting gain amplifying tube is connected to the second end of the second transmitting digital attenuator, the first end of the second radio frequency switch chip is connected to the other end of the second transmitting gain amplifying tube, one end of the second high linearity push tube is connected to the second end of the second radio frequency switch chip, one end of the second radio frequency amplifier group is connected to the other end of the second high linearity push tube, one end of the second adjusting attenuator is connected to the other end of the second radio frequency amplifier group, and the other end of the second adjusting attenuator is connected to the second agile transceiver through a preset connecting port, a first end of the second circulator is connected to the other end of the second rf amplifier group, one end of the second main path filter is connected to a second end of the second circulator, the other end of the second main path filter is connected to the second antenna through a predetermined antenna port, a third end of the second circulator is connected to one end of the second low noise amplifier, the other end of the second low noise amplifier is connected to a first end of a second one-stage switch, a second end of the second one-stage switch is connected to one end of the second branch filter, the other end of the second branch filter is connected to a first end of the second two-stage switch, a second end of the second two-stage switch is connected to one end of the second one-stage receive gain amplifier tube, and the other end of the second one-stage receive gain amplifier tube is connected to a first end of the second receive digital attenuator, the second end of the second receiving digital attenuator is connected to the first end of the second secondary receiving gain amplifying tube, and the second end of the second secondary receiving gain amplifying tube is connected to the second agile transceiver through a preset receiving port;
one end of the second comparator is connected to the third end of the second adaptive logic circuit, and the second emission detector is respectively connected to the other end of the second comparator, the other end of the second radio frequency amplifier group, the third end of the second emission digital attenuator, the third end of the second radio frequency switch chip, and the second processor;
one end of the second receiving detector is connected to the third end of the second secondary receiving gain amplifying tube, the second processor is further connected to the other end of the second receiving detector, the third end of the second receiving digital attenuator, the third end of the second primary switch, the third end of the second secondary switch and one end of the second booster circuit, and the other end of the second booster circuit is connected to the other end of the second radio frequency amplifier group.
In the ad hoc network emergency communication system, the first FPGA digital circuit includes a first FPGA chip, a first RAM module, a first ROM module, and a first SD card, the first FPGA chip is connected to the other end of the first transceiver and one end of the first agile transceiver, respectively, and the first RAM module, the first ROM module, and the first SD card are all connected to the first FPGA chip.
In the ad hoc network emergency communication system, the second FPGA digital circuit includes a second FPGA chip, a second RAM module, a second ROM module, and a second SD card, the second FPGA chip is connected to the other end of the second transceiver and one end of the second agile transceiver, respectively, and the second RAM module, the second ROM module, and the second SD card are all connected to the second FPGA chip.
In another aspect, a communication method of an ad hoc network emergency communication system is provided, where the ad hoc network emergency communication system is adopted, and the communication method includes:
arranging a core network connecting end at a preset core network to establish communication connection between the core network connecting end and the core network;
arranging a base station connecting end at a preset base station or user coverage end to establish communication connection between the base station connecting end and the base station or the user coverage end;
and establishing wireless communication connection between the core network connecting end and the base station connecting end, thereby realizing signal coverage of the base station or the user coverage end.
Therefore, the invention has the advantages that under the conditions that underground optical fibers cannot be laid, the optical fibers are dug and broken, and temporary large-scale activities are emergent and the like in a specific environment, the wireless technology is adopted, the operation is simple, and no professional is needed to open the system; the requirement on the environment is low, and the system signal strength can be intelligently and adaptively adjusted at any time and any place, so that the target area is covered by network signals of 3G, 4G, 5G and the like.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
fig. 1 is a schematic view of an application scenario of an ad hoc network emergency communication system in the prior art;
fig. 2 is a schematic view of an application scenario of an ad hoc network emergency communication system according to an embodiment of the present invention;
fig. 3 is a schematic internal structure diagram of an ad hoc network emergency communication system according to an embodiment of the present invention;
FIG. 4 is a schematic connection diagram of a first FPGA digital circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a first FPGA digital circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a first rf circuit according to an embodiment of the present invention.
Detailed Description
In order to more clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the following description is only a specific illustration of the embodiments of the present invention and should not be taken as limiting the scope of the invention.
Referring to fig. 2, fig. 2 is a schematic view of an application scenario of an ad hoc network emergency communication system 100 according to an embodiment of the present invention, where the ad hoc network emergency communication system 100 includes a core network connection end 1 and a base station connection end 2.
An application embodiment of the intelligent emergency communication system of the broadband wireless ad hoc network of the invention is as follows: the core network is dug to be broken or can not be recovered due to other reasons from a roof machine room to a user coverage end of an iron tower, 2 pieces of ad hoc network emergency equipment and 4 antennas can be used, the visual transmission distance can reach 10KM, one piece of ad hoc network emergency equipment is installed in the roof machine room, the antennas are installed on an antenna mast of the machine room, and a core network packet network interface transmits data signals and is connected with one piece of ad hoc network emergency equipment through six types of network cables to pass through a receiving and transmitting antenna (Mimo). The other Ad hoc network emergency equipment is arranged in a small machine room at the position of the iron tower, the antenna is arranged at one half of the height of the iron tower, so that a wireless emergency communication system is established by the two Ad hoc network emergency equipment, the network port of the original covering equipment BTS or BBU is accessed through six types of wires, then 3G, 4G and 5G signals are generated to a user covering antenna through a base station (BTS) or BBU + RRU to achieve the purpose of signal covering, the Ad hoc network emergency equipment at the two sides can be opened only by erecting the antenna and then switching on a power supply or a battery to supply power, and a power switch is turned on, the packet loss ratio of a test result is 0, the equipment is small in size, the communication can be rapidly recovered under a complex environment, and the purpose of mobile phone network signal covering can.
Another application embodiment of the intelligent emergency communication system of the broadband wireless ad hoc network of the invention is as follows: the system comprises a machine room, a machine room antenna, a core network packet network interface, a self-networking emergency device, a double receiving and transmitting antenna and the like, wherein traffic and data capacity are temporarily increased in urban large sports meetings, holidays or celebration activities, emergency rescue and disaster relief are carried out, 2 self-networking emergency devices and 4 antennas are used, visual transmission distance can reach 10KM, one self-networking emergency device is installed in a roof machine room, the antennas are installed on an antenna mast of the machine room, a core network packet network interface transmits data signals and is connected with one self-networking emergency device through six types of. The other piece of ad hoc network emergency equipment is installed in the mobile communication vehicle, the antenna is installed on a holding pole on the top of the mobile vehicle, so that the two pieces of ad hoc network emergency equipment establish a wireless emergency communication system, the two pieces of ad hoc network emergency equipment are connected to a network cable interface of BTS or BBU through six types of network cables, and then 3G, 4G and 5G signals generated by BBU + RRU cover the periphery of the emergency communication vehicle through a vehicle-mounted user covering antenna. The equipment has small volume, is flexible to use, can be conveniently and quickly built and can be quickly evacuated.
Referring to fig. 3, fig. 3 is an internal structure schematic diagram of an ad hoc network emergency communication system 100 according to an embodiment of the present invention, where the core network connection end 1 includes a first transceiver 11, a first FPGA digital circuit 12, a first agile transceiver 13, a plurality of first radio frequency circuits 14, and a plurality of first antennas 15 corresponding to the plurality of radio frequency circuits, one end of the first transceiver 11 is connected to a preset core network, one end of the first FPGA digital circuit 12 is connected to the other end of the first transceiver 11, one end of the first agile transceiver 13 is connected to the other end of the first FPGA digital circuit 12, one end of each first radio frequency circuit 14 is connected to the other end of the first agile transceiver 13, and the other end of each first radio frequency circuit 14 is connected to a corresponding first antenna 15;
referring to fig. 3, the base station connection end 2 is symmetrical to the core network connection end 1 in structure, the base station connection end 2 includes a second transceiver 21, a second FPGA digital circuit 22, a second agile transceiver 23, a plurality of second radio frequency circuits 24, and a plurality of second antennas 25 corresponding to the plurality of radio frequency circuits, one end of the second transceiver 21 is connected to a preset base station or a user coverage end, one end of the second FPGA digital circuit 22 is connected to the other end of the second transceiver 21, one end of the second agile transceiver 23 is connected to the other end of the second FPGA digital circuit 22, one end of each of the second rf circuits 24 is connected to the other end of the second agile transceiver 23, the other end of each of the second rf circuits 24 is connected to a corresponding second antenna 25, and the plurality of second antennas 25 are respectively connected to the plurality of first antennas 15 by wireless.
Preferably, the core network connection terminal 1 further includes a first RJ45 interface 16, one end of the first transceiver 11 is connected to the core network through the first RJ45 interface 16, the base station connection terminal 2 further includes a second RJ45 interface 26, and one end of the second transceiver 21 is connected to the base station or the user coverage terminal through the second RJ45 interface 26.
Referring to fig. 3, the brief working principle of the ad hoc network emergency device is summarized as follows: the RJ45 network ports in the emergency equipment access the self-networking from the grouped network ports of the computer room core network through a GbE transceiver, an FPGA digital circuit comprises a network interface protocol technology, an AES/SHA encryption and decryption technology, a COFDM modulation and demodulation technology, a Mesh technology, a VLAN transparent transmission technology and the like, the agile transceiver is high in integration, two paths of high-performance output linear RF transceiver chips with 20M bandwidths are divided into two paths of TX1/RX1RF circuits, two paths of TX2 and RX2RF circuits for amplification, filtering, a circulator and the like to an antenna end.
And the other Ad hoc network emergency device and the Ad hoc network emergency device accessed to the core network establish a wireless emergency communication system, a receiving and transmitting signal is amplified to a agile transceiver, an FPGA digital circuit and an RJ45 interface of a GbE transceiver through a filter, a circulator, two paths of TX1/RX1RF circuits and TX2 and RX2RF circuits to generate 3G, 4G and 5G network coverage signals, and the target area is covered.
Referring to fig. 4, fig. 4 is a schematic connection diagram of the first FPGA digital circuit 12 according to an embodiment of the present invention, where the first FPGA digital circuit 12 includes a first FPGA chip 121, a first RAM module 122, a first ROM module 123, a first SD card 124, and preferably, a GPS module, a WIFI module, and the like, the first FPGA chip 121 is connected to the other end of the first transceiver 11 and one end of the first agile transceiver 13, and the first RAM module 122, the first ROM module 123, and the first SD card 124 are all connected to the first FPGA chip 121.
In FIG. 4, the receiving sensitivity from the GNSS/BDS/GPS antenna to the NEO-8 module can reach-167 dBm, and the module is applied to receive data RXD1 to the FPGA by a serial port communication protocol. Converting SDIO from WIFI antenna to RTL8723BU module (ieee802.11b/g/n2.4ghz 1T1R) bluetooth 3.0+ HS4.0 includes (SD _ D0, D1, D2, D3, SD _ CMD, SD _ CLK, CS) interfacing to FPGA.
Because the major function of the RJ45 interface is to receive the high-speed GE or FE ethernet interface of the core network, the transceiver chip 88E1116RNNC1 uses advanced mixed signal processing for equalization, echo and crosstalk cancellation, data recovery, and error correction at the gigabit per second data rate; physical layer devices for single gigabit ethernet (GbE) transceivers, and is the smallest single-port gigabit ethernet PHY with integrated passive devices. The transceiver realizes the standard of 1000BASE-T, 100BASE-T and 10BASE-T at the physical layer part of the Ethernet, receiving end data RXD2 and sending end data TXD 2.
Referring to fig. 4, the FPGA chip XC7Z030-1FBG484C fully programmable SoC, memory (256MBDDR3SDRAM, 512MbSPI flash and microSD16G), communication interface: gigabit ethernet, reservation: (USB2.0 and USB3.0, MiniPCie and JTAG and multimedia HDMI, CMOS camera connector and audio input and output), SDIO and TXD2 data of the wifi transceiver module and an FPGA internal data selector (MUX) perform 256-bit encrypted data packets of AES and SHA and an FPGA software algorithm to perform LDPC coding (low density parity check code) to perform channel interleaving processing, and the data interface JESD204B is in serial communication with an AD9371 transmitting end JESD 204B. An I/Q orthogonal demodulation is performed on an internal algorithm data packet after baseband processing is received by an internal frame module after serial communication programming of a serial communication interface JESD204B and an FPGA data communication interface JESD204B of an AD9371 receiving end, the data packet is decrypted by AES/SHA and sent to a data selector (MUX) to be controlled and processed with central data, the data is stored in a RAM, a ROM and an SD card to be communicated with SDIO and a network transceiver RXD2 of a wifi receiving module, and the internal algorithm design meets the network protocol standards of IEEE802.3, IEEE802.3u and IEEE802.3 ab.
Referring to fig. 5, fig. 5 is a schematic structural diagram of the first FPGA digital circuit 12 according to an embodiment of the present invention, where the RJ45 interface mainly functions to receive a high-speed GE or FE ethernet interface of a core network, and the transceiver chip 88E1116RNNC1 performs equalization, echo and crosstalk cancellation, data recovery, and error correction at a gigabit per second data rate; physical layer devices for single gigabit ethernet (GbE) transceivers, and is the smallest single-port gigabit ethernet PHY with integrated passive devices. The transceiver realizes the standards of 1000BASE-T, 100BASE-T and 10BASE-T at the physical layer part of the Ethernet, receiving end data RXD2 and sending end data TXD 2;
FPGA chip XC7Z030-1FBG484C full programmable SoC, memory (256MB DDR3SDRAM, 512Mb SPI flash memory and microsD16G), communication interface: gigabit ethernet, reservation: (USB2.0 and USB3.0, Mini PCIe and JTAG and multimedia HDMI, CMOS camera connector and audio input and output), SDIO and TXD2 data of the wifi transceiver module and an FPGA internal data selector (MUX) perform 256-bit encrypted data packet of AES and SHA and FPGA software algorithm, LDPC coding (low density parity check code) is performed for channel interleaving processing, and the data interface JESD204B is in serial communication with an AD9371 transmitting end JESD 204B. An I/Q orthogonal demodulation is performed on an internal algorithm data packet after baseband processing is received by an internal frame module after serial communication programming of a serial communication interface JESD204B and an FPGA data communication interface JESD204B of an AD9371 receiving end, the data packet is decrypted by AES/SHA and sent to a data selector (MUX) to be controlled and processed with central data, the data is stored in a RAM, a ROM and an SD card to be communicated with SDIO and a network transceiver RXD2 of a wifi receiving module, and the internal algorithm design meets the network protocol standards of IEEE802.3, IEEE802.3u and IEEE802.3 ab.
AD9371 is a high-performance high-integration SDR radio software and Radio Frequency (RF) digital pre-distortion algorithm transceiver integrated chip, the linearization bandwidth reaches 40M, an FPGA digital packet serial interface JESD204B sets two internal local oscillation frequencies of 1.785-1.805 GHz respectively for MIX (frequency mixing), amplifier, DVGA (numerical control variable gain amplifier) and returning DPD to carry out PA linearization and output 250mW power through a chip transmitting part, a DAC (digital-to-analog conversion), LPF, a modulator BPSK and TX1 in the chip and a TX2 channel through software configuration. RX1, RX2 receiving partial channel receives 1.785 ~ 1.805GHz to chip internal low noise amplifier, then to mixer, amplifier, radio frequency DVGA, intermediate frequency LPF, demodulator BPSK to ADC (analog to digital conversion) serial interface JESD204B to FPGA processing. Simultaneously, SPI, CTRL-INT, REF _ CLK, observation receivers ORX1 and ORX2 with 2-path input are arranged, the signals from the emission are received, then attenuators are carried out on the two paths, and the signals enter an incident frequency DVGA, enter a mixer and a demodulator BPSK to ADC (analog-to-digital conversion) serial interface JESD204 SD204B and are processed by FPGA to observe emission output signals; the sniffing receiver SNRRX1 with 3 input paths, RX2 receiving partial channels receive signals from 1.785 GHz to 1.805GHz to an internal amplifier of a chip, a radio frequency DVGA, a mixer, an LPF intermediate frequency LPF, a demodulator BPSK to ADC (analog-to-digital conversion) serial interface JESD204B to an FPGA to process main monitoring network flow, analyzing data packets, monitoring network resource utilization, executing network security operation rules, identifying and analyzing network data and diagnosing and repairing network problems.
The second FPGA digital circuit 22 is symmetrical to the first FPGA digital circuit 12 in structure, and therefore the second FPGA digital circuit 22 includes a second FPGA chip, a second RAM module, a second ROM module, and a second SD card, the second FPGA chip is connected to the other end of the second transceiver 21 and one end of the second agile transceiver 23, respectively, and the second RAM module, the second ROM module, and the second SD card are connected to the second FPGA chip.
Referring to fig. 6, fig. 6 is a schematic structural diagram of the first radio frequency circuit 14 according to an embodiment of the present invention, the core network connection end 1 further includes a first processor 17 and a first voltage boost circuit 18, the first processor 17 is respectively connected to the plurality of first radio frequency circuits 14 and the first FPGA digital circuit 12, and the first processor 17 is further connected to the plurality of first radio frequency circuits 14 through the first voltage boost circuit 18.
Referring to fig. 6, each first rf circuit 14 includes a first adaptive logic circuit 1401, a first transmission digital attenuator 1402, a first transmission gain amplifying tube 1403, a first rf switch chip 1404, a first high linearity push tube 1405, a first rf amplifier group 1406, a first adjusting attenuator 1407, a first circulator 1408, a first main filter 1409, a first transmission detector 1410, a first comparator 1411, a first low noise amplifier 1412, a first primary switch 1413, a first branch filter 1414, a first secondary switch 1415, a first primary reception gain amplifying tube 1416, a first reception digital attenuator 1417, a first secondary reception gain amplifying tube 1418, and a first reception detector 1419;
a first end of the first adaptive logic circuit 1401 is connected to the first agile transceiver 13 through a preset transmission port, a first end of the first transmission digital attenuator 1402 is connected to a second end of the first adaptive logic circuit 1401, one end of the first transmission gain amplification tube 1403 is connected to a second end of the first transmission digital attenuator 1402, a first end of the first rf switch chip 1404 is connected to the other end of the first transmission gain amplification tube 1403, one end of the first high linearity push tube 1405 is connected to a second end of the first rf switch chip 1404, one end of the first rf amplifier group 1406 is connected to the other end of the first high linearity push tube 1405, one end of the first adjusting attenuator 1407 is connected to the other end of the first rf amplifier group 1406, the other end of the first adjusting attenuator 1407 is connected to the first agile transceiver 13 through a preset connection port, a first terminal of the first circulator 1408 is connected to the other terminal of the first group of rf amplifiers 1406, one terminal of the first main filter 1409 is connected to a second terminal of the first circulator 1408, the other terminal of the first main filter 1409 is connected to the first antenna 15 through a predetermined antenna port, a third terminal of the first circulator 1408 is connected to one terminal of the first low noise amplifier 1412, the other terminal of the first low noise amplifier 1412 is connected to a first terminal of a first primary switch 1413, a second terminal of the first primary switch 1413 is connected to one terminal of a first branch filter 1414, the other terminal of the first branch filter 1414 is connected to a first terminal of the first secondary switch 1415, a second terminal of the first secondary switch 1415 is connected to one terminal of a first primary receiving gain amplifying tube 1416, the other terminal of the first primary receiving gain amplifying tube 1416 is connected to a first terminal of the first receiving digital attenuator 1417, a second end of the first receiving digital attenuator 1417 is connected to a first end of the first secondary receiving gain amplifying tube 1418, and a second end of the first secondary receiving gain amplifying tube 1418 is connected to the first agile transceiver 13 through a preset receiving port;
one end of the first comparator 1411 is connected to the third end of the first adaptive logic circuit 1401, and the first emission detector 1410 is respectively connected to the other end of the first comparator 1411, the other end of the first rf amplifier group 1406, the third end of the first emission digital attenuator 1402, the third end of the first rf switch chip 1404, and the first processor 17;
one end of the first receiving detector 1419 is connected to the third end of the first secondary receiving gain amplifying tube 1418, the first processor 17 is further connected to the other end of the first receiving detector 1419, the third end of the first receiving digital attenuator 1417, the third end of the first primary switch 1413, the third end of the first secondary switch 1415 and one end of the first boosting circuit 18, and the other end of the first boosting circuit 18 is connected to the other end of the first rf amplifier group 1406.
Referring to fig. 6, the uplink and downlink principles of the present invention are as follows:
1. the TX1+ TX 0-difference of a downlink AD9371 selects a 20M bandwidth frequency band within a frequency band (1.785-1.805G) range (which can be configured according to customer requirements) of a TX1-OUT output by a balun, and then the frequency band is controlled from TX1-IN to automatic gain control, wherein the main functions are over-power protection, ATT attenuation and gain automatic attenuation, and the high-precision digital attenuation chip PE4312 adjusts gain matching IN a range of 0.5-31.5 + (0.10+ 1% x Atten) dB precision @ 1-2 GHz, and then the gain is transmitted to a TX-AMP P105 (gain amplifier tube) for 15dB, and the noise coefficient: 1.9dB, P1dB 19.3.3 dBmat 1.785-1.805 GHz amplifier tubes, then, the RF SPDT switch chip PE42551, high speed switch, gate and phase lag elimination, low insertion loss 0.65dB, isolation 29dB, 2W high linearity push tube TQM7P9104 gain 15dB, P1dB +32.8dBm at 1.0-2 GHz, the last power amplifier adopts the Doherty technology, 12-watt LDMOSPTFA220121M power supply voltage +28V, LTM4609 module from +12V to +28V, power supply of the power amplifier tube, main and auxiliary tube output power 37dBm, through circulator, the main action of 0-OUT signal can not enter RX0-IN channel, the TX1 is guaranteed to be isolated to TX1 channel, IN order to guarantee that the difference loss is less than 1dB, the frequency control is IN the selected frequency band range, the filter insertion loss is less than 2.5 OUT-band rejection high, and the output power 33.5dBm reaches the antenna interface.
2. IN the frequency band (1.785-1.805G) range of the TX2+ TX 2-difference of the other AD9371 of the downlink, a 40M bandwidth frequency band is selected by a client requirement IN the output TX2-OUT frequency band of the balun, and the automatic gain control is carried OUT from a TX2 IN to the automatic gain control, wherein the main functions are over-power protection, ATT attenuation and gain automatic attenuation, and the high-precision digital attenuation chip PE4312 adjusts gain matching IN the range of 0.5-31.5 +/-0.10 + 1% xAtten dB precision @ 1-2 GHz, and sends the gain matching to a TX-AMP P105 (gain amplifier tube) for 15dB and has the noise coefficient: after an amplifier tube with the gain of 1.9dB, the gain of P105 dB, the gain of P1dB 19.3.3 dBm at 1.0-2 GHz enters a radio frequency SPDT switch chip PE42551, high-speed switching is carried OUT, gate and phase lag are eliminated, the low insertion loss is 0.65dB, the isolation is 29dB, 2W high-linearity pushing tube TWM 7P9104 gain 15dB and P1dB +32.8dBm at 1.785-1.805 GHz are carried OUT, the last-stage power amplifier adopts the Doherty technology, the power supply voltage of 12-watt LDMOSPTFA220121M is +28V, the LTM4609 module boosts the voltage from +12V to +28V to provide power for the last-stage amplifier tube, the output power of a main tube and an auxiliary tube is 37dBm, a TX 0-IN signal mainly acts through a circulator cannot enter an RX0-IN channel, the RX1 is ensured to isolate the TX1 channel, IN order to ensure that the difference loss is less than 1dB, the frequency control is selected within the frequency band, the insertion loss of a filter is less than 2.5 OUT-band.
3. The output of a downlink TX1 control part TX1 can be input into a range of-52 dBm to +8dBm for 60dB detection through a DET (detection) AD8362, a voltage comparator meets the requirement of ALC automatic power control, the other path of the output reaches the ARM detection power, the gain of a TX1 channel is automatically adjusted through ATT, and an RX1 channel is switched off through an RX1 two switching devices HMC 545.
4. The output of a downlink TX2 control part TX2 can be input into a range of-52 dBm to +8dBm by a DET (detection) AD8362 to reach 60dB, a voltage comparator meets the requirement of ALC automatic power control, the other path of the output reaches ARM detection power, the gain of a TX1 channel is automatically adjusted through ATT, and an RX2 channel is switched off by two RX2 switching devices HMC 545.
5. The uplink is input into a frequency band (1.785-1.805) GHz of RX1-IN by ANT1, the required frequency band (1785-1805) MHz is screened by a filter, an RX1-IN channel is less than 1dB, the insertion loss of an input circulator is less than 0.5dB, LNA (low noise amplification) TQP3M9037 noise coefficient is 0.4, gain is 20dB, an output IP3 reaches 35dBm, high linearity is achieved, the noise coefficient of the whole receiving channel is less than 3.0, an RX1-IN channel radio frequency SPDT switching device HMC545 turns off the isolation degree of 31dB, a secondary filter is performed, an input SPDT switching device HMC545 is synchronously closed, two radio frequency switches are enabled to avoid the TX1 channel from being connected IN series with the RX1 channel, the RX1-AMP (gain amplifier tube) is fed with the gain of 15dB, at 1.0-2 GHz is output by the amplifier tube, ATT attenuation is performed, automatic gain attenuation is performed, a high-precision digital attenuation chip PE4312 is adjusted IN a step gain range of 0.5-1.5 +/-1.10 + 1% and Atten (Atten) gain matching range of 1%, the amplifier tube output RX1_ OUT sent to RX1-AMP (gain amplifier tube) P105 with the gain of 15dB and P1dB 19.3.3 dBm at 1-2 GHz passes through the balun to RX1+, and RX1-AD9371 input ends.
6. The uplink is input into a frequency band (1.785-1.805) GHz of RX2-IN by ANT2, the required frequency band (1785-1805) MHz is screened by a filter, an RX1-IN channel is less than 1dB, the insertion loss of an input circulator is less than 0.5dB, LNA (low noise amplification) TQP3M9037 noise coefficient is 0.4, gain is 20dB, an output IP3 reaches 35dBm, high linearity is achieved, the noise coefficient of the whole receiving channel is less than 3.0, an RX1-IN channel radio frequency SPDT switch device HMC545 is used for switching off the isolation degree of 31dB, a secondary filter is performed, an input SPDT switch device HMC545 is used for synchronously switching off two radio frequency switches, the TX1 channel is prevented from being serially connected into an RX1 channel, the RX2-AMP (gain amplifier tube) P105 gain 15dB, the noise coefficient is 1.9, PdB19.3dBm 1.5-1.8 GHz amplifier tube output, the ATT attenuation is automatically adjusted, the gain attenuation degree is adjusted IN a high-precision range of At0.10.12% plus 0 to 1.10 plus 0% plus 0 deg. 10 plus 0 deg. PE (ATT) chip, the output RX2OUT of the amplifier tube which is sent into RX2-AMP (gain amplifier tube) P105 and has the gain of 15dB and the noise coefficient of 1.9dB P1dB 19.3.3 dBm atl-2.0 GHz passes through the balun to RX2+, and RX2-AD9371 input ends.
7. The output of the control part of the uplink RX1 can be input into a range from-52 dBm to +8dBm by a DET (detection) AD8362 to reach 60dB, the voltage proportion is processed by an ARM to control ATT to ATT attenuation, gain automatic attenuation is realized, a high-precision digital attenuation chip PE4312 adjusts gain matching in a range from 0.5 to 31.5 +/-0.10 + 1% xAtten dB precision @1 to 2GHz, the input gain of the RX1 is controlled, an RX1 receiving signal is detected and input into the ARM to control a TX1 SPDT switch chip PE42551, and a TX1 signal is turned off at a high speed. The ARM communicates with the FPGA through a data port.
8. The output of the control part of the uplink RX2 can be input into a range from-52 dBm to +8dBm by a DET (detection) AD8362 to reach 60dB, the voltage proportion is processed by an ARM to control ATT to ATT attenuation, gain automatic attenuation is realized, a high-precision digital attenuation chip PE4312 adjusts gain matching in a range from 0.5 to 31.5 +/-0.10 + 1% x Atten dB precision @1 to 2GHz, the input gain of the RX2 is controlled, an RX2 receiving signal is detected and input into the ARM to control a TX2SPDT switch chip PE42551, and a TX2 signal is turned off at a high speed. The ARM communicates with the FPGA through a data port.
Because the base station connection end 2 and the core network connection end 1 are symmetrical in structure, the base station connection end 2 further includes a second processor and a second boost circuit, the second processor is respectively connected to the plurality of second radio frequency circuits 24 and to the second FPGA digital circuit 22, and the second processor is further connected to the plurality of second radio frequency circuits 24 through the second boost circuit.
Each second radio frequency circuit 24 includes a second adaptive logic circuit, a second transmission digital attenuator, a second transmission gain amplifier tube, a second radio frequency switch chip, a second high linearity push tube, a second radio frequency amplifier group, a second adjusting attenuator, a second circulator, a second main path filter, a second transmission detector, a second comparator, a second low noise amplifier, a second primary switch, a second branch filter, a second secondary switch, a second primary reception gain amplifier tube, a second reception digital attenuator, a second secondary reception gain amplifier tube, and a second reception detector;
the first end of the second adaptive logic circuit is connected to the second agile transceiver 23 through a preset transmitting port, the first end of the second transmitting digital attenuator is connected to the second end of the second adaptive logic circuit, one end of the second transmitting gain amplifying tube is connected to the second end of the second transmitting digital attenuator, the first end of the second rf switch chip is connected to the other end of the second transmitting gain amplifying tube, one end of the second high linearity push tube is connected to the second end of the second rf switch chip, one end of the second rf amplifier group is connected to the other end of the second high linearity push tube, one end of the second adjusting attenuator is connected to the other end of the second rf amplifier group, the other end of the second adjusting attenuator is connected to the second agile transceiver 23 through a preset connecting port, a first end of the second circulator is connected to the other end of the second rf amplifier group, one end of the second main path filter is connected to a second end of the second circulator, the other end of the second main path filter is connected to the second antenna 25 through a predetermined antenna port, a third end of the second circulator is connected to one end of the second low noise amplifier, the other end of the second low noise amplifier is connected to a first end of a second one-stage switch, a second end of the second one-stage switch is connected to one end of the second branch filter, the other end of the second branch filter is connected to a first end of the second two-stage switch, a second end of the second two-stage switch is connected to one end of the second one-stage receive gain amplifier tube, and the other end of the second one-stage receive gain amplifier tube is connected to the first end of the second receive digital attenuator, the second end of the second receiving digital attenuator is connected to the first end of the second secondary receiving gain amplifying tube, and the second end of the second secondary receiving gain amplifying tube is connected to the second agile transceiver 23 through a preset receiving port;
one end of the second comparator is connected to the third end of the second adaptive logic circuit, and the second emission detector is respectively connected to the other end of the second comparator, the other end of the second radio frequency amplifier group, the third end of the second emission digital attenuator, the third end of the second radio frequency switch chip, and the second processor;
one end of the second receiving detector is connected to the third end of the second secondary receiving gain amplifying tube, the second processor is further connected to the other end of the second receiving detector, the third end of the second receiving digital attenuator, the third end of the second primary switch, the third end of the second secondary switch and one end of the second booster circuit, and the other end of the second booster circuit is connected to the other end of the second radio frequency amplifier group.
On the other hand, there is provided a communication method of the ad hoc network emergency communication system 100, which employs the ad hoc network emergency communication system 100 as described above, the communication method including steps S1-S3:
s1, arranging a core network connecting end 1 at a preset core network to establish communication connection between the core network connecting end 1 and the core network;
s2, arranging a base station connecting end 2 at a preset base station or user coverage end to establish communication connection between the base station connecting end 2 and the base station or user coverage end;
s3, establishing wireless communication connection between the core network connection end 1 and the base station connection end 2, thereby realizing signal coverage of a base station or a user coverage end.
The protection core technical key points of the intelligent emergency communication system of the broadband wireless ad hoc network are as follows:
1. the wireless SDR technology is adopted, the setting is avoided, the flexibility and the maneuverability are realized, the operation is simple, and the startup is started;
2. the Cofdm technology has the advantages of long error code resistance transmission distance and high anti-interference performance, has the capability of transmitting signals under clutter interference, and intelligently and adaptively adjusts the signal strength of a system at any time and any place;
3. the Mesh technology applies ad-hoc dynamic routing, multiple self-organizing multi-hop and automatic relay in the city to achieve farther coverage;
4. the network response speed is high, the time delay of a packet bearer network is small (less than or equal to 5ms), and the packet loss rate is basically 0 after practical verification and network hanging test;
5. fast moving, dynamic topology: the system design emphasizes the mobility of multiple nodes, and routes can be automatically reconstructed along with the change of the topological connection relation (topological structure) of the multiple nodes, and the real-time response is realized. The data communication is not limited by the change of the system topology;
6. the connection protocol of the core network packet interface and the self-organizing network emergency equipment, and the connection protocol of the self-organizing network emergency equipment and BTS or BBU.
7. The network standard protocol is adopted to design key indexes of QoS (quality of service) meeting 3G, 4G and 5G base stations and technical requirements of IP telephone gateway equipment.
8. VLAN transparent transmission and link self- adaption 3G, 4G and 5G network signals can quickly establish a low-cost emergency communication network.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (10)

1. An ad-hoc network emergency communication system, comprising:
the core network connection end comprises a first transceiver, a first FPGA digital circuit, a first agile transceiver, a plurality of first radio frequency circuits and a plurality of first antennas corresponding to the first radio frequency circuits, one end of the first transceiver is connected to a preset core network, one end of the first FPGA digital circuit is connected to the other end of the first transceiver, one end of the first agile transceiver is connected to the other end of the first FPGA digital circuit, one end of each first radio frequency circuit is connected to the other end of the first agile transceiver, and the other end of each first radio frequency circuit is connected to the corresponding first antenna;
the base station comprises a base station connecting end, wherein the base station connecting end comprises a second transceiver, a second FPGA digital circuit, a second agile transceiver, a plurality of second radio frequency circuits and a plurality of second antennas corresponding to the second radio frequency circuits, one end of the second transceiver is connected to a preset base station or a user coverage end, one end of the second FPGA digital circuit is connected to the other end of the second transceiver, one end of the second agile transceiver is connected to the other end of the second FPGA digital circuit, one end of each second radio frequency circuit is connected to the other end of the second agile transceiver, the other end of each second radio frequency circuit is connected to a corresponding second antenna, and the plurality of second antennas are respectively connected to the plurality of first antennas in a wireless mode.
2. The ad hoc network emergency communication system according to claim 1, wherein the core network connection terminal further comprises a first RJ45 interface, and one end of the first transceiver is connected to the core network through the first RJ45 interface.
3. The ad hoc network emergency communication system of claim 1, wherein said base station connection terminal further comprises a second RJ45 interface, one end of said second transceiver being connected to said base station or user coverage terminal through said second RJ45 interface.
4. The ad hoc network emergency communication system according to claim 1, wherein the core network connection end further comprises a first processor and a first boost circuit, the first processor is respectively connected to the plurality of first radio frequency circuits and to the first FPGA digital circuit, and the first processor is further connected to the plurality of first radio frequency circuits through the first boost circuit.
5. The ad hoc network emergency communication system according to claim 1 or 4, wherein the base station connection end further comprises a second processor and a second boost circuit, the second processor is respectively connected to the plurality of second radio frequency circuits and to the second FPGA digital circuit, and the second processor is further connected to the plurality of second radio frequency circuits through the second boost circuit.
6. The ad hoc network emergency communication system according to claim 4, wherein each first radio frequency circuit comprises a first adaptive logic circuit, a first transmission digital attenuator, a first transmission gain amplifying tube, a first radio frequency switch chip, a first high linearity push tube, a first radio frequency amplifier group, a first tuning attenuator, a first circulator, a first main path filter, a first transmission detector, a first comparator, a first low noise amplifier, a first primary switch, a first branch filter, a first secondary switch, a first primary reception gain amplifying tube, a first reception digital attenuator, a first secondary reception gain amplifying tube and a first reception detector;
the first end of the first adaptive logic circuit is connected to the first agile transceiver through a preset transmitting port, the first end of the first transmitting digital attenuator is connected to the second end of the first adaptive logic circuit, one end of the first transmitting gain amplifying tube is connected to the second end of the first transmitting digital attenuator, the first end of the first radio frequency switch chip is connected to the other end of the first transmitting gain amplifying tube, one end of the first high linearity push tube is connected to the second end of the first radio frequency switch chip, one end of the first radio frequency amplifier group is connected to the other end of the first high linearity push tube, one end of the first adjusting attenuator is connected to the other end of the first radio frequency amplifier group, and the other end of the first adjusting attenuator is connected to the first agile transceiver through a preset connecting port, a first end of the first circulator is connected to the other end of the first rf amplifier group, one end of the first main path filter is connected to a second end of the first circulator, the other end of the first main path filter is connected to the first antenna through a predetermined antenna port, a third end of the first circulator is connected to one end of the first low noise amplifier, the other end of the first low noise amplifier is connected to a first end of a first primary switch, a second end of the first primary switch is connected to one end of the first branch filter, the other end of the first branch filter is connected to a first end of the first secondary switch, a second end of the first secondary switch is connected to one end of the first primary receiving gain amplifying tube, and the other end of the first primary receiving gain amplifying tube is connected to a first end of the first receiving digital attenuator, the second end of the first receiving digital attenuator is connected to the first end of the first secondary receiving gain amplifying tube, and the second end of the first secondary receiving gain amplifying tube is connected to the first agile transceiver through a preset receiving port;
one end of the first comparator is connected to the third end of the first adaptive logic circuit, and the first emission detector is respectively connected to the other end of the first comparator, the other end of the first radio frequency amplifier group, the third end of the first emission digital attenuator, the third end of the first radio frequency switch chip and the first processor;
one end of the first receiving detector is connected to the third end of the first secondary receiving gain amplifying tube, the first processor is further connected to the other end of the first receiving detector, the third end of the first receiving digital attenuator, the third end of the first primary switch, the third end of the first secondary switch and one end of the first booster circuit, and the other end of the first booster circuit is connected to the other end of the first radio frequency amplifier group.
7. The ad hoc network emergency communication system according to claim 5, wherein each second radio frequency circuit comprises a second adaptive logic circuit, a second transmission digital attenuator, a second transmission gain amplifying tube, a second radio frequency switch chip, a second high linearity pushing tube, a second radio frequency amplifier group, a second adjusting attenuator, a second circulator, a second main path filter, a second transmission detector, a second comparator, a second low noise amplifier, a second primary switch, a second branch filter, a second secondary switch, a second primary reception gain amplifying tube, a second reception digital attenuator, a second secondary reception gain amplifying tube and a second reception detector;
the first end of the second adaptive logic circuit is connected to the second agile transceiver through a preset transmitting port, the first end of the second transmitting digital attenuator is connected to the second end of the second adaptive logic circuit, one end of the second transmitting gain amplifying tube is connected to the second end of the second transmitting digital attenuator, the first end of the second radio frequency switch chip is connected to the other end of the second transmitting gain amplifying tube, one end of the second high linearity push tube is connected to the second end of the second radio frequency switch chip, one end of the second radio frequency amplifier group is connected to the other end of the second high linearity push tube, one end of the second adjusting attenuator is connected to the other end of the second radio frequency amplifier group, and the other end of the second adjusting attenuator is connected to the second agile transceiver through a preset connecting port, a first end of the second circulator is connected to the other end of the second rf amplifier group, one end of the second main path filter is connected to a second end of the second circulator, the other end of the second main path filter is connected to the second antenna through a predetermined antenna port, a third end of the second circulator is connected to one end of the second low noise amplifier, the other end of the second low noise amplifier is connected to a first end of a second one-stage switch, a second end of the second one-stage switch is connected to one end of the second branch filter, the other end of the second branch filter is connected to a first end of the second two-stage switch, a second end of the second two-stage switch is connected to one end of the second one-stage receive gain amplifier tube, and the other end of the second one-stage receive gain amplifier tube is connected to a first end of the second receive digital attenuator, the second end of the second receiving digital attenuator is connected to the first end of the second secondary receiving gain amplifying tube, and the second end of the second secondary receiving gain amplifying tube is connected to the second agile transceiver through a preset receiving port;
one end of the second comparator is connected to the third end of the second adaptive logic circuit, and the second emission detector is respectively connected to the other end of the second comparator, the other end of the second radio frequency amplifier group, the third end of the second emission digital attenuator, the third end of the second radio frequency switch chip, and the second processor;
one end of the second receiving detector is connected to the third end of the second secondary receiving gain amplifying tube, the second processor is further connected to the other end of the second receiving detector, the third end of the second receiving digital attenuator, the third end of the second primary switch, the third end of the second secondary switch and one end of the second booster circuit, and the other end of the second booster circuit is connected to the other end of the second radio frequency amplifier group.
8. The ad hoc network emergency communication system according to claim 1, wherein the first FPGA digital circuit comprises a first FPGA chip, a first RAM module, a first ROM module and a first SD card, the first FPGA chip is connected to the other end of the first transceiver and one end of the first agile transceiver respectively, and the first RAM module, the first ROM module and the first SD card are all connected to the first FPGA chip.
9. The ad hoc network emergency communication system according to claim 1, wherein the second FPGA digital circuit comprises a second FPGA chip, a second RAM module, a second ROM module and a second SD card, the second FPGA chip is connected to the other end of the second transceiver and one end of the second agile transceiver respectively, and the second RAM module, the second ROM module and the second SD card are connected to the second FPGA chip.
10. A communication method of an ad hoc network emergency communication system, wherein the ad hoc network emergency communication system according to any one of claims 1 to 9 is used, the communication method comprising:
arranging a core network connecting end at a preset core network to establish communication connection between the core network connecting end and the core network;
arranging a base station connecting end at a preset base station or user coverage end to establish communication connection between the base station connecting end and the base station or the user coverage end;
and establishing wireless communication connection between the core network connecting end and the base station connecting end, thereby realizing signal coverage of the base station or the user coverage end.
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