CN107394004A - 一种多光谱双芯片红外探测器的底部填充方法 - Google Patents

一种多光谱双芯片红外探测器的底部填充方法 Download PDF

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CN107394004A
CN107394004A CN201710509717.2A CN201710509717A CN107394004A CN 107394004 A CN107394004 A CN 107394004A CN 201710509717 A CN201710509717 A CN 201710509717A CN 107394004 A CN107394004 A CN 107394004A
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multispectral
infrared detector
dual chip
chip infrared
filling method
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CN107394004B (zh
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王骏
王成刚
东海杰
谢珩
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CETC 11 Research Institute
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Abstract

本发明提供了一种多光谱双芯片红外探测器的底部填充方法，所述方法包括：将填充剂填充至预设的填充区域，预设的填充区域为两芯片之间的缝隙；将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化。本发明实施例提供的多光谱双芯片红外探测器的底部填充方法，通过对填充剂填充区域的摸索，并使用一定的真空环境进行胶水固化，解决了多光谱双芯片红外探测器底部填充时填充不饱满的问题。

Description

一种多光谱双芯片红外探测器的底部填充方法
技术领域
本发明涉及红外探测器领域，特别涉及一种多光谱双芯片红外探测器的底部填充方法。
背景技术
红外焦平面探测器广泛应用于航空、航天、光学遥感、监控及测量领域，大视场高分辨率成像作为遥感器发展的一个重要方向，为了满足航天用红外成像系统长焦距、大视场、高分辨率以及多光谱探测的要求，同时基于碲镉汞材料特性及工艺技术难度，目前采用长线列双探测器芯片的倒装互连方法。在进行两个长线列探测器芯片互连工艺中，将两个长线列探测器芯片分别互连到单读出电路模块上的对应位置，从而实现了两个探测器芯片在单读出电路模块上的并排互连，图1为现有技术中多谱段碲镉汞混成芯片制造过程示意图。
航天用红外成像系统另外一个重要的要求是高可靠性、长寿命。影响碲镉汞探测器组件寿命的因素较多，其中探测器芯片寿命是最重要的一项，经过多年的技术研究，目前通过芯片底部填充技术可以大幅提高探测器芯片寿命，因此底部填充技术成为连接芯片与读出电路应用可靠性保证的重要环节，是器件满足长寿面和抵抗极端恶劣环境要求的关键步骤。
图2为现有技术中底部填充工艺示意图，在图2中，Top die-Flip chip表示芯片，Bottom die-Wire bonded表示电路，Package substrate表示铟球。但是在本申请的多光谱双芯片红外探测器混成芯片是由两个长线列探测器芯片分别互连到单读出电路模块上的对应位置，在进行下一步底部填充的时候时，通过毛细作用让胶水将探测器芯片与读出电路之间的缝隙填满，由于多了中间的探测器与探测器之间的缝隙，从而引起填充不饱满的现象。
发明内容
为了能够有效解决现有技术中多光谱双芯片红外探测器底部填充时填充不饱满的问题，本发明提供了一种多光谱双芯片红外探测器的底部填充方法。
本发明提供的一种多光谱双芯片红外探测器的底部填充方法，包括以下步骤：
将填充剂填充至预设的填充区域，所述预设的填充区域为两芯片之间的缝隙；
将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，所述预设的填充区域为两芯片之间缝隙的1/3处～2/3处。
更加具体的，两芯片之间的缝隙为100～200微米。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，所述填充剂为环氧树脂。
更加具体的，所述填充剂的用量为5～6mg。
作为本发明一种具体的实施方式，将填充剂填充至预设的填充区域，所述预设的填充区域为两芯片之间的缝隙，包括：
将5～6mg的环氧树脂填充至两芯片之间缝隙的1/3处～2/3处，所述两芯片之间的缝隙为100～200微米。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化，包括：
将填充结束后的多光谱双芯片红外探测器放置在100～150mba的真空环境中，加热至90～100℃使填充剂固化。
本发明的有益效果如下：
本发明实施例提供的多光谱双芯片红外探测器的底部填充方法，通过对填充剂填充区域及填充量的摸索，并使用一定的真空环境进行胶水固化，解决了多光谱双芯片红外探测器底部填充时填充不饱满的问题。
附图说明
图1为现有技术中多谱段碲镉汞混成芯片制造过程示意图；
图2为现有技术中底部填充工艺示意图；
图3是本发明方法实施例的多光谱双芯片红外探测器底部填充方法的流程图；
其中，1、读出电路；2、读出电路芯片；3、碲镉汞外延材料；4、碲镉汞器件芯片；5、碲镉汞芯片；6、混成芯片模块；7、拼接探测器。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
为了能够有效解决现有技术中多光谱双芯片红外探测器底部填充时填充不饱满的问题，本发明提供了一种多光谱双芯片红外探测器的底部填充方法，以下结合附图对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不限定本发明。
根据本发明的方法实施例，提供了一种多光谱双芯片红外探测器的底部填充方法，图3是本发明方法实施例的多光谱双芯片红外探测器底部填充方法的流程图，如图3所示，本发明方法实施例的多光谱双芯片红外探测器的底部填充方法，包括以下步骤：
S301：将填充剂填充至预设的填充区域，所述预设的填充区域为两芯片之间的缝隙。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，所述预设的填充区域为两芯片之间缝隙的1/3处～2/3处。
更加具体的，两芯片之间的缝隙为100～200微米。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，所述填充剂为环氧树脂。
更加具体的，所述填充剂的用量为5～6mg。
S302：将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化。
具体的，在本发明所述的多光谱双芯片红外探测器的底部填充方法中，将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化，包括：
将填充结束后的多光谱双芯片红外探测器放置在100～150mba的真空环境中，加热至90～100℃使填充剂固化。
为了详细的说明本发明的方法实施例，给出以下实例。
步骤A：选用粘度系数为2000～2500mPa.s的底部填充剂，均匀脱泡。
步骤B：根据多谱段碲镉汞混成芯片的尺寸，选取双芯片红外探测器混成芯片两个碲镉汞芯片中间缝隙任意一端三分之一处为底部填充起始点；另外一段三分之一处为底部填充截止点。
步骤C：将5～6mg的胶水按照点胶路径填充到多谱段碲镉汞混成芯片上。
步骤D：将点完胶后的多谱段碲镉汞混成芯片放在100～150mba的真空环境中，加热至90～100℃使胶水固化。
本发明实施例提供的多光谱双芯片红外探测器的底部填充方法，通过对填充剂填充区域及填充量的摸索，并使用一定的真空环境进行胶水固化，解决了多光谱双芯片红外探测器底部填充时填充不饱满的问题。
若在对该种多光谱双芯片红外探测器的底部填充方法进行操作时，未按照本发明提供的方法进行操作。例如将步骤B替换为以下步骤：选取双芯片红外探测器混成芯片两个碲镉汞芯片一边进行底部填充，而不是在中间缝隙进行底部填充，则会造成底部填充胶流动不到另外一个芯片的情况发生，造成裂片。再如将步骤D替换为以下步骤：未将点完胶后的多谱段碲镉汞混成芯片放在100-150mba的真空环境中，而是放在正常大气压下，加热90～100℃使胶水固化。这样的操作会使底部填充不饱满，出现气泡，造成碲镉汞材料断裂的情况出现。
以上所述仅为本发明的实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (7)

1.一种多光谱双芯片红外探测器的底部填充方法，其特征在于，包括以下步骤：
将填充剂填充至预设的填充区域，所述预设的填充区域为两芯片之间的缝隙；
将填充结束后的多光谱双芯片红外探测器放置在真空环境中使所述填充剂固化。
2.如权利要求1所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，所述预设的填充区域为两芯片之间缝隙的1/3～2/3处。
3.如权利要求2所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，所述两芯片之间的缝隙为100～200微米。
4.如权利要求1所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，所述填充剂为环氧树脂。
5.如权利要求3所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，所述填充剂的用量为5～6mg。
6.如权利要求1所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，将填充剂填充至预设的填充区域，所述预设的填充区域为两芯片之间的缝隙，包括：
将5～6mg的环氧树脂填充至两芯片之间缝隙的1/3处～2/3处，所述两芯片之间的缝隙为100～200微米。
7.如权利要求1所述的多光谱双芯片红外探测器的底部填充方法，其特征在于，将填充结束后的多光谱双芯片红外探测器放置在真空环境中使填充剂固化，包括：
将填充结束后的多光谱双芯片红外探测器放置在100～150mba的真空环境中，加热至90～100℃使填充剂固化。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508854A (zh) * 2020-04-10 2020-08-07 中国电子科技集团公司第十一研究所 一种混成芯片的制备方法及混成芯片

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101432876A (zh) * 2006-04-27 2009-05-13 住友电木株式会社 半导体器件和制造半导体器件的方法
CN101580684A (zh) * 2009-06-05 2009-11-18 烟台德邦科技有限公司 一种低温快速固化底部填充胶及其制备方法
CN101899195A (zh) * 2009-06-01 2010-12-01 信越化学工业株式会社 坝料组合物及多层半导体装置的制造方法
CN102623441A (zh) * 2011-01-28 2012-08-01 三星电子株式会社 半导体装置及其制造方法
CN202423279U (zh) * 2011-12-29 2012-09-05 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN104979225A (zh) * 2015-05-19 2015-10-14 深圳创维－Rgb电子有限公司 一种防止bga ic虚焊的底部填充方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101432876A (zh) * 2006-04-27 2009-05-13 住友电木株式会社 半导体器件和制造半导体器件的方法
CN101899195A (zh) * 2009-06-01 2010-12-01 信越化学工业株式会社 坝料组合物及多层半导体装置的制造方法
US20100304536A1 (en) * 2009-06-01 2010-12-02 Kazuaki Sumita Dam composition for use with multilayer semiconductor package underfill material, and fabrication of multilayer semiconductor package using the same
CN101580684A (zh) * 2009-06-05 2009-11-18 烟台德邦科技有限公司 一种低温快速固化底部填充胶及其制备方法
CN102623441A (zh) * 2011-01-28 2012-08-01 三星电子株式会社 半导体装置及其制造方法
CN202423279U (zh) * 2011-12-29 2012-09-05 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN104979225A (zh) * 2015-05-19 2015-10-14 深圳创维－Rgb电子有限公司 一种防止bga ic虚焊的底部填充方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508854A (zh) * 2020-04-10 2020-08-07 中国电子科技集团公司第十一研究所 一种混成芯片的制备方法及混成芯片

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