CN107393943B - 显示装置及制造显示装置的方法 - Google Patents
显示装置及制造显示装置的方法 Download PDFInfo
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- CN107393943B CN107393943B CN201710343227.XA CN201710343227A CN107393943B CN 107393943 B CN107393943 B CN 107393943B CN 201710343227 A CN201710343227 A CN 201710343227A CN 107393943 B CN107393943 B CN 107393943B
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- H—ELECTRICITY
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- H—ELECTRICITY
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Abstract
一种显示装置及制造显示装置的方法,所述装置包括在基板上的多个像素,其中多个像素中的第一像素包括:在第一方向上延伸的扫描线,在与第一方向交叉的第二方向上延伸的多条配线,在扫描线和多条配线之间的至少一个绝缘层;电连接到扫描线和多条配线的薄膜晶体管,以及电连接到薄膜晶体管的像素电极,其中多条配线中的至少一条配线包括:在第二方向上彼此隔开的第一线和第二线,以及将第一线和第二线电连接的连接线,至少一个绝缘层在连接线与第一线和第二线之间。
Description
相关申请的交叉引用
2016年5月16日在韩国知识产权局提交的题为“显示装置”的第10-2016-0059793号韩国专利申请的全部内容通过引用合并于此。
技术领域
实施例涉及一种显示装置及制造显示装置的方法。
背景技术
近来,随着半导体技术的快速发展,显示装置的性能已有所改善,例如增大了显示装置的屏幕尺寸并减轻了显示装置的重量,因此显示装置的需求已急剧增加。
作为显示装置之一的有机发光显示装置可以包括两个电极以及布置在该两个电极之间的有机发光层。当通过一个电极注入的电子和通过另一电极注入的空穴在有机发光层中彼此结合时,形成激子,以便激子发射出能量和光。
有机发光显示装置可以包括多个像素,该多个像素包括作为自发光器件的有机发光二极管。每个像素可以包括多个薄膜晶体管以及一个或多个用于驱动该有机发光二极管的电容器。
发明内容
实施例涉及一种显示装置。
实施例可以通过提供一种显示装置来实现,所述显示装置包括位于基板上的多个像素,其中多个像素中的第一像素包括:扫描线,在第一方向上延伸;多条配线,在与第一方向交叉的第二方向上延伸;至少一个绝缘层,位于扫描线和多条配线之间;薄膜晶体管,电连接到扫描线和多条配线;像素电极,电连接到薄膜晶体管,其中多条配线中的至少一条配线包括:第一线和第二线,在第二方向上彼此隔开;以及连接线,将第一线和第二线电连接,至少一个绝缘层位于连接线与第一线和第二线之间。
第一线和第二线可以包括与像素电极相同的材料。
连接线可以在第一线和第二线的下方,并且连接线可以包括与扫描线相同的材料。
连接线可以与像素电极重叠。
像素电极可以包括将连接线覆盖的至少一个开口。
像素电极的一部分可以在第一线和第二线之间延伸。
显示装置还可以包括:存储电容器,电连接到薄膜晶体管,所述存储电容器包括顺序堆叠的第一存储电极、介电层和第二存储电极。
第一存储电极可以包括与连接线相同的材料。
第二存储电极可以包括与像素电极相同的材料。
第二存储电极可以是像素电极的一部分。
至少一个绝缘层可以包括介电层。
多条配线可以包括:第一配线,被设置在第一存储电极的一侧;以及第二配线,被设置在第一存储电极的另一侧。
第一配线的连接线和第二配线的连接线中的至少一条连接线可以包括与像素电极重叠的重叠区域。
多条配线中的至少一条配线可以包括第一数据线或驱动电压线。
多个像素可以包括:与第一像素相邻的第二像素,并且第二像素的像素电极可以在第一线和第二线之间延伸,以部分地与连接线重叠。
多条配线中的至少一条配线还可以包括:第二数据线,该第二数据线电连接到第二像素的薄膜晶体管,并且第一数据线的第一线与第二线之间的距离可以与第二数据线的第一线和第二之间的距离相同。
第一像素可以包括:中间层,被设置在像素电极上,并且包括发光层;以及对电极,被设置在中间层上。
实施例可以通过提供一种制造显示装置的方法来实现,该方法包括:在基板上形成有源层;在有源层上形成第一绝缘层;在第一绝缘层上形成栅电极和扫描线,使得栅电极和扫描线在第一方向上延伸;在栅电极和扫描线上形成第二绝缘层;在第二绝缘层上形成像素电极,使得像素电极被电连接到有源层;并且在基板上形成多条配线,使得多条配线在与第一方向不同的第二方向上延伸,其中形成多条配线包括:形成在第二方向上彼此隔开的第一线和第二线;以及在第一线和第二线的下方形成连接线,该连接线将第一线和第二线电连接,第一绝缘层和所述第二绝缘层中的至少一个绝缘层被置于所述第一线和所述第二线之间。
形成第一线和第二线可以与形成像素电极在同一工艺中进行。
形成连接线可以与形成扫描线在同一工艺中进行。
附图说明
通过参照附图详细描述示例性实施例,各特征对于本领域技术人员而言将是显而易见的,其中:
图1示出根据实施例的显示装置的平面图;
图2A示出包括在图1的显示装置中的像素的等效电路图;
图2B示出根据另一实施例的包括在图1的显示装置中的像素的等效电路图;
图3示出根据实施例的显示装置的像素的示意性平面图;
图4示出沿着图3的线IV-IV'截取的图3的像素的剖面图;
图5A至5C示出图3的显示装置的像素的各种示例的示意性平面图;
图6A和6B示出根据其他实施例的显示装置的像素的示意性平面图;
图7和8示出根据其他实施例的显示装置的像素的示意性平面图;以及
图9A至9E示出根据实施例的形成显示装置的像素的方法中的各阶段的平面图和剖面图。
具体实施方式
现在将在下文中参考附图来更全面地描述示例性实施例,然而,这些示例性实施例可以以不同的形式来体现,并且不应被解释为受限于本文所阐述的实施例。相反,提供这些实施例,是为了使本公开全面和完整,并且将示例性实现方式完整地传达给本领域技术人员。
在附图中,为了图示清楚,可以放大层和区域的尺寸。还将理解,当一层或元件被称为位于另一层或元件“上”时,该层或元件可以直接位于另一层或元件上,或者还可以存在中间层。进一步,将理解,当一层被称为位于另一层“下方”时,其可以直接位于下方,或还可以存在一个或多个中间层。此外,还将理解,当一层被称为位于两个层“之间”时,其可以是这两个层之间的唯一层,或者还可以存在一个或多个中间层。在全文中,相同的附图标记指代相同的要素。
如本文所使用的,术语“或”和“和/或”包括一个或多个相关的所列项目的任意和所有的组合。当诸如“…中的至少一个”之类的表述在元件的列表之后时,该表述修饰元件的整个列表而不修饰列表的个别元件
在本文中使用的诸如“第一”和“第二”之类的术语仅用于描述各种构成元件,但是构成元件并不受这些术语所限制。这些术语仅被用于将一个构成元件与另一构成元件区分开的目的。
在一实施例中,本说明书中的单数形式表述包括复数形式的表述,除非另有明确规定。
诸如“包括”或“包含”之类术语可以不被解释为必须包括说明书中所描述的任何和所有构成元件或步骤,但是可以被解释为将一些构成元件或步骤排除在外,或者进一步包括另外的构成元件或步骤。
当可以不同地实现某个实施例时,可以不同于所描述的顺序而执行特定的处理顺序。例如,两个连续描述的处理可以被大致同时地执行或者以与所描述的顺序相反的顺序来执行。
在本说明书中,当构成元件“连接”或“被连接”到另一构成元件时,该构成元件不仅可以直接地接触或被连接到另一构成元件,而且还可以通过置于该构成元件和另一构成元件之间的其他构成元件中的至少一个构成元件来间接地接触或被连接到另一构成元件。例如,当构成元件电连接或被电连接到另一构成元件时,构成元件不仅可以直接地电接触或被电连接到另一构成元件,而且还可以通过置于该构成元件和另一构成元件之间的其他构成元件中的至少一个构成元件来间接地电接触或被电连接到另一构成元件。
图1示出根据实施例的显示装置1的平面图。
参考图1,根据本实施例的显示装置1可以包括基板100上的显示区域DA和非显示区域NDA。
显示区域DA可以包括多个像素P以实现图像。诸如有机发光器件之类的各种显示器件可被设置在显示区域DA中。
非显示区域NDA可被设置成与显示区域DA邻接。在一实施例中,如图1所示,非显示区域NDA可被设置成包围或环绕显示区域DA。在另一实施例中,非显示区域NDA可以被设置成与显示区域DA的一侧(例如仅一侧)邻接。用于对将要施加到显示区域DA的电信号进行传输的各种配线可以位于非显示区域NDA中。
图2A示出包括在图1的显示装置1中的像素P的等效电路图。图2A示出像素P包括OLED的情况。
参考图2A,每个像素P可以包括连接到扫描线SL和数据线DL的像素电路PC,以及连接到像素电路PC的OLED。
像素电路PC可以包括多个薄膜晶体管T1和T2以及存储电容器Cst。像素P可以包括显示器件,例如有机发光二极管(OLED),该显示器件通过经薄膜晶体管T1和T2以及存储电容器Cst接收驱动电压来发光。
在一实施例中,薄膜晶体管可以包括一个开关薄膜晶体管T1和一个驱动薄膜晶体管T2。
开关薄膜晶体管T1的栅电极可以连接到扫描线SL。开关薄膜晶体管T1的源电极和漏电极中的任意一个可以连接到数据线DL,并且另一个可以连接到存储电容器Cst的一端。当从扫描线SL供应扫描信号时,开关薄膜晶体管T1导通,并且将从数据线DL供应来的数据信号供应到存储电容器Cst。在这种情况下,存储电容器Cst可以充入与数据信号相对应的电压。
驱动薄膜晶体管T2的栅电极可以连接到栅极控制线EL,该栅极控制线EL被电连接到开关薄膜晶体管T1。驱动薄膜晶体管T2的源电极可以电连接到存储电容器Cst和驱动电压线PL,并且驱动薄膜晶体管T2的漏电极可以连接到OLED的像素电极。
驱动薄膜晶体管T2可以由开关薄膜晶体管T1导通,并且可以对应于存储在存储电容器Cst中的电压值,来对从驱动电压线PL流向OLED的对电极的驱动电流Ioled进行控制。OLED的中间层可以通过驱动电流Ioled来发射具有一定亮度的光。
在一实现方式中,如图2A所示,可以存在两个薄膜晶体管。在一实现方式中,可以改变薄膜晶体管的类型和数量。
图2B示出根据另一实施例的包括在图1的显示装置1中的像素的等效电路图。在图2B中,存在三个薄膜晶体管。
第一开关薄膜晶体管T1的栅电极可以连接到扫描线SL。第一开关薄膜晶体管T1的源电极和漏电极中的任意一个可以连接到数据线DL,并且另一个可以连接到存储电容器Cst的一端。当从扫描线SL供应扫描信号时,第一开关薄膜晶体管T1可以导通,并且将数据线DL供应的数据信号供应到存储电容器Cst。在这种情况下,存储电容器Cst可以充入与数据信号相对应的电压。
第二开关薄膜晶体管T3的栅电极可以连接到感测扫描线SSL。第二开关薄膜晶体管T3的源电极和漏电极中的任意一个可以连接到初始化电压线22,并且另一个可以连接到驱动薄膜晶体管T2的一端。初始化电压线22可以传输初始化电压VINT,以对驱动薄膜晶体管T2进行初始化。第二开关薄膜晶体管T3根据感测扫描线SSL而导通,并且将初始化电压VINT传输到驱动薄膜晶体管T2的栅电极,从而执行初始化操作,以对驱动薄膜晶体管T2的栅电极的电压进行初始化。
驱动薄膜晶体管T2可以由第一开关薄膜晶体管T1导通,并且可以对应于存储在存储电容器Cst中的电压值来对从驱动电压线PL流向OLED的对电极的驱动电流(Ioled)进行控制。OLED的中间层可以通过驱动电流(Ioled)来发射具有一定亮度的光。在以下的描述中,为了便于说明,主要描述三个薄膜晶体管的情况。
图3示出根据实施例的显示装置1的像素P的示意性平面图。图4示出沿着图3的线IV-IV'截取的图3的像素P的剖面图。
参考图3和图4,根据本实施例的显示装置1可以包括位于基板100上的多个像素。在各像素中,像素P可以包括扫描线SL、多条配线160、多个薄膜晶体管(TFT)、以及像素电极150。
在一实现方式中,基板100可以由例如玻璃基板或塑料基板来形成,所述塑料基板包括聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、或聚酰亚胺。根据一实施例,基板100可以包括柔性基板100。柔性基板100是指可很好地弯曲的、柔性的、可折叠的或可卷曲的基板。柔性基板100可以由超薄的玻璃、金属或塑料来形成。
还可以在基板100上提供缓冲层101,以有助于确保基板100的平滑度,并且有助于防止杂质侵入到基板100。在缓冲层101中,氮化硅和/或氧化硅可被设置成单层或多层。可以在缓冲层101的显示区域DA中设置薄膜晶体管(TFT)。还可以在基板100和缓冲层101之间进一步设置阻挡层。在一实现方式中,可以省略缓冲层101。
TFT可以作为像素电路的一部分来发挥作用以驱动OLED。像素电路还可以包括连接到TFT的存储电容器Cst。在图4中,示出TFT中的驱动薄膜晶体管T2。
驱动薄膜晶体管T2可以包括被设置在缓冲层101上的有源层110和被设置在有源层110的至少一部分上的栅电极131。栅极绝缘层103可被设置在有源层110和栅电极131之间。
在一实现方式中,有源层110可以包括半导体材料,例如非晶硅或多晶硅。在一实现方式中,有源层110可以包括有机半导体材料或氧化物半导体材料。有源层110可以包括沟道区113和位于沟道区113外部的源区和漏区,源区和漏区通过掺杂离子杂质或者等离子体处理来形成。源区和漏区分别与源电极111和漏电极115对应。
栅电极131可以包括与用于将导通/截止信号施加到驱动薄膜晶体管T2的扫描线SL相同的材料,并且可以由低电阻金属材料来形成。在一实现方式中,栅电极131可以由选自铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)、铜(Cu)中的至少一种金属以单层或多层来形成。
在一实现方式中,栅电极131可以形成为由上述低电阻金属材料形成的层和包括透光导电氧化物的层这样的多层。透光导电氧化物可以包括选自氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)和氧化铝锌(AZO)中的至少一种的透光导电氧化物。
层间绝缘层105可被设置在驱动薄膜晶体管T2上。栅极绝缘层103和层间绝缘层105可以是由无机材料形成的单层膜或多层膜。例如,无机材料可以包括氧化硅(SiO2)、氮化硅(SiNx)、氮氧化硅(SiON)、氧化铝(Al2O3)、氧化钛(TiO2)、氧化钽(Ta2O5)、氧化铪(HfO2)和/或氧化锆(ZrO2)。
缓冲层101、栅极绝缘层103和层间绝缘层105不仅可以延伸到显示区域DA,而且可以延伸到非显示区域NDA的一部分。根据一实施例,缓冲层101和层间绝缘层105可被设置在除了基板100的最外面的边缘区域之外的区域中。
像素电极150(经由通孔VIA电连接到驱动薄膜晶体管T2)可被设置在层间绝缘层105上。像素电极150可以电连接到源电极111和漏电极115中的任意一个。
存储电容器Cst可以电连接到驱动薄膜晶体管T2,并且可以包括依次层叠的第一存储电极133、介电层和第二存储电极153。栅极绝缘层103和层间绝缘层105中的至少一个绝缘层可以包括介电层。在一实现方式中,介电层可以形成为置于第一存储电极133和第二存储电极153之间的层间绝缘层105的一部分。
存储电容器Cst的第二存储电极153可被设置成与第一存储电极133至少部分地重叠。例如,第二存储电极153可被设置成完全覆盖第一存储电极133。第二存储电极153可以包括与像素电极150相同的材料,并且可以形成为像素电极150的一部分。在一实现方式中,第一存储电极133可以连接到驱动薄膜晶体管T2的栅电极131。第一存储电极133的一部分可以是驱动薄膜晶体管T2的栅电极131。
配线160可以在第二方向上延伸,以跨越在第一方向上延伸的扫描线SL。配线160可以包括至少一条数据线DL和至少一条驱动电压线PL。数据线DL可以包括红色数据线、绿色数据线和蓝色数据线中的至少一种。配线160中的至少一条可以包括在第二方向上彼此隔开的第一线161和第二线162、以及将第一线161和第二线162电连接的连接线163。连接线163可被设置在第一线161和第二线162的下方,至少一个绝缘层被置于第一线161和第二线162之间。绝缘层可以是层间绝缘层105。
图3仅示出一个像素P,并且第一线161和第二线162显现为独立的元件。在一实现方式中,第一线161和第二线162可以在第二方向上大致设置在同一条线上,以连接到相邻像素的第二线和第一线。第一线161和第二线162可以与像素电极150包括相同的材料并且在同一的层上。例如,第一线161和第二线162可以由选自Al、Pt、Pd、Ag、Mg、Au、Ni、Nd、Ir、Cr、Li、Ca、Mo、Ti、W和Cu中的至少一种金属以单层或多层来形成。例如,第一线161和第二线162可以由从底部依次设置的Ti/Al/AlNiLa合金/ITO的多层、Mo/Al/AlNiLa合金/ITO的多层、Ti/Cu/AlNiLa合金/ITO的多层和Mo/Cu/AlNiLa合金/ITO的多层中的任意一种来形成。
连接线163可以经由在层间绝缘层105中形成的在连接线163的相对侧或端部的接触孔CNT而电连接到第一线161和第二线162。不同于第一线161和第二线162,连接线163可以位于与像素电极150不同的层上,并且可以包括与像素电极150不同的材料。例如,连接线163可以包括与扫描线SL相同的材料。例如,连接线163可以由选自Al、Pt、Pd、Ag、Mg、Au、Ni、Nd、Ir、Cr、Li、Ca、Mo、Ti、W和Cu中的至少一种金属以单层或多层来形成。连接线163可以是岛型。在一实现方式中,连接线163可被设置成不与扫描线SL重叠。
连接线163可以位于与像素电极150不同的层上,并且连接线163可以包括与像素电极150重叠的重叠区域A。例如,像素电极150的一部分可以在第一线161和第二线162之间延伸,以与第一线161和第二线162中的每一个间隔开。因此,像素电极150可以确保增加的面积而不会干扰配线160。
图5A至5C示出图3的显示装置1的像素P的各种示例的示意性平面图。图5A至5C的示例与图3的像素P的不同仅在于像素电极150和配线160之间的重叠区域,除了驱动薄膜晶体管T2之外的薄膜晶体管和存储电容器Cst从图中被省略掉,并且可以省略对各元件的重复描述。
参考图5A至5C,配线160可以包括与第一存储电极133的一侧隔开设置的一条或多条第一配线160-1、以及与第一存储电极133的另一侧隔开设置的一条或多条第二配线160-2。
第一配线160-1和第二配线160-2中的每一条配线可以包括第一线161和第二线162以及连接线163,第一线161和第二线162在第二方向上彼此隔开并且包括与像素电极150相同的材料,并且,连接线163将第一线161和第二线162连接并且包括与扫描线SL相同的材料。在不包括连接线163的实现方式中,配线160可以包括直接将第一线161和第二线162连接的第三配线160-3。
在一实现方式中,第一配线160-1的第一连接线163-1和第二配线160-2的第二连接线163-2中的至少一条连接线可以包括与像素电极150重叠的重叠区域。在图5A中,第一连接线163-1和像素电极150在第一重叠区域A1中彼此重叠,并且第二连接线163-2和像素电极150在第二重叠区域A2中彼此重叠。
如图5A所示,配线160可以包括:包含第一线161、第二线162和连接线163的所有配线,并且像素电极150可被设置在第一重叠区域A1和第二重叠区域A2中。在一实现方式中,如图5B所示,配线160可以包括第一配线160-1和第三配线160-3,并且像素电极150可以与包括第一连接线163-1的第一配线160-1形成第一重叠区域A1。在一实现方式中,如图5C所示,配线160可以仅包括第一配线160-1和第二配线160-2,而没有第三配线160-3。像素电极150可以仅与第一配线160-1和第二配线160-2中之一形成重叠区域。
图6A和6B示出根据其他实施例的显示装置1的像素P的示意性平面图。在图6A和6B中,与图3中的那些附图标记相同的附图标记指代相同的元件,为了简化说明,可以省略对相同的元件的重复描述。
参考图6A和6B,配线160中的至少一条可以包括第一线161、第二线162,以及连接线163,第一线161和第二线162在第二方向上彼此隔开并且包括与像素电极150相同的材料,连接线163将第一线161和第二线162连接并且包括与扫描线SL相同的材料。连接线163可以包括与像素电极150重叠的重叠区域A。在这种情况下,像素电极150可以包括至少一个被设置成与连接线163相对应的开口H。在一实现方式中,开口H可被设置成与每条连接线163相对应。如图6A所示,开口H可以选择性地被设置在连接线163中。在一实现方式中,如图6B所示,开口H可以是从像素电极150的外侧凹入的凹形槽。
像素电极150中的开口H可以暴露出连接线163的上表面,并且可以减小与像素电极150重叠的区域。因此,可以有利地减少在像素电极150和配线160之间否则可能产生的寄生电容。
图7和图8示出根据其他实施例的显示装置1的像素P的示意性平面图。在图7和图8中,与图3中的那些附图标记相同的附图标记指代相同的元件,为了简化说明,省略对相同的元件的重复描述。
参考图7,根据另一实施例的显示装置1可以包括各像素之中的第一像素P1和第二像素P2。在这种情况下,第一像素P1和第二像素P2可被设置在第二方向上。在一实现方式中,配线160可以包括第一数据线DL1、第二数据线DL2和驱动电压线。第一数据线DL1可以将数据信号施加到第一像素P1的TFT,并且第二数据线DL2可以将数据信号施加到第二像素P2的TFT。
第一像素P1可以包括第一TFT T2-1和第一像素电极1501。在这种情况下,第一TFTT2-1可以电连接到配线160中的任意一条配线,并且可以包括第一栅电极1131、第一源电极1111和第一漏电极1151。第一像素电极1501可以电连接到第一源电极1111和第一漏电极1151中的任意一个。另外,第一像素P1还可以包括第一存储电容器Cst1。
第二像素P2可以包括第二TFT T2-2和第二像素电极1502。在这种情况下,第二TFTT2-2可以电连接到配线160中的任意一条配线,并且可以包括第二栅电极1132、第二源电极1112和第二漏电极1152。第二像素电极1502可以电连接到第二源电极1112和第二漏电极1152中的任意一个。第二像素P2还可以包括第二存储电容器Cst2。
配线160中的至少一条配线可以包括在第二方向上彼此隔开的第一线161和第二线162,以及将第一线161和第二线162电连接的连接线163。第一线161和第二线162可以与第一像素电极1501和第二像素电极1502包括相同的材料并且位于同一层上。连接线163可以将第一线161和第二线162连接,可以位于与第一像素电极1501不同的层上,并且可以包括与扫描线SL相同的材料。
第一像素电极1501和第二像素电极1502中的至少一个像素电极可以在第一线161和第二线162之间延伸,以与连接线163部分地重叠。换言之,连接线163可以包括与第一像素电极1501和第二像素电极1502中的至少任意一个像素电极重叠的重叠区域A。第一像素P1可以是红色子像素、绿色子像素和蓝色子像素中的任意一个子像素,并且第二像素P2可以是与第一像素P1的颜色不同的颜色的子像素。
在根据另一实施例的显示装置1中,第一像素P1和与第一像素P1相邻的第二像素P2可以共享扫描线SL以及配线160中的至少初始化电压线22和驱动电压线PL。在一实现方式中,第一数据线DL1和第二数据线DL2可以连接到第一像素P1的TFT和第二像素P2的TFT中的每一个。在一实现方式中,第一数据线DL1和第二数据线DL2都可以在第二方向上延伸,以被分别包括在第一像素P1和第二像素P2中。因此,包括在第一像素P1和第二像素P2中的配线160可以是第一数据线DL1、第二数据线DL2、初始化电压线22和驱动电压线PL。在一实现方式中,配线160还可以包括连接到OLED并施加电源电压ELVSS的电源电压线155。
参考图8,第一像素电极1501和第二像素电极1502中的至少一个像素电极可以包括至少一个开口H,开口H被设置成与连接线163对应或覆盖在连接线163上。第一像素电极1501和第二像素电极1502可以通过由于存在开口H而减小与配线160的重叠区域,而有助于减小寄生电容。
在另一实施例中,第一数据线DL1的第一线161和第二线162之间的距离可以与第二数据线DL2的第一线161和第二线162之间的距离大致相同。例如,当配线160是数据线DL时,如果第一线161和第二线162之间的距离d针对配线160中的每一条配线而变化,则配线160的电阻可能因距离差异而变化。将数据信号施加到像素P的时间可能会由于电阻的差异而变化,并且可以将第一线161和第二线162之间的距离d设置为常数以有助于减小电阻差。
参照图9A至9E来描述制造根据实施例的显示装置的方法。
图9A至9E示出形成根据实施例的显示装置的像素的方法中的各阶段的平面图和剖面图。
参考图9A,可以在形成有缓冲层101的基板100上形成有源层。有源层110可以由非晶硅或多晶硅、或者诸如G-I-Z-O层[(In2O3)a(Ga2O3)b(ZnO)c层]之类的氧化物半导体来形成,其中“a”、“b”和“c”是分别满足条件a≥0、b≥0、c>0的整数。
可以在有源层110上形成作为第一绝缘层的栅极绝缘材料层103'。栅极绝缘材料层103'可以形成在基板100的整个表面上,覆盖有源层110。栅极绝缘材料层103'可以由有机和/或无机绝缘材料来形成。在一实施例中,栅极绝缘材料层103'可以由例如氮化硅(SiNx)、氧化硅(SiO2)、氧化铪(HfO2)或氧化铝(Al2O3)来形成。
参考图9B,在第一导电层被堆叠在栅极绝缘材料层103'上之后,可以通过使用掩模来对第一导电层进行图案化,从而形成栅电极131、第一存储电极133和连接线163(即配线160中的至少一条配线)。在这种情况下,当有源层110为氧化物半导体时,为了形成源区和漏区,可以通过将栅极绝缘材料层103'完全图案化来形成栅极绝缘层103。接着,源电极111和漏电极115可以通过使用栅电极131作为掩模、将杂质注入到有源层110的相对端或在有源层110上进行等离子体处理来形成。杂质可以根据TFT的类型而变化,并且可以使用N型杂质或P型杂质。
参考图9C,可以形成层间绝缘层105(即将栅电极131、第一存储电极133和连接线163覆盖的第二绝缘层)。接着,可以形成穿透层间绝缘层105的接触孔CNT和通孔VIA。接触孔CNT可以暴露出连接线163,并且通孔VIA可以暴露出漏电极115。
参考图9D,在第二导电层被堆叠在层间绝缘层105上之后,可以通过使用掩模来对第二导电层进行图案化,使得在多条配线中,可以形成包括第一线161、第二线162和像素电极150中的至少之一并且不包括连接线163的配线。在这种情况下,像素电极150可以被定位成与第一存储电极133重叠,并且像素电极150的一部分可以执行第二存储电极153的功能。连接线163可以经由接触孔CNT而连接到彼此隔开的第一线161和第二线162。
参考图9E,可以在像素电极150的上方设置像素限定层107。像素限定层107可以具有暴露出像素电极150的上表面的开口,并且可以对基板100上的像素区域进行限定。可以形成将用于施加电源电压ELVSS的电源电压线155的上表面的一部分暴露出的开口。电源电压线155可以经由对电极180而电连接到OLED。
可以在像素电极150的上方设置OLED。OLED可以包括中间层170和对电极180。
中间层170可以包括发射红光、绿光或蓝光的有机发光层。有机发光层可以包括低分子有机材料或聚合物有机材料。当有机发光层是由低分子有机材料形成的低分子有机层时,空穴传输层HTL和空穴注入层HIL可以被定位在相对于有机发光层而朝向像素电极150的方向上,并且电子传输层ETL和电子注入层EIL在朝向对电极180的方向上堆叠。除了HTL、HIL、ETL和EIL之外,可以根据需要来堆叠各种层。
面对像素电极150的对电极180可以在中间层170上提供。当对电极180形成为透光电极时,对电极180可以包括由诸如Li、Ca、LiF/Ca、LiF/Al、Al、Ag、Mg或其化合物之类的具有低逸出功的金属形成的层、以及诸如ITO、IZO、ZnO或In2O3之类的透光导电层。当对电极180形成为反射电极时,对电极180可以包括由Li、Ca、LiF/Ca、LiF/Al、Al、Ag、Mg或其化合物形成的层。
通过总结和回顾,随着单位像素的尺寸减小(由于高分辨率显示装置的需求),确保开口率可能是需要解决的问题。
如上所述,在根据上述实施例的显示装置中,与像素电极位于同一层上的配线的一部分可以被绕到不同的层,并且可以增加像素电极的面积,从而可以提高开口率。
实施例可以提供可以确保开口率的显示装置。
本文已经公开了示例性实施例,并且虽然采用了特定术语,但是它们仅在通用性及描述性的意义上被使用并且被解释,而不是为了限制的目的。在一些情况下,如提交本申请的本领域普通技术人员所显而易见的,结合特定实施例描述的特征、特性和/或元件可以单独使用或者和与其他实施例相关的特征、特性和/或元件组合使用,除非另有具体说明。因此,本领域技术人员将理解,在不脱离如所附权利要求中阐述的本发明的精神和范围的情况下,可以进行形式和细节上的各种改变。
Claims (19)
1.一种显示装置,包括位于基板上的多个像素,其中所述多个像素中的第一像素包括:
扫描线,在第一方向上延伸;
多条配线,在与所述第一方向交叉的第二方向上延伸;
至少一个绝缘层,位于所述扫描线和所述多条配线之间;
薄膜晶体管,电连接到所述扫描线和所述多条配线;以及
像素电极,电连接到所述薄膜晶体管,
其中所述多条配线中的至少一条配线包括:
第一线和第二线,在所述第二方向上彼此隔开,以及
连接线,将所述第一线和所述第二线电连接,所述至少一个绝缘层位于所述连接线与所述第一线和所述第二线之间,并且
其中所述连接线与所述像素电极重叠。
2.根据权利要求1所述的显示装置,其中
所述第一线和所述第二线包括与所述像素电极相同的材料。
3.根据权利要求1所述的显示装置,其中
所述连接线在所述第一线和所述第二线的下方,并且
所述连接线包括与所述扫描线相同的材料。
4.根据权利要求1所述的显示装置,其中
所述像素电极包括将所述连接线覆盖的至少一个开口。
5.根据权利要求1所述的显示装置,其中
所述像素电极的一部分在所述第一线和所述第二线之间延伸。
6.根据权利要求1所述的显示装置,进一步包括:
存储电容器,电连接到所述薄膜晶体管,所述存储电容器包括顺序堆叠的第一存储电极、介电层、和第二存储电极。
7.根据权利要求6所述的显示装置,其中
所述第一存储电极包括与所述连接线相同的材料。
8.根据权利要求6所述的显示装置,其中
所述第二存储电极包括与所述像素电极相同的材料。
9.根据权利要求6所述的显示装置,其中
所述第二存储电极是所述像素电极的一部分。
10.根据权利要求6所述的显示装置,其中
所述至少一个绝缘层包括所述介电层。
11.根据权利要求6所述的显示装置,其中,所述多条配线包括:
第一配线,被设置在所述第一存储电极的一侧;以及
第二配线,被设置在所述第一存储电极的另一侧。
12.根据权利要求11所述的显示装置,其中
所述第一配线的连接线和所述第二配线的连接线中的至少一条连接线包括与所述像素电极重叠的重叠区域。
13.根据权利要求1所述的显示装置,其中
所述多条配线中的至少一条配线包括第一数据线或驱动电压线。
14.根据权利要求13所述的显示装置,其中:
所述多个像素包括与所述第一像素相邻的第二像素,并且
所述第二像素的像素电极在所述第一线和所述第二线之间延伸,以部分地与所述连接线重叠。
15.根据权利要求14所述的显示装置,其中:
所述多条配线中的至少一条配线进一步包括:第二数据线,所述第二数据线电连接到所述第二像素的薄膜晶体管,并且
所述第一数据线的第一线和第二线之间的距离与所述第二数据线的第一线和第二线之间的距离相同。
16.根据权利要求1所述的显示装置,其中,所述第一像素包括:
中间层,被设置在所述像素电极上,并且包括发光层;以及
对电极,被设置在所述中间层上。
17.一种制造显示装置的方法,所述方法包括:
在基板上形成有源层;
在所述有源层上形成第一绝缘层;
在所述第一绝缘层上形成栅电极和扫描线,使得所述栅电极和所述扫描线在第一方向上延伸;
在所述栅电极和所述扫描线上形成第二绝缘层;
在所述第二绝缘层上形成像素电极,使得所述像素电极被电连接到所述有源层;并且
在所述基板上形成多条配线,使得所述多条配线在与所述第一方向不同的第二方向上延伸,
其中形成所述多条配线包括:
形成在所述第二方向上彼此隔开的第一线和第二线;以及
在所述第一线和所述第二线的下方形成连接线,所述连接线将所述第一线和所述第二线电连接,所述第一绝缘层和所述第二绝缘层中的至少一个绝缘层被置于所述第一线和所述第二线之间。
18.根据权利要求17所述的方法,其中
形成所述第一线和所述第二线与形成所述像素电极在同一工艺中进行。
19.根据权利要求17所述的方法,其中
形成所述连接线与形成所述扫描线在同一工艺中进行。
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