CN107369618B - Method for flattening wafer - Google Patents
Method for flattening wafer Download PDFInfo
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- CN107369618B CN107369618B CN201710552553.1A CN201710552553A CN107369618B CN 107369618 B CN107369618 B CN 107369618B CN 201710552553 A CN201710552553 A CN 201710552553A CN 107369618 B CN107369618 B CN 107369618B
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- wafer
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- cerium oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The invention provides a wafer planarization method, wherein the wafer comprises a substrate and an oxide layer, a groove is formed on the substrate, the oxide layer covers the substrate and fills the groove, and the wafer is ground by using cerium oxide grinding fluid, so that the defect of depression can be effectively overcome, and the wafer has better in-chip flatness and smaller butterfly degree. The scratch on the surface of the wafer is small, which is beneficial to planarization; the pH value of the surface of the wafer is increased, so that the adhesiveness of cerium oxide particles can be effectively reduced, the cerium oxide particles adhered to the surface of the wafer are reduced, and the subsequent cleaning of the wafer is facilitated; and grinding the wafer by using deionized water, and washing away cerium oxide particles and other impurities attached to the surface of the wafer. The whole process flow is very simple, the subsequent detection of the wafer is more accurate, and the yield of the chip is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a wafer planarization method.
Background
In a semiconductor manufacturing process, a planarization process is one of the indispensable process steps, and the planarization capability directly affects the flatness of the wafer surface, which in turn affects the product yield.
Shallow Trench Isolation (STI) is a front-end process used to form isolation regions between devices on the surface of a silicon wafer, and the filling oxide layer in the STI is planarized by using a planarization technique to polish off all oxide layers higher than the barrier layer. One difficulty with STI planarization is how to avoid thinning the oxide in the trench too much, or creating dishing. The dishing phenomenon causes many negative effects on the device, such as a decrease in gate voltage, an increase in leakage current, and the like. In the prior art, in order to solve the defect of recess in the STI planarization, a cerium oxide polishing solution is generally used in the STI planarization process, and has very uniform particle size, relatively high polishing speed, high selectivity, automatic stop and other special polishing characteristics. However, the cerium oxide abrasive particles have high adsorbability and are easy to remain on the surface of the silicon wafer, which is not beneficial to the subsequent cleaning of the silicon wafer and increases the complexity of the process. In addition, the particles remaining on the silicon wafer can also cause errors in the detection of the silicon wafer, which affects the yield of the chip.
Therefore, it is necessary to develop a method for planarizing a wafer which can reduce the adhesion of cerium oxide particles to the surface of a silicon wafer.
Disclosure of Invention
The invention aims to provide a method for flattening a wafer, which aims to solve the problem that cerium oxide grinding particles are easy to remain on the surface of a silicon wafer in the process of flattening the wafer by using cerium oxide grinding fluid.
In order to solve the above technical problem, the present invention provides a method for planarizing a wafer, wherein the wafer includes a substrate and an oxide layer; the method comprises the following steps of forming a groove in the substrate, covering the substrate with the oxide layer and filling the groove, and grinding the wafer on a grinding pad to flatten the wafer, wherein the wafer flattening method comprises the following steps: grinding the wafer by using cerium oxide grinding fluid; increasing the pH value of the surface of the wafer; grinding the wafer by using deionized water;
optionally, before the wafer is polished by using the cerium oxide polishing slurry, the method for planarizing the wafer further includes: grinding the wafer by using a silicon oxide grinding fluid;
optionally, the method for increasing the PH of the surface of the wafer includes flowing an alkaline solution over the polishing pad.
Optionally, the time for flowing the alkaline solution on the grinding pad is 10s-20 s;
optionally, the flow rate of the alkaline solution flowing on the grinding pad is 150ml/min-250 ml/min;
optionally, the method for increasing the PH of the surface of the wafer includes immersing the wafer in an alkaline solution;
optionally, the alkaline solution is a silicon dioxide grinding fluid;
optionally, the substrate is made of silicon;
optionally, the oxide layer is made of silicon dioxide;
optionally, the wafer further includes a barrier layer covering the substrate;
optionally, the wafer further includes a dielectric layer located between the substrate and the barrier layer;
optionally, the thickness of the dielectric layer is 90 angstroms to 150 angstroms;
optionally, the dielectric layer is made of silicon oxide;
optionally, the material of the barrier layer is silicon nitride.
In the wafer planarization method provided by the invention, the wafer comprises a substrate, and a groove is formed on the substrate; and the oxide layer covers the substrate and fills the groove. And grinding the wafer by using cerium oxide grinding fluid on a grinding pad to flatten the wafer, increasing the pH value of the surface of the wafer, and finally grinding the wafer by using deionized water. The cerium oxide grinding fluid is used for grinding, the defect that the wafer is sunken after being flattened can be overcome, the flatness in the wafer is better, the butterfly degree is smaller, the scratch on the surface of the wafer is small, and the flattening is facilitated. The cerium oxide grinding fluid is acidic or neutral, the pH value of the cerium oxide grinding fluid is between 5 and 7, the adsorption of cerium oxide particles on the surface of a wafer can be weakened by increasing the pH value of the surface of the wafer, the particles attached to the surface of the wafer are reduced, the subsequent cleaning of the wafer is facilitated, and the process flow is simplified. In addition, the subsequent detection of the wafer is more accurate, and the yield of the chip is improved.
Drawings
FIG. 1 is a schematic view of a wafer structure;
FIG. 2 is a flow chart of a method for planarizing a wafer according to an embodiment;
the method comprises the steps of 1-wafer, 11-substrate, 12-oxide layer, 13-barrier layer, 14-isolation groove and 15-dielectric layer.
Detailed Description
The following describes an embodiment of a method for planarizing a wafer according to the present invention in more detail with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1-2, which are schematic views of a wafer structure and a method for planarizing the wafer according to the present invention, the wafer 1 includes a substrate 11 and an oxide layer 12; a trench 14 is formed in the substrate 11, the oxide layer 12 covers the substrate 11 and fills the trench 14, the wafer 1 is polished on a polishing pad to planarize the wafer 1, and the planarization method for the wafer 1 includes, S1: grinding the wafer 1 by using cerium oxide grinding fluid; s2: increasing the PH value of the surface of the wafer 1; s3: and grinding the wafer 1 by using deionized water. The oxide layer 12 of the wafer 1 is ground by using the cerium oxide grinding fluid, the particle size of the cerium oxide grinding fluid is very uniform, and the cerium oxide grinding fluid has special grinding characteristics such as higher grinding speed, higher selection ratio and automatic stop. The pH value of the cerium oxide grinding fluid is between 5 and 7, the pH value of the surface of the wafer 1 is increased, the adsorbability of cerium oxide particles can be effectively reduced, and the cleaning of the wafer is facilitated. The surface particles of the wafer 1 are reduced, the subsequent detection of the wafer 1 is more accurate, and the yield of chips is also improved.
As shown in fig. 1, an isolation trench 14 for isolating an active region is formed on a substrate 11, and an oxide layer 12 is filled in the isolation trench 14, wherein the oxide layer 12 covers the substrate 11 and is higher than the surface of the substrate 11. Preferably, the substrate 11 further includes a barrier layer 13, the barrier layer 13 covering the portion of the substrate except the trench 14, the barrier layer 13 being a layer of a robust mask material that helps protect the active area during the STI oxide deposition process and acts as a ground barrier material, and a dielectric layer 15 may be formed between the substrate 11 and the barrier layer 13, the dielectric layer 15 having a thickness of 90 a to 150 a for matching the stress between the barrier layer 13 and the substrate 11. The substrate 11 is preferably made of silicon, the oxide layer 12 is preferably made of silicon dioxide, the barrier layer 13 is preferably made of silicon nitride, and the dielectric layer 15 is preferably made of silicon oxide, which may be other materials, but the present invention is not limited thereto.
S1: the oxide layer 12 of the wafer 1 is polished with a cerium oxide polishing liquid, and polishing is stopped on the barrier layer 13. The cerium oxide particles have a small diameter and a uniform size, and the scratches formed during the polishing of the wafer 1 are small. Moreover, since the cerium oxide polishing liquid has a strong reactivity with the oxide layer 12 of the present invention and a weak reactivity with the barrier layer 13, the polishing rate of the cerium oxide polishing liquid with respect to the oxide layer 12 of the present invention is more than 50 times the polishing rate of the barrier layer with the same polishing force,
before polishing the wafer 1 with the cerium oxide polishing liquid, the wafer 1 may be polished with a silicon dioxide polishing liquid to polish the oxide layer 12 to a predetermined thickness. The consumption speed of the grinding fluid is high as a consumable material, the oxide layer 12 is ground to a certain thickness by using the silicon dioxide grinding fluid, and then the cerium oxide grinding fluid is used for grinding, so that the use speed of the cerium oxide grinding fluid can be greatly reduced, and the production cost is reduced. It is understood, of course, that the step of polishing the wafer 1 with the silica polishing slurry is not essential, and that the additional step may not be necessary in situations where the manufacturing cost is not high or where the quality of the wafer is high.
S2: the method for increasing the pH value of the surface of the wafer 1 is to flow an alkaline solution on the polishing pad 2. The cerium oxide has the characteristic of adsorbing negative ions, and the barrier layer 13 in the invention also has the capability of adsorbing negative ions, so that cerium oxide particles are easily adsorbed on the surface of the wafer after grinding. The pH value of the cerium oxide grinding fluid is between 5 and 7, and an alkaline solution flows on the grinding pad, so that the adhesion of cerium oxide can be effectively reduced, particles adhered to the surface of the wafer 1 are reduced, and the cleaning process of the wafer 1 is facilitated.
The time for flowing the alkaline solution is 10s to 20s, for example 15 s; the flow rate of the flowing alkaline solution is 150ml/min to 250ml/min, for example 200 ml/min.
In this embodiment, the method for increasing the PH of the surface of the wafer 1 is to flow an alkaline solution onto the polishing pad. However, it should be appreciated that there may be other methods for increasing the PH of the surface of the wafer 1, such as soaking the polished wafer 1 in an alkaline solution, preferably for 10 seconds; alternatively, a pipe is added to the polishing machine, and the surface of the polished wafer 1 is rinsed with an alkaline solution. In summary, the method for increasing the PH of the surface of the wafer 1 is not limited in the present invention.
The alkaline solution is preferably a silica polishing solution, and the silica particles do not have strong adsorption capacity, so that the contact chance between the cerium oxide particles and the surface of the wafer 1 is greatly reduced.
S3: the wafer 1 is ground by using deionized water, in the process of flattening the wafer 1, grinding liquid is used for grinding, components in the grinding liquid react with the wafer 1, new impurities are introduced, the wafer is ground by using the deionized water, an oxidation layer 12 of the wafer 1 cannot be further ground, a recess is formed, and only by-products generated by grinding and the grinding liquid or particles remained on the surface of the wafer are washed away.
In summary, in the method for planarizing a wafer according to the embodiment of the present invention, the wafer includes a substrate, and a trench is formed on the substrate; and the oxide layer covers the substrate and fills the groove. And grinding the wafer by using cerium oxide grinding fluid on a grinding pad to flatten the wafer, increasing the pH value of the surface of the wafer, and finally grinding the wafer by using deionized water. The cerium oxide grinding fluid is used for grinding, the defect that the wafer is sunken after being flattened can be overcome, the flatness in the wafer is better, the butterfly degree is smaller, the scratch on the surface of the wafer is small, and the flattening is facilitated. The cerium oxide grinding fluid is acidic or neutral, the pH value of the cerium oxide grinding fluid is between 5 and 7, the adsorption of cerium oxide particles on the surface of a wafer can be weakened by increasing the pH value of the surface of the wafer, the particles attached to the surface of the wafer are reduced, the subsequent cleaning of the wafer is facilitated, and the process flow is simplified. In addition, the subsequent detection of the wafer is more accurate, and the yield of the chip is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. The wafer planarization method is characterized in that the wafer comprises a substrate and an oxide layer; the method comprises the following steps of forming a groove in the substrate, covering the substrate with the oxide layer and filling the groove, and grinding the wafer on a grinding pad to flatten the wafer, wherein the wafer flattening method comprises the following steps:
grinding the wafer by using cerium oxide grinding fluid;
increasing the pH value of the surface of the wafer;
grinding the wafer by using deionized water;
the method for increasing the pH value of the surface of the wafer comprises the steps of flowing an alkaline solution on the grinding pad or soaking the wafer in the alkaline solution, wherein the alkaline solution is silicon dioxide grinding fluid.
2. The method of claim 1, wherein before polishing the wafer with the ceria slurry, the method further comprises: and polishing the wafer by using a silicon oxide polishing solution.
3. The method as claimed in claim 1, wherein the flowing time of the alkaline solution on the polishing pad is 10s-20 s.
4. The method of claim 1, wherein the alkaline solution is flowed over the polishing pad at a flow rate of 150ml/min to 250 ml/min.
5. The method as claimed in claim 1, wherein the substrate is made of silicon.
6. The method as claimed in claim 1, wherein the oxide layer is made of silicon dioxide.
7. The method of claim 1, wherein the wafer further comprises a barrier layer covering the substrate.
8. The method of claim 7, wherein the wafer further comprises a dielectric layer between the substrate and the barrier layer.
9. The method of claim 8, wherein the dielectric layer has a thickness of 90-150 angstroms.
10. The method of claim 8, wherein the dielectric layer is made of silicon oxide.
11. The method as claimed in claim 7, wherein the material of the barrier layer is silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710552553.1A CN107369618B (en) | 2017-07-07 | 2017-07-07 | Method for flattening wafer |
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| CN201710552553.1A CN107369618B (en) | 2017-07-07 | 2017-07-07 | Method for flattening wafer |
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| CN107369618A CN107369618A (en) | 2017-11-21 |
| CN107369618B true CN107369618B (en) | 2020-02-21 |
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| CN113327852B (en) * | 2021-05-27 | 2022-07-29 | 上海芯物科技有限公司 | Chemical mechanical polishing method for wafer surface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308790A (en) * | 2007-05-16 | 2008-11-19 | 联华电子股份有限公司 | Method for removing dielectric layer on substrate and chemical mechanical polishing process |
| CN105308164A (en) * | 2013-05-17 | 2016-02-03 | 高级技术材料公司 | Compositions and methods for removing ceria particles from a surface |
| CN106558529A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润微电子有限公司 | Shallow trench isolation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006339594A (en) * | 2005-06-06 | 2006-12-14 | Seimi Chem Co Ltd | Abrasive agent for semiconductor |
| US20080045014A1 (en) * | 2006-08-18 | 2008-02-21 | United Microelectronics Corp. | Complex chemical mechanical polishing and method for manufacturing shallow trench isolation structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308790A (en) * | 2007-05-16 | 2008-11-19 | 联华电子股份有限公司 | Method for removing dielectric layer on substrate and chemical mechanical polishing process |
| CN105308164A (en) * | 2013-05-17 | 2016-02-03 | 高级技术材料公司 | Compositions and methods for removing ceria particles from a surface |
| CN106558529A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润微电子有限公司 | Shallow trench isolation method |
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