CN107359123A - Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof - Google Patents
Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof Download PDFInfo
- Publication number
- CN107359123A CN107359123A CN201710516564.4A CN201710516564A CN107359123A CN 107359123 A CN107359123 A CN 107359123A CN 201710516564 A CN201710516564 A CN 201710516564A CN 107359123 A CN107359123 A CN 107359123A
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- nano wire
- electric fuse
- layer
- fin
- semiconductor devices
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 185
- 238000000034 method Methods 0.000 title claims abstract description 145
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- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical group [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 6
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
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- 229910018999 CoSi2 Inorganic materials 0.000 claims description 4
- 239000003153 chemical reaction reagent Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910008814 WSi2 Inorganic materials 0.000 claims description 3
- XNPAKGMQCVYQAO-UHFFFAOYSA-N [F].CC(O)=O Chemical compound [F].CC(O)=O XNPAKGMQCVYQAO-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- LVXIMLLVSSOUNN-UHFFFAOYSA-N fluorine;nitric acid Chemical compound [F].O[N+]([O-])=O LVXIMLLVSSOUNN-UHFFFAOYSA-N 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000000347 anisotropic wet etching Methods 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 230000005669 field effect Effects 0.000 abstract description 48
- 238000012545 processing Methods 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 description 62
- 239000002184 metal Substances 0.000 description 62
- 229910021332 silicide Inorganic materials 0.000 description 61
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 53
- 229910052710 silicon Inorganic materials 0.000 description 51
- 239000010703 silicon Substances 0.000 description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 238000002955 isolation Methods 0.000 description 14
- 238000003723 Smelting Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 241000209094 Oryza Species 0.000 description 4
- 235000007164 Oryza sativa Nutrition 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
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- 229910052802 copper Inorganic materials 0.000 description 4
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- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 235000012149 noodles Nutrition 0.000 description 4
- 235000009566 rice Nutrition 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 230000002950 deficient Effects 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A variety of electric fuse structures and forming method thereof, semiconductor devices and forming method thereof are provided in embodiments of the invention, such as adulterated into nano wire or fin, form electric fuse structure, while all-around-gate transistor or fin formula field effect transistor is formed, corresponding electric fuse structure is formed, realizes the diversity to form electric fuse structure and semiconductor devices.Also, when parasitizing among the step of forming all-around-gate transistor or fin formula field effect transistor when form electric fuse structure the step of, extra processing step will not be increased, production cost is low.
Description
The application is to submit Patent Office of the People's Republic of China, Application No. 201310192826.8, entitled on May 22nd, 2013
The division of the Chinese patent application of " electric fuse structure and forming method thereof, semiconductor devices and forming method thereof ".
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to electric fuse structure and forming method thereof, semiconductor device
Part and forming method thereof.
Background technology
In integrated circuit fields, fuse (Fuse) refers to some connecting lines that can be fused formed in integrated circuits.
Initially, fuse is for connecting the redundant circuit in integrated circuit, once detection finds that integrated circuit has defect, just using molten
Silk is repaired or substitutes defective circuit.Fuse is generally laser fuse (Laser Fuse) and electric fuse (Electrical
Fuse, hereinafter referred to as E-fuse) two kinds.With the development of semiconductor technology, E-fuse gradually instead of laser fuse.
In general, electric fuse structure can be made of metal (aluminium, copper etc.) or silicon, a kind of typical electric smelting in the prior art
As shown in figure 1, the electric fuse structure is formed on fleet plough groove isolation structure (STI) 100 in the semiconductor substrate, it is wrapped silk structure
Anode 101 and negative electrode 103, and the fuse 102 for the fine strip shape being connected between anode 101 and negative electrode 103 with both are included,
Its Anodic 101 and the surface of negative electrode 103 have contact plunger 104.When passing through larger moment between anode 101 and negative electrode 103
During electric current, fuse 102 is blown.According to 102 actual bar of fuse is wide and thickness, the specific electric current to fuse needed for fuse 102 is not to the utmost
It is identical, usually hundreds of milliamperes.It is low resistance state (such as resistance is R) in the state of fuse 102 is not blown, at electric fuse structure,
It is high-impedance state in the state of after fuse 102 is blown, at electric fuse structure (such as resistance is infinitely great).
Characteristic that low-resistance converts to high resistant can be realized by electric current because it has, electric fuse structure is except in redundant circuit
In application outside, also have widely application, such as：Built-in self-test (Build in self test, abbreviation BIST) technology, from
Recovery technique, one-time programming (One Time Program, abbreviation OTP) chip, on-chip system (System On Chip, abbreviation
SoC) etc..
In the prior art, it is as follows with reference to figure 1, the forming method of electric fuse structure：
Step S11, there is provided Semiconductor substrate, fleet plough groove isolation structure 100 is formed in the Semiconductor substrate；
Step S12, polysilicon layer is formed on the surface of fleet plough groove isolation structure 100, is formed on the surface of polysilicon layer
Patterned mask layer, using the patterned mask layer as mask etching polysilicon layer, formation both ends are roomy, and and both ends
The semiconductor structure for the intermediate elongated being connected.
Step S13, the mask layer is removed, form metal silicide in the semicon-ductor structure surface, partly led described
The metal silicide surface at the both ends of body structure forms conductive plunger 104, forms anode 101 and negative electrode 103, the anode 101
Elongated semiconductor structure between negative electrode 103 is fuse 102.
However, electric fuse structure that prior art is formed and forming method thereof is single, and generally forming planar transistor
When form electric fuse, how to realize the variation of electric fuse structure and forming method, for example, formed non-planar transistor (example
Such as all-around-gate transistor (Gate-All-Around, GAA), fin formula field effect transistor) electric fuse is formed, turn into and need solution badly
Certainly the problem of.
More the relevant information on electric fuse structure refers to Publication No. US20050214982A1 United States Patent (USP) Shen
Please.
The content of the invention
It is of the invention to solve the problems, such as to be to provide electric fuse structure and forming method thereof, semiconductor devices and forming method thereof,
Realize the variation of electric fuse structure and forming method.
To solve the above problems, the embodiment provides a kind of forming method of electric fuse structure, including：There is provided
Semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate include top-layer semiconductor；Etch the top layer semiconductors
Layer forms nano wire, and the nano wire is used to form the electric fuse structure for including negative electrode, anode and fuse area；In the nano wire
Both ends doping, form the negative electrode and anode of electric fuse structure, and the fuse area between the negative electrode and anode.
Alternatively, in addition to：Before the negative electrode and anode of electric fuse is formed, adulterated among nano wire, formation has
The fuse area of doping.
Alternatively, in addition to：Multiple conductive plungers are formed, the multiple conductive plunger is respectively at the negative electrode and anode electricity
Connection.
Accordingly, inventor additionally provides a kind of electric fuse structure, including：Semiconductor-on-insulator substrate, the insulation
Body semiconductor substrate thereon includes backing bottom, the buried oxide layer for covering backing basal surface and covering buried oxide layer surface
Top-layer semiconductor；Positioned at the nano wire of the buried oxide layer surface, the nano wire is by the top-layer semiconductor
Formed, the electric fuse structure of negative electrode, anode and fuse area is included for being formed；Wherein, the negative electrode and sun of the electric fuse structure
Pole is located at the both ends of the nano wire respectively, and it is internal with doping；The fuse area of the electric fuse structure is located at negative electrode and sun
Between pole.
Alternatively, there is doping in the fuse area.
Alternatively, in addition to：Cover the interlayer dielectric layer of the negative electrode, anode and fuse area；Through the inter-level dielectric
Multiple conductive plungers of layer, the conductive plunger electrically connect with the negative electrode and anode respectively.
Accordingly, inventor additionally provides a kind of forming method of semiconductor devices, including：Semiconductor-on-insulator is provided
Substrate, it is buried that the semiconductor-on-insulator substrate includes backing bottom, the buried oxide layer for covering backing basal surface and covering
The top-layer semiconductor of oxide layer surface；Etch the top-layer semiconductor and form the first nano wire and therewith discrete second
Nano wire；At least remove the buried oxide layer of segment thickness, make the centre of the first nano wire and the second nano wire hanging and two
End has support；Centre to be formed forms vacantly and after the first nano wire of the both ends with support and covers first nano wire
The grid structure on surface；After forming the grid structure, adulterate to form all-around-gate transistor at the both ends of the first nano wire
Source electrode and drain electrode；The negative electrode and anode to form electric fuse structure are adulterated at the both ends of second nano wire, and positioned at described
Fuse area between negative electrode and anode.
Alternatively, the source electrode for forming all-around-gate transistor and the step of drain electrode and the formation electric fuse structure
Negative electrode and anode the step of carry out simultaneously.
Alternatively, in addition to：Before forming grid structure, to middle hanging and both ends have support the first nano wire and
Doping among second nano wire, form middle the first nano wire with doping and middle the second nano wire with doping.
Alternatively, hanging to centre and both ends have the middle doping of the first nano wire and the second nano wire of support
Ionic type with the first nano wire both ends adulterate ionic type and second nano wire both ends adulterate from
Subtype is identical.
Alternatively, in addition to：The first nano wire and middle the second nano wire with doping with doping among being formed
Afterwards, first nano wire and the surface of the second nano wire and two end faces are repaired.
Alternatively, the technique used of repairing is annealing process or thermal oxidation technology.
Alternatively, in addition to：Form the interlayer dielectric layer for covering the all-around-gate transistor and electric fuse structure；Institute
State and multiple conductive plungers are formed in interlayer dielectric layer, the multiple conductive plunger source electrode with the all-around-gate transistor respectively
With the electrical connection of the negative electrode and anode of drain electrode and electric fuse structure.
Alternatively, the technique of the etching top-layer semiconductor is for anisotropic dry etch process or respectively to different
The wet-etching technology of property.
Alternatively, the chemical reagent that the wet-etching technology uses is potassium hydroxide, ammoniacal liquor or tetramethyl aqua ammonia.
Alternatively, the technique of the buried oxide layer for removing segment thickness is isotropic wet-etching technology,
And etching liquid is acid solution.
Alternatively, the acid solution is hydrofluoric acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid.
Accordingly, inventor additionally provides a kind of semiconductor devices, including：Semiconductor-on-insulator substrate, the insulation
Body semiconductor substrate thereon includes backing bottom, the buried oxide layer for covering backing basal surface and covering buried oxide layer surface
Top-layer semiconductor；All-around-gate transistor and the electric smelting isolated therewith positioned at the semiconductor-on-insulator substrate surface
Silk structure；Wherein, the all-around-gate transistor includes the first nano wire as channel region, covers first nano wire
Grid structure and the source electrode positioned at the grid structure both sides and drain electrode, first nano wire is by etching the top layer half
Formed after conductor layer；The electric fuse structure is included as the fuse area being located among the second nano wire, and positioned at described the
The negative electrode and anode at two nano wire both ends.
Alternatively, mixed in the anode and negative electrode of the source electrode of the all-around-gate transistor and drain electrode and electric fuse structure
Miscellaneous ionic type is identical.
Alternatively, there is doping in the fuse area of the channel region of the all-around-gate transistor and electric fuse structure, it is described
Doped ions type and the source electrode and the sun of drain electrode and electric fuse structure of all-around-gate transistor in channel region and fuse area
Pole is identical with the ionic type adulterated in negative electrode.
Alternatively, the material of the electric fuse structure is WSi2、CoSi2Or NiPtSi.
Accordingly, inventor additionally provides a kind of forming method of electric fuse structure, including：Semiconductor substrate, institute are provided
Stating Semiconductor substrate has raised fin, and the fin has the first doping type；Ion is carried out to the top of the fin
Doping, forms the electric fuse with the second doping type, and second doping type is opposite with first doping type；Formed
Cover the interlayer dielectric layer of the electric fuse surface and Semiconductor substrate；The multiple conductions formed in the interlayer dielectric layer
Connector, the multiple conductive plunger electrically connect with the both ends of electric fuse respectively.
Alternatively, the Semiconductor substrate includes well region and is formed at the doped region on the well region surface, the doped region
There is opposite doping type with well region.
Alternatively, in addition to：Before carrying out ion doping to the top of the fin, the top of the covering fin is formed
Silicon layer.
Alternatively, in addition to：The metal silicide layer for covering the fin top surface is formed, the conductive plunger is located at
The metal silicide layer surface.
Alternatively, first doping type adulterates for p-type, and second doping type is n-type doping；Or described
One doping type is n-type doping, and second doping type adulterates for p-type.
Alternatively, the forming method of the conductive plunger includes：Formed on the surface of the interlayer dielectric layer patterned
Mask layer；Using the patterned mask layer as mask, etch the interlayer dielectric layer and form opening, the bottom dew of the opening
Go out the electric fuse；Conductive material is filled into the opening, forms conductive plunger.
Accordingly, inventor additionally provides a kind of electric fuse structure, including：Semiconductor substrate, the Semiconductor substrate tool
There is the fin of projection, the fin has the first doping type；Electric fuse with the second doping type, the electric fuse to
Adulterate to be formed positioned at the top of the fin, second doping type is opposite with first doping type；Cover the electricity
Fuse surface and the interlayer dielectric layer of Semiconductor substrate；Multiple conductive plungers in the interlayer dielectric layer, it is the multiple
Conductive plunger electrically connects with the both ends of electric fuse respectively.
Alternatively, the Semiconductor substrate includes well region and is formed at the doped region on the well region surface, the doped region
There is opposite doping type with well region.
Alternatively, in addition to：Cover the silicon layer at the top of the fin.
Alternatively, in addition to：The metal silicide layer of the fin top surface is covered, the conductive plunger is positioned at described
Metal silicide layer surface.
Alternatively, first doping type adulterates for p-type, and second doping type is n-type doping；Or described
One doping type is n-type doping, and second doping type adulterates for p-type.
Accordingly, inventor additionally provides a kind of forming method of semiconductor devices, including：Semiconductor substrate, institute are provided
Stating Semiconductor substrate has raised the first fin and the second fin, has fleet plough groove isolation structure between adjacent fin, described
First fin and the second fin have the first doping type；Adulterated to the top of second fin, being formed has the second doping
The electric fuse of type；Form the fin formula field effect transistor with the first fin, the forming step bag of the fin field effect pipe
Include：It is developed across the top of first fin and the grid structure of side wall；Using the grid structure as mask, to described first
Adulterated in fin, form the source electrode with the second doping type and drain electrode；Formed and cover the fin formula field effect transistor and electricity
The interlayer dielectric layer of fuse；
Formed through the interlayer dielectric layer multiple conductive plungers, the conductive plunger respectively with fin field effect crystal
The both ends of the source electrode of pipe and drain electrode and electric fuse electrically connect.
Alternatively, the Semiconductor substrate includes well region and is formed at the doped region on the well region surface, the doped region
There is opposite doping type with well region.
Alternatively, the technique for forming source electrode and drain electrode and the top doping to second fin is in same work
Formed in skill step.
Alternatively, in addition to：Before forming source electrode, drain electrode and electric fuse, formed and cover the first of the grid structure both sides
The silicon layer at the top of fin top surface and the second fin.
Alternatively, in addition to：Formed and cover the source electrode and the metal silicide layer at the top of drain electrode and the second fin,
The conductive plunger electrically connects with the metal silicide layer.
Alternatively, first doping type adulterates for p-type, and second doping type is n-type doping；Or described
One doping type is n-type doping, and second doping type adulterates for p-type.
Accordingly, inventor additionally provides a kind of semiconductor devices, including：Semiconductor substrate, the Semiconductor substrate tool
There are the first fin and the second fin of projection, there is fleet plough groove isolation structure, first fin and second between adjacent fin
Fin has the first doping type；Electric fuse with the second doping type, the electric fuse is from the top to second fin
Formed after portion's doping；Fin formula field effect transistor with the first fin, the fin field effect pipe include：Across described first
The top of fin and the grid structure of side wall；And the source electrode in the first fin of the grid structure both sides and drain electrode,
The source electrode and drain electrode have the second doping type；Cover the interlayer dielectric layer of the fin formula field effect transistor and electric fuse；
Through multiple conductive plungers of the interlayer dielectric layer, the conductive plunger source electrode with fin formula field effect transistor and leakage respectively
Pole and the electrical connection of the both ends of electric fuse.
Alternatively, in addition to：Cover the first fin top surface and the top of the second fin of the grid structure both sides
Silicon layer.
Alternatively, the Semiconductor substrate includes well region and is formed at the doped region on the well region surface, the doped region
There is opposite doping type with well region.
Alternatively, in addition to：The metal silicide layer at the top of the source electrode and drain electrode and the second fin is covered, it is described
Conductive plunger electrically connects with the metal silicide layer.
Alternatively, first doping type adulterates for p-type, and second doping type is n-type doping；Or described
One doping type is n-type doping, and second doping type adulterates for p-type.
Compared with prior art, technical scheme has advantages below：
The forming method of the electric fuse structure of the embodiment of the present invention, after etching forms nano wire, the two of the nano wire
End doping forms electric fuse structure, and such a forming method is simple, and the electric fuse structure of formation is novel, realizes the electric fuse to be formed
The diversity of structure.
The nano wire that the electric fuse structure of the embodiment of the present invention is adulterated by both ends is formed, and its is simple in construction, the knot of electric fuse
Structure is various.
Further, there is provided a kind of forming method of semiconductor devices, form the first nano wire on a semiconductor substrate
Discrete second nano wire therewith, first nano wire are subsequently formed all-around-gate transistor, and after second nano wire
It is continuous to form electric fuse structure, the diversity of the forming method of semiconductor devices is realized, and electric fuse structure is novel.
Further, the source electrode for forming all-around-gate transistor and the step of drain electrode and the formation electric fuse knot
The step of the step of negative electrode and anode of structure carries out, that is, forms the electric fuse structure simultaneously colonizes in form all-around-gate crystal
Among the step of pipe, during forming the semiconductor devices, extra processing step will not be increased, its production cost is low.
Accordingly, because the electric fuse structure and all-around-gate transistor are located at same semiconductor-on-insulator substrate
In, the structure of the semiconductor devices is novel, and its application is wider.
Embodiments of the invention additionally provide a kind of forming method of electric fuse structure, after forming the fin of projection, in institute
The top doping of fin is stated, electric fuse is formed, realizes the variation of electric fuse structure.Also, Semiconductor substrate and fin top
The doping type in portion is on the contrary, Semiconductor substrate and fin top composition P-N junction, are effectively isolated electric fuse, its cost is low, starts
The precedent of electric fuse is directly formed on the active area.
For the electric fuse structure by being formed after the top of fin is adulterated, its structure is novel, realizes electric fuse structure
Variation.Also, due to the doping type at the top of Semiconductor substrate and fin on the contrary, forming P- at the top of Semiconductor substrate and fin
N is tied, and is effectively isolated electric fuse, its cost is low.
Further, there is provided a kind of forming method of semiconductor devices, form the first fin on the same semiconductor substrate
Portion and the second fin, first fin are used to form fin formula field effect transistor, and second fin is then used to form electric smelting
Silk structure, realize the diversity for the semiconductor devices to be formed.Also, the doping class at the top of the Semiconductor substrate and fin
Type is effectively isolated electric fuse, its cost is low on the contrary, Semiconductor substrate and fin top composition P-N junction.
Further, the technique for forming source electrode and drain electrode and the top doping to second fin is same
Among the step of being formed in processing step, that is, forming electric fuse structure parasitizes the step of forming fin formula field effect transistor, no
Extra processing step can be increased, forming method is simple, and production cost is low.
Accordingly, there is provided semiconductor devices in, including the electric fuse structure positioned at same semi-conductive substrate and fin field
Effect transistor, the structure diversification of the semiconductor devices, application are wider.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the electric fuse of prior art；
Fig. 2A-Figure 15 C are the cross-sectional views of the forming process of the semiconductor devices of first embodiment of the invention；
Figure 16 is the cross-sectional view of the forming process of the electric fuse structure of second embodiment of the invention；
Figure 17-Figure 26 is the cross-sectional view of the forming process of the semiconductor devices of third embodiment of the invention；
Figure 27 and Figure 28 is the cross-sectional view of the forming process of the electric fuse structure of fourth embodiment of the invention；
Figure 29 is the cross-sectional view of the forming process of the electric fuse structure of fifth embodiment of the invention.
Embodiment
As described in background, prior art generally forms electric fuse when forming planar transistor, its forming method
And structure is more single.
After research, the forming method and structure of semiconductor devices are inventor provided, complete surround can formed respectively
Gate transistor and the method and structure of electric fuse are formed simultaneously, and form electric smelting while fin formula field effect transistor is formed
Silk, effectively realizes the method and structure diversity to form semiconductor devices.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
First embodiment
In the first embodiment of the present invention, inventor provide one kind and form electric smelting when forming all-around-gate transistor
The forming method and structure of silk.
Incorporated by reference to reference to figure 2A, 2B, 2C, wherein, Fig. 2A is the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey, Fig. 2 B are cross-sectional views of the Fig. 2A along X-X ' directions；Fig. 2 C are Fig. 2A along Y-Y ' directions
Cross-sectional view.
It should be noted that for ease of understanding the present invention, in an embodiment of the present invention, along the cross-section structure in X-X ' directions
Schematic diagram merely illustrates the structure on the section.
There is provided includes first area I and second area II semiconductor-on-insulator substrate (SOI) 200, wherein described the
One region I is used to form all-around-gate transistor, and the second area II is used to form electric fuse structure.
The semiconductor-on-insulator substrate 200 is used to provide platform for subsequent technique, and forms nano wire.The insulation
Body semiconductor substrate thereon 200 includes backing bottom 201, the buried oxide layer (BOX) 203 on the surface of covering backing bottom 201 and covering
The top-layer semiconductor 205 on the surface of buried oxide layer 203.Wherein, the top-layer semiconductor 205 subsequently is etched to be formed and received
Rice noodles, its material are monocrystalline silicon or monocrystalline germanium.
In embodiments of the invention, the material at the backing bottom 201 is monocrystalline silicon, and doped with p-type ion；It is described buried
The material of oxide skin(coating) 203 is silica, and the material of the top-layer semiconductor 205 is monocrystalline silicon.
Please continue to refer to Fig. 2A, 2B, 2C, the first mask positioned at the surface of semiconductor-on-insulator substrate 200 is formed
Layer 207, first mask layer 207 defines first area I and second area II nano wire.
First mask layer 207 is used in subsequent etching top-layer semiconductor 205 as mask.The first of the present invention
In embodiment, the material of first mask layer 207 is photoresistance (PR) material, the technique such as its formation process is exposure, development,
This is repeated no more.
, can be with it should be noted that in other embodiments of the invention：Before the first mask layer 207 is formed, formed
Cover the hard mask layer (not shown) on the semiconductor-on-insulator substrate surface.The material of the hard mask layer be silica,
Silicon nitride or silicon oxynitride, for protecting semiconductor-on-insulator substrate surface, it will not be repeated here.
Fig. 3 A, 3B, 3C are refer to, wherein, Fig. 3 A are the forming process of the semiconductor devices of first embodiment of the invention
Overlooking the structure diagram；Fig. 3 B are cross-sectional views of Fig. 3 A along X-X ' directions；Fig. 3 C are Fig. 3 A cuing open along Y-Y ' directions
Face structural representation.
With first mask layer 207 (refer to Fig. 2A, 2B, 2C) for mask, the top-layer semiconductor 205 is etched
(as shown in figure Fig. 2A, 2B, 2C) until exposing buried oxide layer 203, formation is located at first area I the first nano wire
205a and the second nano wire 205b positioned at second area II；And formed the first nano wire 205a and the second nano wire 205b it
Afterwards, first mask layer 207 is removed.
The technique for etching the top-layer semiconductor 205 is anisotropic dry etching or wet-etching technology.At this
In the embodiment of invention, the top-layer semiconductor 205, the wet etching are etched using anisotropic wet-etching technology
The chemical reagent that technique uses is potassium hydroxide (KOH), ammoniacal liquor (NH4) or tetramethyl aqua ammonia (TMAH) OH.Due to above-mentioned
Chemical reagent in the surface direction of top-layer semiconductor 205 etch rate it is very fast, can quickly remove and be covered exposed to first
Top-layer semiconductor 205 outside film layer 207.
It should be noted that in other embodiments of the invention, anisotropic dry etch process can also be used
Etch the top-layer semiconductor 205.
The first nano wire 205a is used for the follow-up channel region as all-around-gate transistor.First nano wire
205a material is identical with the material of top-layer semiconductor 205, is monocrystalline silicon or monocrystalline germanium.It is described in embodiments of the invention
First nano wire 205a material is monocrystalline silicon.
The second nano wire 205b is used to be subsequently formed electric fuse structure.The material of the second nano wire 205b and top
The material of layer semiconductor layer 205 is identical, is monocrystalline silicon or monocrystalline germanium.In embodiments of the invention, shown second nano wire 205b
Material be monocrystalline silicon.
After forming the first nano wire 205a and the second nano wire 205b, first mask layer 207 is removed, in favor of follow-up
The progress of technique.In embodiments of the invention, first mask layer 207 is removed using cineration technics or etching technics.
Incorporated by reference to reference to figure 4A, 4B, 4C, wherein, Fig. 4 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey；Fig. 4 B are cross-sectional views of Fig. 4 A along X-X ' directions；Fig. 4 C are Fig. 4 A along Y-Y ' directions
Cross-sectional view.
Formed positioned at the first nano wire 205a both ends, the second nano wire 205b both ends and buried oxide layer 203
Second mask layer 209 on surface.
Second mask layer 209 is used for be subsequently formed the first hanging nano wire 205a and the second hanging nano wire
205b prepares.In embodiments of the invention, the material of second mask layer 209 is photoresist, and its formation process includes
The techniques such as exposure, development.
It should be noted that X-X ' the pointing needles in Fig. 4 A are to the second nano wire 205b.Therefore, is illustrate only in Fig. 4 B
Two nano wire 205b.
Incorporated by reference to reference to figure 5A, 5B, 5C, wherein, Fig. 5 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey；Fig. 5 B are cross-sectional views of Fig. 5 A along X-X ' directions；Fig. 5 C are Fig. 5 A along Y-Y ' directions
Cross-sectional view.
Be mask with second mask layer 209, at least remove segment thickness buried oxide layer 203 (such as Fig. 4 A,
Shown in 4B, 4C), make the first nano wire 205a and the second nano wire 205b centre hanging, and both ends have support.
The buried oxide layer 203 for removing segment thickness is used to make the first nano wire 205a and the second nano wire 205b
It is middle hanging, and both ends have support, form space 208, are received in favor of subsequently there is enough spaces to form covering described first
Rice noodles 205a gate dielectric layer and gate electrode layer.The technique of the buried oxide layer 203 for removing segment thickness is each to same
The wet-etching technology of property, and etching liquid is acid solution, such as hydrofluoric acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid etc., with more
The fast removal buried oxide layer 203.In an embodiment of the present invention, the hidden of the segment thickness is removed using hydrofluoric acid
Bury oxide skin(coating) 203 so that remaining part buried oxide layer 203a and the first nano wire 205a, the second nano wire 205b it
Between there is space 208.
, can be with it should be noted that in other embodiments of the invention：Remove outside the second mask layer 209
Full depth buried oxide layer 203, as long as making the first nano wire 205a and the second nano wire 205b hanging, subsequently there is foot
Enough spaces form the gate dielectric layer and gate electrode layer for covering the first nano wire 205a.
Incorporated by reference to reference to figure 6A, 6B, 6C, wherein, Fig. 6 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey；Fig. 6 B are cross-sectional views of Fig. 6 A along X-X ' directions；Fig. 6 C are Fig. 6 A along Y-Y ' directions
Cross-sectional view.
Be mask with second mask layer 209, to middle hanging and both ends have support the first nano wire 205a and
Doping among second nano wire 205b, formation are middle with the first nano wire 205c adulterated and middle with adulterate second
Nano wire 205d.
And both ends hanging to the centre have to be adulterated in the first nano wire 205a (as shown in Figure 8) of support, after being used for
The carrier mobility of the continuous channel region for improving all-around-gate transistor.And both ends hanging to the centre have the of support
Adulterate in two nano wire 205b (as shown in Figure 8), for subsequently when the second source electrode and the second drain electrode apply electric current, doping from
Son is assembled in the second nano wire 205d one end, causes the change of resistance of the second nano wire 205d on Y-Y ' directions everywhere,
The second nano wire 205d somewhere resistance on Y-Y ' directions is increased to certain value or is fused, can subsequently be used as electric fuse
The fuse area of structure uses.
The ionic type of the doping can be selected according to actual conditions, both can be N-type ion or p-type
Ion.In an embodiment of the present invention, N-type heavy doping may be selected.
It should be noted that in embodiments of the invention, centre has the first nano wire 205c of doping, centre with mixing
Section shapes of the second miscellaneous nano wire 205d along X-X ' directions remains as square.
It should be noted that in other embodiments of the invention, there is the first nano wire of doping among the formation
There is the step of the second nano wire 205d of doping alternative to perform for 205c and centre.
Incorporated by reference to reference to figure 7A, 7B, 7C, wherein, Fig. 7 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey；Fig. 7 B are cross-sectional views of Fig. 7 A along X-X ' directions；Fig. 7 C are Fig. 7 A along Y-Y ' directions
Cross-sectional view.
Have among being formed doping the first nano wire 205c (as shown in Fig. 6 A, 6B, 6C) and centre with the adulterated
After two nano wire 205d (as shown in Fig. 6 A, 6B, 6C), second mask layer 209 (as shown in Fig. 6 A, 6B, 6C) is removed, and it is right
The first nano wire 205c and the second nano wire 205d surface and two end faces is repaired, and is formed and is wrapped up the doping
First nano wire 205e and the second nano wire 205f of doping repair layer 211.
The technique for removing second mask layer 209 is cineration technics or etching technics.Due to removing second mask
The technique of layer 209 is well known to those skilled in the art, and will not be repeated here.
Inventor has found that strong impact power during abovementioned dopant technique is easily to the first nano wire 205c and the second nano wire
205d causes on surface to damage, also, when removing second mask layer 209, also easily to the first nano wire 205c and second
Nano wire 205d surfaces and respective two end faces cause to damage, and influence the performance of semiconductor devices being subsequently formed.If
The the first nano wire 205c damaged and the second nano wire 205d surfaces and two end faces are repaired, are favorably improved half
The performance of conductor device.The reparation can use annealing process or thermal oxidation technology.
In the first embodiment of the present invention, it is preferred to use thermal oxidation technology is to the first nano wire 205c and the second nano wire
205d surfaces and two end faces are repaired, and can not only form second nanometer of parcel the first nano wire 205e and doping
Line 205f repair layer 211, and the section shape of the first nano wire 205e and the second nano wire 205f along X-X ' directions after reparation
Shape is become round by square, can further increase the grid width of all-around-gate transistor, is improved and is surrounded entirely in semiconductor devices
The performance of gate transistor.In the first embodiment of the present invention, the material of the repair layer 211 is silica, by oxidized portion
Obtained after one nano wire 205c and part the second nano wire 205d.
It should be noted that the step of above-mentioned formation repair layer 211 can selectivity execution.Except that formed
Repair layer 211 contributes to reparation abovementioned dopant technique to be damaged to caused by nano wire, beneficial to the performance for improving semiconductor devices.
Incorporated by reference to reference to figure 8A, 8B, 8C, wherein, Fig. 8 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey, also, it is of the invention for ease of understanding, the grid structure in Fig. 8 A is shown in broken lines, and in Fig. 8 A
X-X ' directions are directed to the first nano wire 205e；Fig. 8 B are cross-sectional views of Fig. 8 A along X-X ' directions；Fig. 8 C are figure
Cross-sectional views of the 8A along Y-Y ' directions.
Repair after forming the first nano wire 205e and the second nano wire 205f, remove part repair layer 211, only retain support
First nano wire 205e and the second nano wire 205f part repair layer 211, formed and cover the first nano wire 205e surfaces
Grid structure 213.
Wherein, the forming step of the grid structure 213 includes：Form the grid for covering the first nano wire 205e surfaces
Dielectric layer 213a；Form the gate electrode layer 213b for covering the gate dielectric layer 213a.Wherein, the material of the gate dielectric layer 213a
For silica or high K dielectric, the material of the gate electrode layer 213b is polysilicon or metal, be will not be repeated here.
It should be noted that in embodiments of the invention, the first nano wire 205e of the support He of part repair layer 211
Gate dielectric layer 213a wraps up the first nano wire 205e jointly.
It should be noted that due to second area II and without forming all-around-gate transistor, therefore, grid knot is being formed
Before structure 213, second area II the second nano wire 205f can be first covered using photoresist layer 212, will not be repeated here.
Incorporated by reference to reference to figure 9A, 9B, 9C, wherein, Fig. 9 A are the formation of the semiconductor devices of first embodiment of the invention
The overlooking the structure diagram of journey；Fig. 9 B are cross-sectional views of Fig. 9 A along X-X ' directions；Fig. 9 C are Fig. 9 A along Y-Y ' directions
Cross-sectional view.
The part of grid pole structure 213 exposed is etched, and the side wall of remaining grid structure 213 forms side wall after etching
216.Gate electrode layer 213b after etching in remaining grid structure 213 is subsequently used for the grid as all-around-gate transistor.
The side wall 216 is then used to protect remaining grid structure 213 not to be damaged when subsequently adulterating, and defines source electrode and drain electrode.
The material of the side wall 216 is silicon nitride, silicon oxynitride etc..
It should be noted that in the step of foregoing etched portions repair layer 211, positioned at the buried oxide layer 203
The part repair layer 211 that the first nano wire 205e of support is played on surface is not removed, the part repair layer 211 not being removed
As shown in Figure 9 B.
Incorporated by reference to reference to figure 10A, 10B, 10C, wherein, Figure 10 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process；Figure 10 B are cross-sectional views of Figure 10 A along X-X ' directions；Figure 10 C are Figure 10 A edges
The cross-sectional view in Y-Y ' directions.
The photoresist layer 212 is removed, and forms the 4th mask layer 218 positioned at the second nano wire 205f surfaces, it is described
4th mask layer 218 is located at the second area II top of space 208, and exposes the second nano wire 205f both ends.The present invention
Embodiment in, the 4th mask layer 218 is photoresist layer.
Incorporated by reference to reference to figure 11A, 11B, 11C, wherein, Figure 11 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process, for ease of understanding the present invention, the first source region 219 being covered, the are shown in Figure 11 A
One drain region 221, the second source region 223 and the second drain region 225；Figure 11 B are cross-sectional views of Figure 11 A along X-X ' directions；Figure
11C is cross-sectional views of Figure 11 A along Y-Y ' directions.
With the grid structure 213, the mask layer 218 of side wall 216 and the 4th for mask, to described first nanometer exposed
Line 205c and the second nano wire 205d both ends adulterate, formed positioned at first area I the first source region 219 and the first drain region 221,
And the second source region 223 positioned at second area II and the second drain region 225.
The drain region 221 of first source region 219 and first is used to be subsequently formed source electrode and the leakage as all-around-gate transistor
Pole.The drain region 225 of second source region 223 and second is used for follow-up negative electrode and anode as electric fuse structure, follow-up described the moon
Pole and anode each electrically connect with conductive plunger, make have electric current to pass through inside the fuse area between negative electrode and anode.This hair
In bright embodiment, first source region 219, the first drain region 221, the second source region 223 and the second drain region 225 walk in same technique
Formed in rapid, i.e., carry out simultaneously, extra processing step will not be increased.
It should be noted that in an embodiment of the present invention, to middle vacantly first nano wire of the both ends with support
The ionic species that the ionic type of doping adulterates with the both ends to the first nano wire 205c among 205c and the second nano wire 205d
Type and the ionic type adulterated to the both ends of the second nano wire 205d are identical.
Incorporated by reference to reference to figure 12A, 12B, 12C, wherein, Figure 12 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process；Figure 12 B are cross-sectional views of Figure 12 A along X-X ' directions；Figure 12 C are Figure 12 A edges
The cross-sectional view in Y-Y ' directions.
Formed and cover first source region 219, the first drain region 221, the second source region 223 and the gold on the surface of the second drain region 225
Belong to silicide layer 226.The metal silicide layer 226 is used to subsequently reducing conductive plunger 229 and first source region 219, the
The contact resistance of interface between one drain region 221, the second source region 223 and the second drain region 225.
Incorporated by reference to reference to figure 13A, 13B, 13C, wherein, Figure 13 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process；Figure 13 B are cross-sectional views of Figure 13 A along X-X ' directions；Figure 13 C are Figure 13 A edges
The cross-sectional view in Y-Y ' directions.
After forming metal silicide layer 226, remove the 4th mask layer 218 (as shown in Figure 12 A, 12B).Remove described
The technique of four mask layers 218 is etching technics or cineration technics, be will not be repeated here.
Incorporated by reference to reference to figure 14A, 14B, 14C, wherein, Figure 14 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process；Figure 14 B are cross-sectional views of Figure 14 A along X-X ' directions；Figure 14 C are Figure 14 A edges
The cross-sectional view in Y-Y ' directions.
After removing the 3rd mask layer and the 4th mask layer, formed and cover the grid structure 213, side wall 216, metal silication
The interlayer dielectric layer 227 of nitride layer 226, repair layer 211 and buried oxide layer 203.
The interlayer dielectric layer 227 is used to subsequently isolate the conducting elements such as adjacent conductive plunger, all-around-gate transistor.
The material of the interlayer dielectric layer 227 is silica, silicon nitride or silicon oxynitride etc., and its formation process is chemical vapor deposition work
Skill, it will not be repeated here.In embodiments of the invention, the material of the interlayer dielectric layer 227 is silicon oxynitride, also, described
The full space 208 (as shown in Figure 13 B) of the filling of interlayer dielectric layer 227, wraps up the second nano wire 205f, due to interlayer dielectric layer
227 capacity of heat transmission is weaker, and when subsequently applying current to electric fuse structure, heat can not expand in time caused by electric fuse structure
Dissipate, therefore, the change in resistance of electric fuse structure can be larger, helps to fuse.
It should be noted that when formed with metal silicide layer 226, the metal silicide layer 226 is also electric fuse
A part for structure.Therefore, the material of the electric fuse structure is autoregistration polysilicon thing (salicide) or non-silicide
, such as WSi (non-silicide)2、CoSi2Or NiPtSi etc..
Incorporated by reference to reference to figure 15A, 15B, 15C, wherein, Figure 15 A are the shape of the semiconductor devices of first embodiment of the invention
Into the overlooking the structure diagram of process；Figure 15 B are cross-sectional views of Figure 15 A along X-X ' directions；Figure 15 C are Figure 15 A edges
The cross-sectional view in Y-Y ' directions.
The multiple conductive plungers 229 formed in the interlayer dielectric layer 227, the multiple conductive plunger 229 are distinguished
Electrically connected with the first source region 219, the first drain region 221, the second source region 223 and the second drain region 225.
The conductive plunger 229 is used for the source electrode and drain electrode, the negative electrode of electric fuse structure for electrically connecting all-around-gate transistor
And anode, that is, electrically connect the first source region 219, the first drain region 221, the second source region 223 and the second drain region 225.The conductive plunger
229 forming step includes：Etch the interlayer dielectric layer 227 and form multiple openings (not indicating), the multiple opening difference
Expose the first source region 219, the first drain region 221, the second source region 223 and the surface of the second drain region 225；Filled out into the multiple opening
Fill conductive material and form conductive plunger 229.The material of the conductive plunger 229 is tungsten, copper, aluminium etc..In embodiments of the invention
In, because the first source region 219, the first drain region 221, the second source region 223 and the surface of the second drain region 225 are covered with metal silicide layer
226, therefore, the opening exposes the surface of metal silicide layer 226.Also, the multiple conductive plunger 229 is in same technique
Formed in step, effectively save processing step.
After the completion of above-mentioned steps, the semiconductor devices of first embodiment of the invention completes.Because electric fuse uses
Nano wire is made, and the channel region of all-around-gate transistor is also made of nano wire.Therefore, all-around-gate crystalline substance can formed
Electric fuse is formed while the channel region of body pipe.Also, the negative electrode and anode of electric fuse structure are also forming all-around-gate crystal
Formed while the source electrode of pipe and drain electrode, extra processing step will not be increased, formation process is simple, and adds realization and partly lead
The diversity of body device, application are wider.
Accordingly, continuing with combining with reference to figure 15A, 15B, 15C, inventor additionally provides a kind of semiconductor devices, including：
Semiconductor-on-insulator substrate (does not indicate), and the semiconductor-on-insulator substrate includes backing bottom 201, the covering back of the body
The buried oxide layer 203 on the surface of substrate 201 and the top-layer semiconductor on covering buried oxide layer 203a surfaces (are not marked
Show)；
Positioned at the all-around-gate transistor (not indicating) on the semiconductor-on-insulator substrate surface and the electricity isolated therewith
Fuse-wires structure (does not indicate)；
Wherein, the all-around-gate transistor includes the first nano wire 205e as channel region, covering described first is received
Rice noodles 205e grid structure 213 and the source electrode (i.e. the first source region 219) positioned at the both sides of grid structure 213 and drain electrode
(i.e. the first drain region 221), the first nano wire 205e after etching the top-layer semiconductor by forming；
The electric fuse structure includes the fuse area among the second nano wire 205f, and positioned at described second nanometer
The negative electrode (i.e. the second source region 223) and anode (i.e. the second drain region 225) at line both ends.
In the first embodiment of the present invention, the source electrode of the all-around-gate transistor and drain electrode and electric fuse structure
Anode is identical with the ionic type adulterated in negative electrode；The channel region of the all-around-gate transistor and the fuse area of electric fuse structure
It is interior that there is doping, Doped ions type in the channel region and fuse area and the source electrode of all-around-gate transistor and drain electrode, with
And the anode of electric fuse structure is identical with the ionic type that is adulterated in negative electrode；The material of the electric fuse structure is WSi2、CoSi2
Or NiPtSi.
In the first embodiment of the present invention, in addition to：Positioned at the side wall 216 of the side wall of grid structure 213；Described in covering
The interlayer dielectric layer 227 of all-around-gate transistor, electric fuse structure and buried oxide layer 203；Positioned at the inter-level dielectric
In layer 227, and with the source electrode (the first source region 219) of all-around-gate transistor and drain (the first drain region 221) and electric fuse knot
The conductive plunger 229 of negative electrode (the second source region 223) and anode (the second drain region 225) electrical connection of structure；Positioned at the all-around-gate
The metal silicide layer 226 of the negative electrode and anode surface of the source electrode of transistor and drain electrode and electric fuse structure, with the conduction
Connector 229 electrically connects.
The more description as described in the semiconductor devices, the correlation that refer in the forming method of aforementioned semiconductor device are retouched
State.
In first embodiment of the invention, all-around-gate transistor, in addition to electric smelting are not only included in the semiconductor devices
Silk structure, and the fuse area of the electric fuse structure is formed by nano wire, due to its area of section vertical with the sense of current
Small, resistance is high, easily fuses.And when having doping in the fuse area, it can be made by the migration of carrier in it
The change of portion's resistivity, so as to reach the purpose of fusing.Realize the variation of electric fuse structure and forming method thereof, and half
The integrated level of conductor device is high, and application is wider.
Second embodiment
It is different from first embodiment, in the second embodiment of the present invention, there is provided a kind of forming method of electric fuse structure,
The electric fuse structure might not be parasitized in the forming step of all-around-gate transistor, can be individually in Semiconductor substrate
On nano wire on form electric fuse structure.
It refer to Figure 16, there is provided semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate include backing bottom
301st, the buried oxide layer 303 on the surface of backing bottom 301 and the top layer semiconductors on covering buried oxide layer 303 surface are covered
Layer (not indicating)；Etch the top-layer semiconductor and form hanging nano wire 305f, the nano wire 305f for forming bag
Include the electric fuse structure of negative electrode 323, anode 325 and fuse area；Adulterated at the both ends of the nano wire 305, form electric fuse knot
The negative electrode 323 and anode 325 of structure, and the fuse area (not indicating) between the negative electrode 323 and anode 325.
In the second embodiment of the present invention, in addition to：Before the negative electrode 323 and anode 325 of electric fuse structure is formed,
Doping among nano wire 305f, forms the fuse area with doping, subsequently when applying electric signal, with moving for carrier
Move, cause the resistivity in fuse area everywhere to change, so as to fuse.
It should be noted that after nano wire 305 is formed, can also be to the surface and two end faces of the nano wire 305
Repaired.In the second embodiment of the present invention, the nano wire 305 is repaired using thermal oxidation technology, forms bag
Wrap up in the repair layer 311 of the nano wire 305.
It should be noted that in the second embodiment of the present invention, in addition to：Form the layer for covering the electric fuse structure
Between dielectric layer 327；The multiple conductive plungers 321 formed in interlayer dielectric layer 327, the multiple conductive plunger 321 are distinguished
Electrically connect in the negative electrode 323 and anode 325, applied electrical signals to realizing on negative electrode and anode.
It should be noted that in the second embodiment of the present invention, to reduce conductive plunger 321 and negative electrode 323, anode
The contact resistance of 325 interfaces, it can also include：Formed positioned at the negative electrode 323, the metal silicide layer on the surface of anode 325
326。
After the completion of above-mentioned steps, the electric fuse structure of second embodiment of the invention completes, the electric fuse knot of formation
The processing step of structure is simple, realizes the variation of electric fuse structure forming method.
Meanwhile please continue to refer to the electric fuse structure that Figure 16, the above method are formed, including：
Semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate include backing bottom 301, covering backing basal surface
Buried oxide layer 303 and covering buried oxide layer 303 surface top-layer semiconductor (not indicating)；
Nano wire 305f positioned at the surface of buried oxide layer 303, the nano wire 305f are partly led by the top layer
Body layer is formed, and the electric fuse structure of negative electrode 323, anode 325 and fuse area is included for being formed；
Wherein, the negative electrode 323 of the electric fuse structure and anode 325 are located at the both ends of the nano wire 305f respectively, its
Inside has doping；The fuse area of the electric fuse structure is between negative electrode 323 and anode 325.
In the second embodiment of the present invention, above-mentioned electric fuse structure also includes：Wrap up the repair layer of the electric fuse structure
211, i.e., described repair layer 211 covers the surface and two end faces of the nano wire 305f.The repair layer 211 is received for reparation
Rice noodles 305f, and for further increasing the resistance of electric fuse structure.
It should be noted that in the second embodiment of the present invention, there is doping in the fuse area.Also, above-mentioned electric smelting
Silk structure also includes：Cover the negative electrode 323, the metal silicide layer 326 on the surface of anode 325；Cover the negative electrode 323, sun
Pole 325 and the interlayer dielectric layer 327 of fuse area；Through multiple conductive plungers 321 of the interlayer dielectric layer 327, the conduction
Connector 321 is in contact with metal silicide layer 326, and is electrically connected respectively with the negative electrode 323 and anode 325.
In the second embodiment of the present invention, because the fuse area of the electric fuse structure is formed by nano wire, due to its with
The vertical area of section of the sense of current is small, and resistance is high, easily fuses.And, can when having doping in the fuse area
The change of its internal resistance rate is made by the migration of carrier, so as to reach the purpose of fusing.Realize electric fuse structure and its
The variation of forming method.
3rd embodiment
Different from first and second embodiment of the present invention, in the third embodiment of the present invention, electric fuse structure is forming fin
Formed while field-effect transistor.Also, the technique of the fin formula field effect transistor in first area is divided into high-k gate dielectric layer
In preceding formation process (HK First) and high-k gate dielectric layer at rear formation process (HK Last).In the third embodiment of the present invention
In, electric fuse structure is formed in high-k gate dielectric layer during preceding formation process.
Incorporated by reference to reference to figure 17 and Figure 18, wherein, Figure 17 is the dimensional structure diagram of the forming process of semiconductor devices,
Figure 18 is cross-sectional views of the Figure 17 along A-A1 directions.
First, there is provided Semiconductor substrate 400, the Semiconductor substrate 400 include first area I ' and adjacent thereto the
Two region II ', the first area I ' are used to form fin formula field effect transistor, and the second area II ' is used to form electric smelting
Silk structure, and the surface of Semiconductor substrate 400 of the first area I ' has the first raised fin 401a, the second area
II ' the surface of Semiconductor substrate 400 has the second raised fin 401b.
The Semiconductor substrate 400 is used to provide platform for subsequent technique, and the Semiconductor substrate 400 can be that silicon serves as a contrast
Bottom or germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator (SOI) substrate.Will due to implementing the present invention on a silicon substrate
Cost than implementing the present invention in other above-mentioned Semiconductor substrates (especially silicon-on-insulator substrate) is low, therefore, in this hair
In bright embodiment, the Semiconductor substrate 400 is silicon substrate.
To block bottom interference, well region 400b and position with the first doping type can be formed in Semiconductor substrate 400
The doped region 400a with the second doping type in its bottom, second doping type is with the first doping type on the contrary, making
PN junction is formed between the doped region 400a and well region 400b.In embodiments of the invention, it is contemplated that in Semiconductor substrate 400
Resistivity during the formation p-type doped region 400a of bottom is relative in the bottom of Semiconductor substrate 400 formation n-type doping area 400a
Resistivity it is low, the isolation effect between successive substrates is more preferable, preferably bottom can be blocked to disturb.Therefore, the doped region
400a adulterates for p-type, and the well region 400b is n-type doping.
, can be with it should be noted that in other embodiments of the invention：The doped region 400a is n-type doping, institute
Well region 400b is stated to adulterate for p-type.As long as both form PN junction, can play a part of blocking bottom interference.
It should be noted that in other embodiments of the invention, when the Semiconductor substrate 400 serves as a contrast for silicon-on-insulator
During bottom, the silicon-on-insulator substrate include backing bottom, the buried oxide layer (BOX) positioned at the backing basal surface and
Positioned at the top silicon layer of the buried oxide layer surface.The follow-up first fin 401a and the second fin 401b is by etching institute
Formed after stating top silicon layer.
The first fin 401a is subsequently used for the channel region as fin formula field effect transistor；The second fin 401b
It is subsequently used for being formed the fuse area, negative electrode and anode of electric fuse structure.Also, the first fin 401a and the second fin 401b
By being formed after the well region 400b of etch semiconductor substrates 400, therefore, the first fin 401a and the second fin 401b have the
One doping type.In the third embodiment of the present invention, the first fin 401a and the second fin 401b are in same etching work
Formed in skill, first doping type is n-type doping.
In other embodiments of the invention, the first fin 401a and the second fin 401b doping type can be with
Adulterate, will not be repeated here for p-type.
The fleet plough groove isolation structure (STI) 403 is less than at the top of the first fin 401a and the second fin 401b, and position
Between the first adjacent fin 401a and the second fin 401b, for adjacent fin will to be isolated.The shallow trench every
Material from structure 403 is silica, because the forming method of the fleet plough groove isolation structure 403 is ripe for those skilled in the art
Know technology, will not be repeated here.
Then, the top of the first fin 401a and the grid structure 405 of side wall are developed across.
The grid structure 405 is used for the grid for being subsequently formed fin formula field effect transistor.The shape of the grid structure 405
Include into step：It is developed across the top of the first fin 401a and the gate dielectric layer 406 of side wall；Formed and cover grid Jie
The pseudo- gate electrode layer 407 of matter layer 406.The material of the gate dielectric layer 406 is silica or hafnium, such as HfO2、Al2O3、
ZrO2, HfSiO, HfSiON, HfTaO and HfZrO etc., the material of the pseudo- gate electrode layer 407 is polysilicon.
It should be noted that in embodiments of the invention, in addition to：Before forming grid structure 405, covering described the is formed
The two region II fin 401b of Semiconductor substrate 400 and second photoresist layer.The photoresist layer is forming grid structure 405
Afterwards, it is removed, will not be repeated here before forming doped region.
Figure 19 is refer to, the side wall 408 formed around the grid structure 405, is carved with the side wall 408 for mask
The first fin 401a is lost, the groove 409 formed in the first fin 401a.
The groove 409 is used to subsequently fill stress germanium silicon or stress germanium carbon, to improve fin formula field effect transistor raceway groove
The carrier mobility in area.The groove 409 is shaped as U-shaped or sigma shapes.In embodiments of the invention, it is subsequently formed
The type of fin formula field effect transistor is p-type, and the groove 409 is shaped as sigma shapes, in the range of effective dimensions, sigma
The sharp corner of connected in star 409 is advantageous to subsequently form larger compression in channel region, to improve current-carrying closer to channel region
Transport factor, improve the performance for the fin formula field effect transistor being subsequently formed.
Please continue to refer to Figure 19, stress liner material is filled into the groove 409, forms stress liner layer 410.
The channel region that the stress liner layer 410 is used for subsequently for fin formula field effect transistor provides compression or drawing should
Power.The material of the stress liner layer 410 is selected according to the type of fin formula field effect transistor, such as p-type fin field effect
Transistor is answered generally to choose germanium silicon material, N-type fin formula field effect transistor generally chooses carbofrax material.In the implementation of the present invention
In example, the material of the stress liner layer 410 is germanium silicon.
It should be noted that in other embodiments of the invention, when the class for the fin formula field effect transistor being subsequently formed
When type is N-type, the groove is preferably U-shaped groove, and in the range of effective dimensions, U-shaped groove is advantageous to subsequently be formed in channel region
Larger tension, to improve the carrier mobility of channel region, improve the performance for the fin formula field effect transistor being subsequently formed.
After forming U-shaped groove, the semi-conducting material filled in U-shaped groove is carborundum.
It should be noted that when groove 409 is formed in the first fin 401a, due to partly leading for the second area II '
The fin 401b surfaces of body substrate 400 and second are covered with photoresist layer, the Semiconductor substrate 400 of the second area II ' and
Two fin 401b are not etched.
Figure 20 is refer to, forms the silicon layer (Si Cap) 411 for covering the surface of stress liner layer 410.
The silicon layer 411 can prevent the doping subsequently in stress liner layer 410 from spreading, so that subsequently in stress
Doping depth in laying 410 will not decline too much, so ensure be subsequently formed fin formula field effect transistor source electrode, leakage
The resistivity of pole is low.
It should be noted that in embodiments of the invention, after forming silicon layer 411, remove foregoing covering second area II's '
Photoresist layer, in order to subsequent step.
It should be noted that in other embodiments of the invention, the silicon layer 411 also covers the second fin 401b
Surface, the part silicon layer 411 on the second fin 401b surfaces of the covering subsequently can be also doped, can be as one of doped region
Point.
Figure 21 is refer to, the source electrode 412 formed after forming silicon layer 411 in the first fin 401a and drain electrode 413, with
And the doped region 414 at the top of the second fin 401b.
The source electrode 407, drain electrode 409 and grid structure 405, the first fin 401a are (as fin formula field effect transistor
Channel region) collectively form fin formula field effect transistor.The source electrode 407 and drain electrode 409 are formed in same processing step, respectively
In the first fin 401a of grid structure both sides.The source electrode 412 and the doping type of drain electrode 413 are the second doping class
Type, it is opposite with the first fin 401a doping type.
The doped region 411 is located in second area II, by being formed at the top of the second fin 401b after adulterating.Due to second
Fin 401b is smaller perpendicular to the size of the sense of current, is subsequently easily blown, and can be used as electric fuse.The 3rd in the present invention is real
Apply in example, it is contemplated that after the doping type of doping second at the top of the second fin 401b, the fin of doped region 414 and second of formation
PN junction is may make up between 401b bottom, the PN junction can play a part of isolation to electric fuse.Therefore, embodiments of the invention
In, the doped region 414 is formed with the source electrode 412 and drain electrode 413 in same step, i.e., to stress laying 410, silicon
While layer 411 carries out the doping of the second doping type, the doping of the second doping type, effectively section are also carried out to the second fin 401b
Processing step is saved.
Due to being to colonize in first area I ' to form fin field effect crystal the step of second area II ' forms P-N junction
Among the step of pipe, almost nil cost；Also, the isolation to electric fuse is reached by doping process can, its method
Simply；In addition, the method isolated using the P-N junction on the second fin 401b in second area II ' to electric fuse
The precedent for directly forming electric fuse is on the active area started.Reason is as follows：Electric fuse of the prior art is can not direct shape
Into on the active area, active area belongs to the very big semiconductor structure of the semiconductor structure of large area, especially width, even in
There is larger immediate current on electric fuse, substantial amounts of heat caused by the electric current can also shed from the active area of large area,
Therefore, in the prior art, it is necessary to which insulating barrier, i.e. generally use silicon-on-insulator substrate (SOI) conduct is provided below in electric fuse
Semiconductor substrate 400, its is with high costs, and the P-N junction can below the electric fuse of the present invention is realized and formed on the active area
The technique of electric fuse.
Figure 22 is refer to, after forming source electrode 412, drain electrode 413 and doped region 414, is formed and covers the silicon layer 411 and doping
The metal silicide layer 415 on the surface of area 414.
Wherein, the metal silicide layer 415 on the surface of silicon layer 411 can effectively reduce silicon layer 411 and be subsequently formed
Contact resistance between conductive plunger；The metal silicide layer 415 on the surface of doped region 414 is used for common with doped region 414
Electric fuse 416 is formed, and is used for the contact resistance between doped regions 414 and the conductive plunger being subsequently formed.
Specifically, when having larger immediate current between the anode and negative electrode that subsequent technique is formed, fuse 416 is by low-resistance
The situation that state changes into high-impedance state has two kinds：
(1) resistivity of metal silicide layer 415 is less than doped region 414, therefore, larger moment between anode and negative electrode
Electric current preferentially can flow through from metal silicide layer 415, so that electromigration occurs for the inside of metal silicide layer 415
(electromigration, EM) phenomenon, that is to say, that most of metal ion in metal silicide layer 415 all migrate to
Negative electrode or anode, so that the inside of metal silicide layer 415 produces cavity so that the resistance of metal silicide layer 415
Increase considerably, and then the resistance of fuse 416 is increased considerably, high-impedance state is changed into by low resistance state；(2) anode and negative electrode
Between larger immediate current can produce substantial amounts of heat energy, the substantial amounts of heat energy can be by metal silicide layer 415 and doped region
414 are fused together, so that the resistance of fuse 416 increases considerably, high-impedance state is changed into by low resistance state.
Certainly, in other embodiments, metallic silicon can not also be formed on the doped region 414 at the top of the second fin 401b
Compound layer 215, it can also implement the present invention.Electric fuse now is only doped region 414, when the anode and negative electrode that subsequent technique is formed
Between when there is larger immediate current, the impurity in doped region 414 can also migrate, and migrate to male or female,
So as to which the resistance of doped region 414 can be caused to increase considerably, high-impedance state is changed into by low resistance state.
It should be noted that the step of forming metal silicide layer 415 is optional step.When electric fuse is only to adulterate
During area 414, when there is larger immediate current between the anode and negative electrode that subsequent technique is formed, the doping in doped region 414
Impurity can also migrate, and migrate to male or female, so as to which the resistance of doped region 414 can be caused to increase considerably, by low-resistance
State changes into high-impedance state.
It should be noted that in other embodiments of the invention, when the silicon layer 411 also covers the second fin 401b's
During top, the part silicon layer 411 at the top of the second fin 401b can also be with doped region 414 and metal silicide layer 415 1
Rise and form electric fuse 416.When including part silicon layer 411 in the electric fuse, have the advantage that：Second area can be prevented
The ion diffusion of the second doping type at the top of II ' the second fin 401b so that the Second Type at the top of the second fin 401b
The distribution of doping is narrow, so as to reduce the resistivity of the doped region 414 at the top of the second fin 401b, reduces electric fuse 416
Fuse operation window so that the condition that electric fuse 416 fuses is easier to control, and then improves the utility ratio of electric fuse 416.When
When electric fuse 416 at the top of second fin 401b has a plurality of, above-mentioned benefit can be more obvious.
Figure 23 is refer to, is formed and covers the fin formula field effect transistor, doped region 411 and metal silicide layer 415
First interlayer dielectric layer 417.
First interlayer dielectric layer 417 is used to isolate fin formula field effect transistor and electric fuse, and first interlayer is situated between
Matter layer 417 covers the grid structure 405, source electrode 412 and drain electrode 413, electric fuse 416 and shallow ridges of the fin formula field effect transistor
Recess isolating structure 403.The formation process of first interlayer dielectric layer 417 is chemical vapor deposition method, and its material is oxidation
Silicon, silicon nitride or silicon oxynitride.In embodiments of the invention, the material of first interlayer dielectric layer 417 is silica, its table
Face flushes with the surface of grid structure 405.
It should be noted that when electric fuse 416 has larger immediate current, substantial amounts of heat, first layer can be produced
Between dielectric layer 417 cover electric fuse 416 can cause the heat can not Quick diffusing go out, be more beneficial for the fusing of electric fuse.
Figure 24 is refer to, removes the pseudo- gate electrode layer 407 (as shown in figure 23), formation exposes the gate dielectric layer
Opening 418, for filling the gate electrode layer of metal material.
Figure 25 is refer to, metal material is filled into the opening 418, gate electrode layer 419 is formed, as fin field effect
The grid of transistor.
It is well known to those skilled in the art due to removing pseudo- gate electrode layer 407 and forming the technique of gate electrode layer 419,
This is repeated no more.
Figure 26 is refer to, after forming gate electrode layer 419, is formed and covers the second of the surface of the first interlayer dielectric layer 417
Interlayer dielectric layer 420；Patterned mask layer (not shown) is formed on the surface of the second interlayer dielectric layer 420, with the figure
The mask layer of change is mask, etches the interlayer dielectric layer 417 of the second interlayer dielectric layer 420 and first, forms several openings,
In first area I ', the metal silicide layer 415 on the source electrode 412 and drain electrode 413 is exposed in the bottom of the opening；Second
The metal silicide layer 415 at the both ends of electric fuse 416 is exposed in region II ', the bottom of the opening；Then, after forming opening,
The opening is filled using conductive material, forms conductive plunger 421.
The source electrode 412 with fin formula field effect transistor and drain electrode 413 and the electric smelting respectively of the multiple conductive plunger 421
The both ends electrical connection of silk 416, for subsequently applying electric signal.In embodiments of the invention, due to being also formed with silicon layer 411 and gold
Belong to silicide layer 415, the opening exposes source electrode 412 and the metal silicide layer 415 of the top of drain electrode 413, and doped region
Metal silicide layer 415 above 411 both ends.The material of the conductive plunger 421 is copper or tungsten.
, can be with it should be noted that in other embodiments：After the first interlayer dielectric layer 417 is formed, pseudo- grid are removed
Electrode layer 407, metal gate electrode layer 419 is formed on the surface of gate dielectric layer 406, then, formed and cover first inter-level dielectric
Second interlayer dielectric layer 420 on 417 surface of layer, and etch the shape of 417 and second interlayer dielectric layer of the first interlayer dielectric layer 420
Into multiple openings, source electrode 412 and the silicon layer 411 on 413 surfaces that drain are exposed in the bottom of the opening, then in the silicon of open bottom
Metal silicide layer 415 is formed on layer 411, after forming metal silicide layer 415, filling opening forms conductive plunger 421.Need
Illustrating, the embodiment can not form metal silicide layer 415 on doped region 414, or, have when on doped region 414
During silicon layer 411, metal silicide layer 415 can not be also formed on silicon layer 411.Therefore, the doped region 415 is electric fuse.
After the completion of above-mentioned steps, the semiconductor devices of third embodiment of the invention completes.One kind is provided in fin
The method that electric fuse structure is formed in portion, to realize the diversity for forming electric fuse structure method on the semiconductor device, and
The step that is integrally formed of electric fuse structure in this method is that the fin field effect colonized in same Semiconductor substrate is brilliant
Among the forming step of body pipe, therefore, method of the invention is simple and process costs are almost nil.
Accordingly, please continue to refer to Figure 23, inventor also provides a kind of semiconductor devices, including：
Semiconductor substrate 400, the Semiconductor substrate 400 have raised the first fin 401a and the second fin 401b,
The first fin 401a and the second fin 401b has the first doping type, has fleet plough groove isolation structure between adjacent fin
403；
Electric fuse with the second doping type, the electric fuse 416 to the top of the second fin 401b from adulterating
Doped region 414 afterwards is formed；
Fin formula field effect transistor with the first fin 401a, the fin field effect pipe include：Across described first
Fin 401a top and the gate dielectric layer 406 of side wall and the gate electrode layer 419 for covering the surface of gate dielectric layer 406；And
Source electrode 412 and drain electrode 413 in the first fin 401a of the gate dielectric layer 406 and the both sides of gate electrode layer 419, the source
Pole 412 and drain electrode 413 have the second doping type；
Cover the interlayer dielectric layer of the fin formula field effect transistor and electric fuse 416；
Through multiple conductive plungers 421 of the interlayer dielectric layer, the conductive plunger 421 is brilliant with fin field effect respectively
The source electrode 412 of body pipe and the electrical connection of the both ends of drain electrode 413 and electric fuse 416.
In the third embodiment of the present invention, the forming method of above-mentioned semiconductor device, in addition to：Cover the gate dielectric layer
406 and the both sides of gate electrode layer 419 the first fin 401a top surfaces and the second fin 401b top silicon layer 411；Covering
The metal silicide layer 415 of doped region 414 at the top of the fin 401b of silicon layer 411 and second, the conductive plunger 421 with
The metal silicide layer 415 electrically connects.In addition to doped region 414 of the electric fuse 416 at the top of including the second fin 401b, also
Including the metal silicide layer 415 above it, the operation window that the electric fuse 416 fuses is small, and the condition that it fuses is more easily-controllable
System, utility ratio improve.
It should be noted that in other embodiments of the invention, the electric fuse pushes up including at least the second fin 401b
The doped region 414 in portion, and the silicon layer 411 and metal silicide layer 415 are option, more associated descriptions refer to institute above
State, will not be repeated here.
In embodiments of the invention, first doping type is n-type doping, and second doping type adulterates for p-type.
In second area II ' the fin 401b of doped region 414 and second bottom form P-N junction, the P-N junction to electric fuse 416 have every
From effect, its cost is low, and the can effectively replace method that surface of silicon forms electric fuse on insulator, having started directly is having
The precedent of electric fuse is formed in source region.
The structure of more multiple semiconductor devices, it refer to above, will not be repeated here.
Because electric fuse structure and fin formula field effect transistor are located at in semi-conductive substrate, realize in semiconductor device
The diversity of electric fuse structure method is formed on part.Also, the doped region and the doping type of Semiconductor substrate are on the contrary, can structure
Into P-N junction, the P-N junction has buffer action to electric fuse, and its cost is low, can effectively replace surface of silicon shape on insulator
Into the method for electric fuse, the precedent for directly forming electric fuse on the active area has been started.
Fourth embodiment
Different from 3rd embodiment in the present invention, the electric fuse structure in the fourth embodiment of the present invention is situated between in high k grid
What matter layer was formed during rear formation process, it refer to Figure 27 and Figure 28 with the difference of 3rd embodiment.It is specific as follows：
Figure 27 is refer to, grid structure 505 is formed on the first area Ι " of Semiconductor substrate 500 fin 504, it is described
Grid structure 505 includes pseudo- gate dielectric layer 506 and the pseudo- gate electrode layer 507 formed on pseudo- gate dielectric layer 506.Wherein, it is pseudo-
The material of gate dielectric layer 506 is silica, the pseudo- dummy poly of gate electrode layer 507.
Wherein, the second area II " is used to be subsequently formed electric fuse structure.The Semiconductor substrate 500 includes doping
Area 500a and well region 500b；The surface of Semiconductor substrate 500 between the first fin 501a and the second fin 501b has shallow
Groove isolation construction 503.The more description as described in features described above, refer to the third embodiment of the present invention, will not be repeated here.
It should be noted that in the fourth embodiment of the present invention, subsequently need to remove the pseudo- gate dielectric layer 506 and pseudo- grid
Electrode layer 507, gate openings are formed, to fill high-K gate dielectric layer and gate electrode layer.
Figure 28 is refer to, the high-k gate dielectric layer 519 of formation covers the bottom and side wall (i.e. side of gate openings (not indicating)
Wall 508).
Due to using high-k gate dielectric layer in fourth embodiment in rear formation process, it is contemplated that if forming metal silication
Form high-k gate dielectric layer 519 after nitride layer 515, the annealing process in the formation process of high-k gate dielectric layer 519 can will before formed
The resistance of metal silicide layer 515 increase considerably, so as to destroy the performance of metal silicide layer 515, therefore, it is necessary in shape
The surface shape of silicon layer 511 into high-K gate dielectric layer 519 and gate electrode layer 520 and then in first area Ι " He second area II "
Into metal silicide layer 515.
In the fourth embodiment of the present invention, it is follow-up to form high-K gate dielectric layer 519 and gate electrode layer 520 formed
First interlayer dielectric layer 517 and the second interlayer dielectric layer 518 can be in advance by first area Ι " and second area II " silicon layer 511
Covering.In subsequent technique, expose opening for silicon layer 511 when being formed in the first interlayer dielectric layer 517 and the second interlayer dielectric layer 518
During mouth, metal silicide layer 515 could be formed in the opening, then forms conductive plunger 521 with conductive material filling opening.
Therefore, in the fourth embodiment of the present invention, the metal silicide layer 515 can not cover whole doped region 516, or, when
When having silicon layer 511 on doped region 516, the metal silicide layer 515 can not also cover second area II " whole silicon layer
511 surfaces.
In the fourth embodiment of the present invention, other related forming step refer to the third embodiment of the present invention, herein not
Repeat again.
It should be noted that the formation process of the fuse-wires structure of the present invention is applicable not only to rear grid formation process, but also
Suitable for preceding grid technique.
5th embodiment
Different from the foregoing 3rd, fourth embodiment, the electric fuse structure of the embodiment of the present invention is formed by fin, but can not be posted
It is born among the step of forming fin formula field effect transistor, can be formed on fin individually on a semiconductor substrate, it is formed
Method is simple.
It refer to Figure 29, there is provided Semiconductor substrate 600, the Semiconductor substrate 600 has raised fin 601, described
Fin 601 has the first doping type；Ion doping is carried out to the top of the fin 601, formation has the second doping type
Electric fuse, second doping type is opposite with first doping type；Formed and cover the electric fuse surface and partly lead
The interlayer dielectric layer 617 of body substrate 600；The multiple conductive plungers 621 formed in the interlayer dielectric layer 617 are described more
Individual conductive plunger 621 electrically connects with the both ends (i.e. negative electrode and anode) of electric fuse respectively.
Wherein, ion doping is carried out to the top of the fin 501, forms doped region 516, the conduct of doped region 616
It is subsequently formed the important component of electric fuse.Doped region 616 forms P-N junction with fin 601, and the P-N junction has to electric fuse
Buffer action.In the fifth embodiment of the present invention, the Semiconductor substrate 600 includes well region 600a and is formed at the well region
The doped region 600b on 600a surfaces, the doped region 600b has opposite doping type with well region 600a, to block bottom to do
Disturb.Formed after the doped region 600b as described in etched portions of fin 601, therefore, the doped region 600b has the first doping
Type, well region 600a have the second doping type.In the shape of Semiconductor substrate 600 including well region 600a and doped region 600b
Into the method for electric fuse, the can effectively replace method that surface of silicon forms electric fuse on insulator, having started directly is having
The precedent of electric fuse is formed in source region.
It should be noted that first doping type can be N-type or p-type, second doping type can also be N
Type or p-type, as long as ensureing that the first doping type and the second doping type are opposite.
The forming method of the conductive plunger 621 includes：Patterned cover is formed on the surface of the interlayer dielectric layer 517
Film layer (not shown)；Using the patterned mask layer as mask, etch the interlayer dielectric layer 617 and formed to be open and (do not scheme
Show), the electric fuse is exposed in the bottom of the opening；Conductive material is filled into the opening, forms conductive plunger 621.
It should be noted that in the fifth embodiment of the present invention, the forming method of the electric fuse, in addition to：Formation is led
Before electric plug 621, the metal silicide layer 615 of the negative electrode and anode surface positioned at the electric fuse is formed, to reduce conductive insert
Contact resistance at the negative electrode and anodic interface of plug 621 and the electric fuse.
It should be noted that in other embodiments of the invention, the forming method of the electric fuse, it can also include：
Before carrying out ion doping formation doped region 616 to the top of the fin 601, the silicon at the top for covering the fin 501 is formed
Layer, the metal silicide layer 615 are located at the silicon surface, can be as a part for electric fuse.
It should be noted that in embodiments of the invention, fleet plough groove isolation structure 503 is also formed with, it is adjacent for isolating
Fin 501.
After the completion of above-mentioned steps, the electric fuse structure of fifth embodiment of the invention completes.The electric fuse structure
By being formed after being adulterated at the top of fin, its structure is novel.Also, because electric fuse and the doping type of Semiconductor substrate are on the contrary, shape
Into P-N junction, the P-N junction has buffer action to electric fuse, and its cost is low, can effectively replace surface of silicon shape on insulator
Into the method for electric fuse, the precedent for directly forming electric fuse on the active area has been started.
Accordingly, a kind of electric fuse structure is additionally provided, including：
Semiconductor substrate 600, the Semiconductor substrate 600 have raised fin 601, and the fin 601 has first
Doping type；
Electric fuse with the second doping type, the electric fuse is from forming to being adulterated positioned at the top of the fin, institute
It is opposite with first doping type to state the second doping type；
Cover the interlayer dielectric layer 517 of the electric fuse surface and Semiconductor substrate 500；
Multiple conductive plungers 621 in the interlayer dielectric layer 517, the multiple conductive plunger respectively with electric fuse
Both ends electrical connection.
Wherein, the Semiconductor substrate 600 includes well region 600a and is formed at the doped region on the well region 600a surfaces
600b, the doped region 600b has opposite doping type with well region 600a, to block bottom to disturb.
Adulterate to form doped region 616 to positioned at the top of the fin 601, the doped region 616 has the second doping class
Type.In embodiments of the invention, first doping type is n-type doping, and second doping type adulterates for p-type.It is described
Doped region 511 forms P-N junction with Semiconductor substrate 500, and the P-N junction has buffer action to electric fuse, and its cost is low.
It should be noted that in embodiments of the invention, in addition to：Between adjacent fin 601 and positioned at described half
The fleet plough groove isolation structure 603 on the surface of conductor substrate 600, for isolating adjacent fin 501.
, can be with it should be noted that in other embodiments of the invention：First doping type is n-type doping,
Second doping type adulterates for p-type, will not be repeated here.
The electric fuse comprises at least the doped region 611.In embodiments of the invention, the electric fuse, which removes, includes doping
Outside area 611, in addition to：Cover the metal silicide layer 615 of the silicon surface.The metal silicide layer 615 helps to drop
Contact resistance between low conductive plunger 621 and Semiconductor substrate 600, further improve the performance of electric fuse.
It should be noted that in other embodiments of the invention, the electric fuse also includes：Cover the doped region
616 silicon layer, the metal silicide layer 615 are located at the silicon surface.Due to the presence of silicon layer so that doped region 616
Narrow distribution, its resistivity reduces, therefore the fusing operation window of electric fuse is smaller, and the fusing condition of electric fuse is more easy to control,
The utility ratio of electric fuse is high.
The conductive plunger 621 is used to subsequently apply electric signal.The material of the conductive plunger 621 is tungsten or copper.This hair
In bright embodiment, the conductive plunger 621 is located at the surface of metal silicide layer 615, is electrically connected with the conductive plunger 621
The both ends of the electric fuse connect are respectively the negative electrode and anode of electric fuse.
Formed after being adulterated due to the electric fuse by fin, its structure is novel, realizes the diversity of electric fuse structure.And
And due to electric fuse and the doping type of Semiconductor substrate on the contrary, both constitute P-N junction, effectively realize electric fuse every
From its cost is low, has started the precedent for directly forming electric fuse on the active area.
To sum up, the forming method of the electric fuse structure of the embodiment of the present invention, after etching forms nano wire, in the nano wire
Both ends adulterate to form electric fuse structure, such a forming method is simple, and the electric fuse structure of formation is novel, realizes the electricity to be formed
The diversity of fuse-wires structure.
The nano wire that the electric fuse structure of the embodiment of the present invention is adulterated by both ends is formed, and its is simple in construction, the knot of electric fuse
Structure is various.
Further, there is provided a kind of forming method of semiconductor devices, form the first nano wire on a semiconductor substrate
Discrete second nano wire therewith, first nano wire are subsequently formed all-around-gate transistor, and after second nano wire
It is continuous to form electric fuse structure, the diversity of the forming method of semiconductor devices is realized, and electric fuse structure is novel.
Further, the source electrode for forming all-around-gate transistor and the step of drain electrode and the formation electric fuse knot
The step of the step of negative electrode and anode of structure carries out, that is, forms the electric fuse structure simultaneously colonizes in form all-around-gate crystal
Among the step of pipe, during forming the semiconductor devices, extra processing step will not be increased, its production cost is low.
Accordingly, because the electric fuse structure and all-around-gate transistor are located at same semiconductor-on-insulator substrate
In, the structure of the semiconductor devices is novel, and its application is wider.
Embodiments of the invention additionally provide a kind of forming method of electric fuse structure, after forming the fin of projection, in institute
The top doping of fin is stated, electric fuse is formed, realizes the variation of electric fuse structure.Also, Semiconductor substrate and fin top
The doping type in portion is on the contrary, Semiconductor substrate and fin top composition P-N junction, are effectively isolated electric fuse, its cost is low, starts
The precedent of electric fuse is directly formed on the active area.
For the electric fuse structure by being formed after the top of fin is adulterated, its structure is novel, realizes electric fuse structure
Variation.Also, due to the doping type at the top of Semiconductor substrate and fin on the contrary, forming P- at the top of Semiconductor substrate and fin
N is tied, and is effectively isolated electric fuse, its cost is low.
Further, there is provided a kind of forming method of semiconductor devices, form the first fin on the same semiconductor substrate
Portion and the second fin, first fin are used to form fin formula field effect transistor, and second fin is then used to form electric smelting
Silk structure, realize the diversity for the semiconductor devices to be formed.Also, the doping class at the top of the Semiconductor substrate and fin
Type is effectively isolated electric fuse, its cost is low on the contrary, Semiconductor substrate and fin top composition P-N junction.
Further, the technique for forming source electrode and drain electrode and the top doping to second fin is same
Among the step of being formed in processing step, that is, forming electric fuse structure parasitizes the step of forming fin formula field effect transistor, no
Extra processing step can be increased, forming method is simple, and production cost is low.
Accordingly, there is provided semiconductor devices in, including the electric fuse structure positioned at same semi-conductive substrate and fin field
Effect transistor, the structure diversification of the semiconductor devices, application are wider.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (15)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Semiconductor-on-insulator substrate is provided, the semiconductor-on-insulator substrate includes backing bottom, covers backing basal surface Buried oxide layer and the top-layer semiconductor for covering buried oxide layer surface；Etch the top-layer semiconductor and form the first nano wire and the second discrete therewith nano wire；The buried oxide layer of segment thickness is at least removed, makes the centre of the first nano wire and the second nano wire hanging and both ends With support；Centre to be formed forms vacantly and after the first nano wire of the both ends with support and covers first nanowire surface Grid structure；After forming the grid structure, source electrode and the drain electrode to form all-around-gate transistor are adulterated at the both ends of the first nano wire；Adulterated at the both ends of second nano wire, form the negative electrode and anode of electric fuse structure, and positioned at the negative electrode and Fuse area between anode.
- 2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the formation all-around-gate transistor Source electrode and the step of drain electrode and it is described form electric fuse structure negative electrode and anode the step of carry out simultaneously.
- 3. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that also include：Before forming grid structure, To middle hanging and both ends have support the first nano wire and the second nano wire among adulterate, formed among there is doping The first nano wire and middle second nano wire with doping.
- 4. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that to middle hanging and both ends have Support the first nano wire and the second nano wire among doping ionic type with the first nano wire both ends adulterate from Subtype and second nano wire both ends adulterate ionic type it is identical.
- 5. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that also include：Have among being formed and mix After the first miscellaneous nano wire and middle the second nano wire with doping, to the surface of first nano wire and the second nano wire Repaired with two end faces.
- 6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that described to repair the technique that uses to move back Ignition technique or thermal oxidation technology.
- 7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that also include：It is described complete to form covering Surround the interlayer dielectric layer of gate transistor and electric fuse structure；Multiple conductive plungers are formed in the interlayer dielectric layer, it is described Multiple conductive plungers are electric with the negative electrode and anode of the source electrode of the all-around-gate transistor and drain electrode and electric fuse structure respectively Connection.
- 8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the etching top layer semiconductors The technique of layer is anisotropic dry etch process or anisotropic wet-etching technology.
- 9. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that what the wet-etching technology used Chemical reagent is potassium hydroxide, ammoniacal liquor or tetramethyl aqua ammonia.
- 10. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that described to remove the hidden of segment thickness The technique for burying oxide skin(coating) is isotropic wet-etching technology, and etching liquid is acid solution.
- 11. the forming method of semiconductor devices as claimed in claim 10, it is characterised in that the acid solution is hydrogen fluorine Acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid.
- A kind of 12. semiconductor devices, it is characterised in that including：Semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate include backing bottom, cover the buried of backing basal surface Oxide skin(coating) and the top-layer semiconductor for covering buried oxide layer surface；All-around-gate transistor and the electric fuse structure isolated therewith positioned at the semiconductor-on-insulator substrate surface；Wherein, the all-around-gate transistor includes the first nano wire as channel region, the grid of covering first nano wire Pole structure and the source electrode positioned at the grid structure both sides and drain electrode, first nano wire are partly led by etching the top layer Formed after body layer；The electric fuse structure is included as the fuse area among the second nano wire, and positioned at second nano wire two The negative electrode and anode at end.
- 13. semiconductor devices as claimed in claim 12, it is characterised in that the source electrode of the all-around-gate transistor and leakage The anode of pole and electric fuse structure is identical with the ionic type adulterated in negative electrode.
- 14. semiconductor devices as claimed in claim 12, it is characterised in that the channel region and electricity of the all-around-gate transistor Have in the fuse area of fuse-wires structure and adulterate, the Doped ions type in the channel region and fuse area and all-around-gate transistor Source electrode and the anode of drain electrode and electric fuse structure it is identical with the ionic type that is adulterated in negative electrode.
- 15. semiconductor devices as claimed in claim 12, it is characterised in that the material of the electric fuse structure is WSi2、 CoSi2Or NiPtSi.
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| CN201710516564.4A CN107359123B (en) | 2013-05-22 | 2013-05-22 | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof |
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| CN201310192826.8A CN104183542B (en) | 2013-05-22 | 2013-05-22 | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof |
| CN201710516564.4A CN107359123B (en) | 2013-05-22 | 2013-05-22 | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof |
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| CN201310192826.8A Active CN104183542B (en) | 2013-05-22 | 2013-05-22 | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770804B (en) * | 2021-02-04 | 2022-07-11 | 華邦電子股份有限公司 | Memory device and method for manufacturing the same |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298529B (en) * | 2015-06-01 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
| US9455222B1 (en) * | 2015-12-18 | 2016-09-27 | Texas Instruments Incorporated | IC having failsafe fuse on field dielectric |
| US10038095B2 (en) * | 2016-01-28 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | V-shape recess profile for embedded source/drain epitaxy |
| CN107293487B (en) * | 2016-04-05 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN107481993B (en) * | 2016-06-08 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor structure |
| CN107785420B (en) * | 2016-08-29 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
| CN108122892B (en) * | 2016-11-30 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and forming method and working method thereof |
| CN109390275B (en) * | 2016-12-02 | 2024-01-09 | 乐清市风杰电子科技有限公司 | Manufacturing method of polycrystalline silicon fuse structure |
| US10056329B1 (en) | 2017-05-02 | 2018-08-21 | International Business Machines Corporation | Programmable buried antifuse |
| CN107256855B (en) * | 2017-07-11 | 2019-07-12 | 上海华力微电子有限公司 | A kind of fuse and its manufacturing method |
| EP3648160B1 (en) | 2018-08-24 | 2021-05-26 | Shenzhen Weitongbo Technology Co., Ltd. | Electrically programmable fuse, manufacturing method therefor, and storage unit |
| JP7425566B2 (en) | 2019-09-09 | 2024-01-31 | 日清紡マイクロデバイス株式会社 | Semiconductor device and its trimming method |
| CN115394749A (en) * | 2021-05-20 | 2022-11-25 | 长鑫存储技术有限公司 | Fuse structure and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200532892A (en) * | 2004-03-26 | 2005-10-01 | Taiwan Semiconductor Mfg | Electrical fuse for semiconductor-on-insulator devices |
| TW200903799A (en) * | 2007-03-07 | 2009-01-16 | Ibm | Electrical antifuse, method of manufacture and method of programming |
| CN101771021A (en) * | 2008-12-29 | 2010-07-07 | 联华电子股份有限公司 | Electric fuse structure and manufacture method thereof |
| US20100244144A1 (en) * | 2009-03-31 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
| US20110042779A1 (en) * | 2009-07-24 | 2011-02-24 | International Business Machines Corporation | Fuse link structures using film stress for programming and methods of manufacture |
| US8026573B2 (en) * | 2008-12-15 | 2011-09-27 | United Microelectronics Corp. | Electrical fuse structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7569503B2 (en) * | 2004-11-24 | 2009-08-04 | Nanosys, Inc. | Contact doping and annealing systems and processes for nanowire thin films |
| US20070176255A1 (en) * | 2006-01-31 | 2007-08-02 | Franz Kreupl | Integrated circuit arrangement |
| US7786024B2 (en) * | 2006-11-29 | 2010-08-31 | Nanosys, Inc. | Selective processing of semiconductor nanowires by polarized visible radiation |
| CN101170099B (en) * | 2007-11-30 | 2012-03-28 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN102082122B (en) * | 2009-11-30 | 2013-12-11 | 联华电子股份有限公司 | Manufacturing method of electric fuse, resistor and transistor |
| US20130109167A1 (en) * | 2011-11-01 | 2013-05-02 | International Business Machines Corporation | Nanowire efuses |
-
2013
- 2013-05-22 CN CN201610908720.7A patent/CN106449516A/en active Pending
- 2013-05-22 CN CN201310192826.8A patent/CN104183542B/en active Active
- 2013-05-22 CN CN201710516564.4A patent/CN107359123B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200532892A (en) * | 2004-03-26 | 2005-10-01 | Taiwan Semiconductor Mfg | Electrical fuse for semiconductor-on-insulator devices |
| TW200903799A (en) * | 2007-03-07 | 2009-01-16 | Ibm | Electrical antifuse, method of manufacture and method of programming |
| US8026573B2 (en) * | 2008-12-15 | 2011-09-27 | United Microelectronics Corp. | Electrical fuse structure |
| CN101771021A (en) * | 2008-12-29 | 2010-07-07 | 联华电子股份有限公司 | Electric fuse structure and manufacture method thereof |
| US20100244144A1 (en) * | 2009-03-31 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
| US20110042779A1 (en) * | 2009-07-24 | 2011-02-24 | International Business Machines Corporation | Fuse link structures using film stress for programming and methods of manufacture |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770804B (en) * | 2021-02-04 | 2022-07-11 | 華邦電子股份有限公司 | Memory device and method for manufacturing the same |
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| CN107359123B (en) | 2019-11-01 |
| CN106449516A (en) | 2017-02-22 |
| CN104183542B (en) | 2017-11-03 |
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