CN107331660A - Electro-static Driven Comb clamp circuit - Google Patents
Electro-static Driven Comb clamp circuit Download PDFInfo
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- CN107331660A CN107331660A CN201710455287.0A CN201710455287A CN107331660A CN 107331660 A CN107331660 A CN 107331660A CN 201710455287 A CN201710455287 A CN 201710455287A CN 107331660 A CN107331660 A CN 107331660A
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- driven comb
- static driven
- transistor
- switch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
The invention discloses a kind of Electro-static Driven Comb clamp circuit, including：Esd detection circuit, static release circuit and charge pump；Static release circuit includes the first Electro-static Driven Comb transistor being connected between I/O port and ground；The grid connection of the output end of charge pump and the first Electro-static Driven Comb transistor；The output end of Esd detection circuit connects the input of charge pump；The output end of Esd detection circuit is also connected with the control end of first switch, and first switch is connected between the grid of I/O port and the first Electro-static Driven Comb transistor；In the state of the appearance of Electro-static Driven Comb event, charge pump is stopped, and first switch is opened, and the first Electro-static Driven Comb transistor turns realize Electro-static Driven Comb；Under chip normal operating conditions, the grid that charge pump and output voltage are connected to the first Electro-static Driven Comb transistor makes the first Electro-static Driven Comb transistor be in deep closed mode, is leaked electricity so as to reduce by the first Electro-static Driven Comb transistor in OFF state.The present invention can reduce power consumption.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of Electro-static Driven Comb (ESD) clamp circuit.
Background technology
As shown in figure 1, being the circuit diagram of existing Electro-static Driven Comb clamp circuit, existing Electro-static Driven Comb clamp circuit includes：It is quiet
Electric circuit for detecting 101 and static release circuit 102.
The Esd detection circuit 101 is arranged between the I/O port of chip and ground, for detecting the quiet of I/O port appearance
Electricity；The voltage of I/O port is represented with VDDIO in Fig. 1.
The Esd detection circuit 101 includes the resistance R101 and electric capacity C101 being connected between I/O port and ground, resistance
R101 and electric capacity C101 junction are formed after detecting voltage V101, detecting voltage V101 by forming defeated after three phase inverters
Go out signal i.e. Electro-static Driven Comb signal ESD Signal.Three phase inverters are all CMOS inverter, first CMOS inverter in Fig. 1
It is made up of NMOS tube MN101 and PMOS MP101, second CMOS inverter is by NMOS tube MN102 and PMOS MP102 groups
Into the 3rd CMOS inverter is made up of NMOS tube MN103 and PMOS MP103.
Static release circuit 102 is made up of Electro-static Driven Comb transistor, and Electro-static Driven Comb transistor is NMOS tube MN104 in Fig. 1,
NMOS tube MN104 is connected between the I/O port and ground, i.e. NMOS tube MN104 source ground, drain electrode connects the I/O port.
NMOS tube MN104 is turned on when Electro-static Driven Comb event occurs and is used for release electrostatic, is closed in chip normal work
Close, the need for meeting progress Electro-static Driven Comb, NMOS tube MN104 size is larger, each relative in Fig. 13 each phase inverters
Transistor, NMOS tube MN104 is that large-sized NMOS tube is BigNMOS pipes.
In Fig. 1, BigNMOS pipes be NMOS tube MN104 be Electro-static Driven Comb main devices.When Esd detection circuit 101 is detectd
When measuring Electro-static Driven Comb pulse, the Electro-static Driven Comb signal ESD Signal on BigNMOS grids are in one state, BigNMOS quilts
Triggering is opened, and discharges ESD electric currents.When circuit is in normal operating conditions, the Electro-static Driven Comb signal on BigNMOS grids
In " 0 " state, BigNMOS is closed, circuit consumption off-state current (Ioff), because NMOS tube MN104 manages for BigNMOS,
The value of off-state current also can be larger.And many products require more and more higher to the Electro-static Driven Comb of whole chip now, then
The Electro-static Driven Comb clamp circuit placed between power supply and ground is more and more, and which results in clamped among whole chip by Electro-static Driven Comb
The power consumption more and more higher of position circuit consumption.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of Electro-static Driven Comb clamp circuit, can reduce power consumption.
In order to solve the above technical problems, the Electro-static Driven Comb clamp circuit that the present invention is provided includes：Esd detection circuit, electrostatic
Release circuit and charge pump.
The Esd detection circuit is arranged between the I/O port of chip and ground, the electrostatic for detecting I O port.
The static release circuit includes the first Electro-static Driven Comb transistor, and the first Electro-static Driven Comb transistor is connected to institute
State between I/O port and ground.
The grid connection of the output end of the charge pump and the first Electro-static Driven Comb transistor；The Esd detection circuit
Output end connect the input of the charge pump.
The output end of the Esd detection circuit is also connected with the control end of first switch, and the first switch is connected to described
Between the grid of I/O port and the first Electro-static Driven Comb transistor.
In the state of the appearance of Electro-static Driven Comb event, the Esd detection circuit detects the quiet of the I/O port appearance
Electricity, the signal of the output end of the Esd detection circuit makes the charge pump be stopped and open the first switch,
The grid connection I/O port of the first Electro-static Driven Comb transistor is simultaneously turned under the control of I/O port voltage, so that by the IO
The Electro-static Driven Comb of port to ground.
Under chip normal operating conditions, the electrostatic that the I/O port does not occur, the output end of the Esd detection circuit
Signal make the charge pump and close the first switch, the grid of the first Electro-static Driven Comb transistor disconnects
The output voltage of connection and the charge pump with the I/O port is connected to the grid of the first Electro-static Driven Comb transistor, institute
Stating the output voltage of charge pump makes the first Electro-static Driven Comb transistor be in deep closed mode, so as to reduce first electrostatic
Electric leakage under discharging transistor in off position.
Further improve is that the first Electro-static Driven Comb transistor is a NMOS tube, the first Electro-static Driven Comb crystal
The size of pipe meets the requirement that Electro-static Driven Comb is carried out in the state of the appearance of Electro-static Driven Comb event.
The charge pump is negative pressure charge pump, and the output voltage of the charge pump is negative pressure.
Further improve is that the static release circuit also includes the second Electro-static Driven Comb transistor.
The second Electro-static Driven Comb transistor is also a NMOS tube, and the size of the second Electro-static Driven Comb transistor is met
Electro-static Driven Comb event carries out the requirement of Electro-static Driven Comb in the state of occurring.
The source ground of the first Electro-static Driven Comb transistor, the drain electrode connection of the first Electro-static Driven Comb transistor is described
The source electrode of second Electro-static Driven Comb transistor.
The drain electrode of the second Electro-static Driven Comb transistor is connected to the I/O port, second electrostatic by second switch
The drain electrode of release transistor is connected to the internal source voltage of the chip by the 3rd switch.
In the state of the appearance of Electro-static Driven Comb event, the second switch conducting and the 3rd switch are closed so that
The electrostatic of the I/O port is discharged by the second Electro-static Driven Comb transistor of series connection and the first Electro-static Driven Comb transistor
To ground.
Under chip normal operating conditions, the second switch is closed and the 3rd switch conduction, and described second is quiet
The internal source voltage of the chip is connected to the drain electrode of the first Electro-static Driven Comb transistor by electricity release transistor, using described
The characteristics of internal source voltage voltage of chip is less than the I/O port voltage reduces the drain electrode of the first Electro-static Driven Comb transistor
With the voltage difference of grid so that reduce the first Electro-static Driven Comb transistor grid induced drain electric leakage (GIDL).
Further improve is that the Esd detection circuit includes first resistor, the first electric capacity, the first phase inverter and second
Phase inverter.
The first end of the first resistor connects the I/O port, the second end connection first electricity of the first resistor
The first end of appearance, the second end ground connection of first electric capacity.
Second end of the first resistor connects the input of first phase inverter, the output end of first phase inverter
Connect the input of second phase inverter, the output end of second phase inverter as the Esd detection circuit output
End.
Further improve is that first phase inverter is CMOS inverter, and second phase inverter is CMOS inverter.
Further improve is that the first switch is a PMOS, and the grid of the first switch connects the electrostatic
The output end of circuit for detecting, the source electrode of the first switch connects the I/O port, and the drain electrode connection of the first switch is described
The grid of first Electro-static Driven Comb transistor.
Further improve is that the second switch is a PMOS, and the grid of the second switch connects the electrostatic
The output end of circuit for detecting, the source electrode of the second switch connects the I/O port, and the drain electrode connection of the second switch is described
The grid of second Electro-static Driven Comb transistor.
Further improve is that the 3rd switch is a PMOS, and the grid of the 3rd switch connects the electrostatic
The inversion signal of the signal of the output end of circuit for detecting, the source electrode of the 3rd switch connects the internal source voltage of the chip,
The grid of drain electrode connection the second Electro-static Driven Comb transistor of 3rd switch.
Further improve is that the chip is included on more than one power domain, the I/O port ring of each power domain
Set including multiple chip submodules, in the same power domain Esd detection circuit and a charge pump and
The Esd detection circuit and the charge pump are arranged in the same chip submodule as an integral module,
A static release circuit is all set in each chip submodule of the same power domain, in the same power domain
In, output voltage all overall signals of the signal of the output end of the Esd detection circuit and the charge pump simultaneously give same institute
State the static release circuit of each chip submodule of power domain.
Further improve is that the first Electro-static Driven Comb transistor is a PMOS, the first Electro-static Driven Comb crystal
The size of pipe meets the requirement that Electro-static Driven Comb is carried out in the state of the appearance of Electro-static Driven Comb event；
The charge pump is malleation charge pump, and the output voltage of the charge pump is malleation.
The present invention is supplied to electrostatic under chip operation state by setting charge pump by the output voltage of charge pump
The grid of the first Electro-static Driven Comb transistor for release electrostatic electric current of release circuit is simultaneously realized to the first Electro-static Driven Comb crystal
The depth of pipe is closed, so, can greatly reduce the OFF state electric leakage of the first Electro-static Driven Comb transistor, pincers is discharged so as to minimizing electrostatic
The power consumption of position circuit.In the state of the appearance of Electro-static Driven Comb event, charge pump is closed, so the increase of charge pump can't influence
Protective capability of the Electro-static Driven Comb clamp circuit to the Electro-static Driven Comb of chip.
In addition, the present invention also sets the second Electro-static Driven Comb transistor by the drain side in the first Electro-static Driven Comb transistor,
The second Electro-static Driven Comb transistor can connect the internal source voltage of chip to the first Electro-static Driven Comb crystal under chip operation state
The drain electrode of pipe, so as to the voltage difference for the drain and gate for reducing the first Electro-static Driven Comb transistor, so as to reduce the first electrostatic
The GIDL of transistor is discharged, the power consumption of clamp circuit is discharged so as to further minimizing electrostatic.Occur in Electro-static Driven Comb event
In the state of, I/O port can then be connected to the drain electrode of the first Electro-static Driven Comb transistor by the second Electro-static Driven Comb crystal, and realization passes through
First Electro-static Driven Comb transistor carries out Electro-static Driven Comb to I/O port, so the increase of the second Electro-static Driven Comb transistor can't influence
Protective capability of the Electro-static Driven Comb clamp circuit to the Electro-static Driven Comb of chip.
In addition, the present invention can also be carried out by the power domain of chip in the setting of Electro-static Driven Comb clamp circuit, a power domain
Only need to set an Esd detection circuit and charge pump, and static release circuit then needs each chip set to power domain
It is electric relative to setting is required in each chip submodule due to only needing to set a charge pump in a power domain in submodule
The situation of lotus pump, the present invention can reduce the power consumption that charge pump is brought in itself to greatest extent.
From the foregoing, it will be observed that present invention energy minimizing electrostatic discharges the function of clamp circuit, while not interfering with Electro-static Driven Comb clamp
Protective capability of the circuit to the Electro-static Driven Comb of chip.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the circuit diagram of existing Electro-static Driven Comb clamp circuit；
Fig. 2 is the circuit diagram of Electro-static Driven Comb clamp circuit of the embodiment of the present invention.
Embodiment
As shown in Fig. 2 being the circuit diagram of Electro-static Driven Comb clamp circuit of the embodiment of the present invention, Electro-static Driven Comb of the embodiment of the present invention
Clamp circuit includes：Esd detection circuit, static release circuit 2 and charge pump 3.In Fig. 1, Esd detection circuit and charge pump 3
Marked as an integral module and with dotted line frame 1.
The Esd detection circuit is arranged between the I/O port of chip and ground, the electrostatic for detecting I O port.Fig. 2
The voltage of middle I O port is that I/O port voltage is represented with VDDIO.
The static release circuit 2 includes the first Electro-static Driven Comb transistor MN0, the first Electro-static Driven Comb transistor MN0
It is connected between the I/O port and ground.
The output end of the charge pump 3 and the first Electro-static Driven Comb transistor MN0 grid connection, it is electric described in Fig. 2
The voltage of the output end of lotus pump 3 is output voltage V4.In the embodiment of the present invention, the first Electro-static Driven Comb transistor MN0 is one
NMOS tube, therefore represented with MNO.The size of the first Electro-static Driven Comb transistor MN0 meets the shape occurred in Electro-static Driven Comb event
The requirement of Electro-static Driven Comb is carried out under state.The charge pump 3 is negative pressure charge pump (Negative Charge Pump) 3, the electricity
The output voltage V4 of lotus pump 3 is negative pressure.In other embodiments, also can be：The first Electro-static Driven Comb transistor is a PMOS
Pipe, the size of the first Electro-static Driven Comb transistor is met carries out wanting for Electro-static Driven Comb in the state of the appearance of Electro-static Driven Comb event
Ask；Now, the charge pump 3 is malleation charge pump 3, and the output voltage of the charge pump 3 is malleation, the corresponding reality of this situation
Apply example to can obtain by the conversion of progress PMOS and NMOS tube of the embodiment of the present invention, be not described in detail herein.
The output end of the Esd detection circuit connects the input of the charge pump 3, Esd detection circuit described in Fig. 2
Output end voltage be voltage V3.
The output end of the Esd detection circuit is the control end that voltage V3 is also connected with first switch MP4, and described first opens
MP4 is closed to be connected between the I/O port and the first Electro-static Driven Comb transistor MN0 grid.The first switch MP4 is
One PMOS, therefore represent first switch with MP4 in Fig. 2.The grid of the first switch MP4 connects the Esd detection circuit
Output end, the source electrode of the first switch MP4 connects the I/O port, the drain electrode connection described first of the first switch MP4
Electro-static Driven Comb transistor MN0 grid.
In the state of the appearance of Electro-static Driven Comb event, the Esd detection circuit detects the quiet of the I/O port appearance
Electricity, the signal of the output end of the Esd detection circuit is that voltage V3 makes the charge pump 3 be stopped and by described first
Switch MP4 to open, the grid of the first Electro-static Driven Comb transistor MN0 connects I/O port and in I/O port voltage VDDIO control
System is lower to be turned on, thus by the Electro-static Driven Comb of the I/O port to.Understand, by the institute in the state of the appearance of Electro-static Driven Comb event
Stating charge pump 3 can be stopped, so increasing the protective capability for the Electro-static Driven Comb that circuit is had no effect on after the charge pump 3.
Under chip normal operating conditions, the electrostatic that the I/O port does not occur, the output end of the Esd detection circuit
Signal be voltage V3 make the charge pump 3 work and by the first switch MP4 close, the first Electro-static Driven Comb crystal
Pipe MN0 grid disconnects and the connection of the I/O port and the output voltage of the charge pump 3 are connected to first electrostatic and released
Transistor MN0 grid is put, the output voltage V4 of the charge pump 3 makes the first Electro-static Driven Comb transistor MN0 be in deep close
Closed state, so that the electric leakage under reducing the first Electro-static Driven Comb transistor MN0 in off position；Described in Fig. 2, due to
The output voltage V4 of the charge pump 3 is negative pressure, and relative to the ground voltage shown in Fig. 1, the negative pressure of the embodiment of the present invention can make
The closing of the first Electro-static Driven Comb transistor MN0 it is tighter, OFF state electric leakage is that Ioff can be smaller.
In Fig. 2, the embodiment of the present invention has also further done following improvement：It is quiet that the static release circuit 2 also includes second
Electricity release transistor MN1.The second Electro-static Driven Comb transistor MN1 is also a NMOS tube, therefore is represented with MN1.Described second is quiet
Electricity release transistor MN1 size meets the requirement that Electro-static Driven Comb is carried out in the state of the appearance of Electro-static Driven Comb event.Including institute
The annexation for stating the static release circuit 2 after the second Electro-static Driven Comb transistor MN1 is：The first Electro-static Driven Comb crystal
Pipe MN0 source ground, the drain electrode of the first Electro-static Driven Comb transistor MN0 connects the second Electro-static Driven Comb transistor MN1
Source electrode.
The drain electrode of the second Electro-static Driven Comb transistor MN1 is connected to the I/O port, described by second switch MP0
Two Electro-static Driven Comb transistor MN1 drain electrode is connected to the internal source voltage of the chip by the 3rd switch MP1, described in Fig. 2
The voltage of the internal source voltage of chip is that internal source voltage voltage is represented with VDDCORE.
In the embodiment of the present invention, the second switch MP0 is a PMOS, therefore is represented with MP0；The second switch MP0
Grid connect the Esd detection circuit output end be connect voltage V3, the second switch MP0 source electrode connection it is described
I/O port, drain electrode connection the second Electro-static Driven Comb transistor MN1 of second switch MP0 grid.
The 3rd switch MP1 is a PMOS, therefore is represented with MP1；The grid connection of the 3rd switch MP1 is described quiet
In the inversion signal of the signal of the output end of electric circuit for detecting, Fig. 2, the signal of the output end of the Esd detection circuit it is anti-phase
Signal is voltage V2.The source electrode of the 3rd switch MP1 connects the internal source voltage of the chip, the 3rd switch MP1's
Drain electrode connection the second Electro-static Driven Comb transistor MN1 grid.
In the state of the appearance of Electro-static Driven Comb event, the second switch MP0 conductings and the 3rd switch MP1 are closed
Close so that the second Electro-static Driven Comb transistor MN1 and first Electro-static Driven Comb that the electrostatic of the I/O port passes through series connection
Transistor MN0 is discharged into ground.Understand, increase the Electro-static Driven Comb that circuit is had no effect on after the second Electro-static Driven Comb transistor MN1
Protective capability.
Under chip normal operating conditions, the second switch MP0 is closed and the 3rd switch MP1 conductings, described
The internal source voltage of the chip is connected to the first Electro-static Driven Comb transistor MN0's by the second Electro-static Driven Comb transistor MN1
Drain electrode, the characteristics of being less than the I/O port voltage VDDIO using the internal source voltage voltage VDDCORE of chip reduction is described
The voltage difference of first Electro-static Driven Comb transistor MN0 drain and gate, so as to reduce the first Electro-static Driven Comb transistor MN0's
Grid induced drain leaks electricity (GIDL), so can further reduce the OFF state electric leakage of the first Electro-static Driven Comb transistor MN0,
So as to the further power consumption for reducing circuit.
In Fig. 2, it is anti-phase that the Esd detection circuit includes first resistor R0, the first electric capacity C0, the first phase inverter and second
Device.
The first end of the first resistor R0 connects the I/O port, the second end connection of the first resistor R0 described the
One electric capacity C0 first end, the second end ground connection of the first electric capacity C0.
In Fig. 2, the second end output voltage V1 of the first resistor R0 and the input for connecting first phase inverter, institute
State the output end output voltage V2 of the first phase inverter and connect the input of second phase inverter, second phase inverter it is defeated
Go out to hold output voltage V3 as the output end of the Esd detection circuit.
Preferably, first phase inverter is CMOS inverter, and second phase inverter is CMOS inverter.In Fig. 2, institute
State the first phase inverter to be connected and formed by NMOS tube MN2 and PMOS MP2, second phase inverter is by NMOS tube MN3 and PMOS
MP3 connects to be formed.
In the embodiment of the present invention, the chip is included on more than one power domain, the I/O port ring of each power domain
Including multiple chip submodules, an Esd detection circuit and a charge pump 3 are set in the same power domain
And the Esd detection circuit and the charge pump 3 are arranged on the same chip submodule as an integral module 1
In, a static release circuit 2 is all set in each chip submodule of the same power domain, same described
In power domain, output voltage all overall signals of the signal of the output end of the Esd detection circuit and the charge pump 3 simultaneously send
The static release circuit 2 to each chip submodule of the same power domain.It can thus be appreciated that, although charge pump 3
Body can bring certain power consumption, but the present invention is by regarding the Esd detection circuit and the charge pump 3 as an entirety
Module 1 and it is provided only in the same chip submodule of power domain, namely only needs in a power domain to use one
Charge pump 3, relative to the situation for being required for setting charge pump 3 in each chip submodule of same power domain, the present invention is real
The power consumption that charge pump 3 itself is brought can be reduced to greatest extent by applying example.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of Electro-static Driven Comb clamp circuit, it is characterised in that including：Esd detection circuit, static release circuit and charge pump；
The Esd detection circuit is arranged between the I/O port of chip and ground, the electrostatic for detecting I O port；
The static release circuit includes the first Electro-static Driven Comb transistor, and the first Electro-static Driven Comb transistor is connected to the IO
Between port and ground；
The grid connection of the output end of the charge pump and the first Electro-static Driven Comb transistor；The Esd detection circuit it is defeated
Go out the input of the end connection charge pump；
The output end of the Esd detection circuit is also connected with the control end of first switch, and the first switch is connected to the IO ends
Between mouth and the grid of the first Electro-static Driven Comb transistor；
In the state of the appearance of Electro-static Driven Comb event, the Esd detection circuit detects the electrostatic that the I/O port occurs, institute
Stating the signal of the output end of Esd detection circuit makes the charge pump be stopped and open the first switch, and described
The grid connection I/O port of one Electro-static Driven Comb transistor is simultaneously turned under the control of I/O port voltage, so that by the I/O port
Electro-static Driven Comb to ground；
Under chip normal operating conditions, the electrostatic that the I/O port does not occur, the letter of the output end of the Esd detection circuit
Number make the charge pump and close the first switch, the grid of the first Electro-static Driven Comb transistor disconnects and institute
State the connection of I/O port and the output voltage of the charge pump is connected to the grid of the first Electro-static Driven Comb transistor, the electricity
The output voltage of lotus pump makes the first Electro-static Driven Comb transistor be in deep closed mode, so as to reduce first Electro-static Driven Comb
Transistor in off position under electric leakage.
2. Electro-static Driven Comb clamp circuit as claimed in claim 1, it is characterised in that：The first Electro-static Driven Comb transistor is one
NMOS tube, the size of the first Electro-static Driven Comb transistor is met carries out Electro-static Driven Comb in the state of the appearance of Electro-static Driven Comb event
Requirement；
The charge pump is negative pressure charge pump, and the output voltage of the charge pump is negative pressure.
3. Electro-static Driven Comb clamp circuit as claimed in claim 2, it is characterised in that：The static release circuit also includes second
Electro-static Driven Comb transistor；
The second Electro-static Driven Comb transistor is also a NMOS tube, and the size of the second Electro-static Driven Comb transistor is met in electrostatic
Release event carries out the requirement of Electro-static Driven Comb in the state of occurring；
The source ground of the first Electro-static Driven Comb transistor, the drain electrode connection described second of the first Electro-static Driven Comb transistor
The source electrode of Electro-static Driven Comb transistor；
The drain electrode of the second Electro-static Driven Comb transistor is connected to the I/O port, second Electro-static Driven Comb by second switch
The drain electrode of transistor is connected to the internal source voltage of the chip by the 3rd switch；
In the state of the appearance of Electro-static Driven Comb event, the second switch conducting and the 3rd switch are closed so that described
The electrostatic of I/O port is discharged into ground by the second Electro-static Driven Comb transistor and the first Electro-static Driven Comb transistor of series connection；
Under chip normal operating conditions, the second switch is closed and the 3rd switch conduction, and second electrostatic is released
The drain electrode that the internal source voltage of the chip is connected to the first Electro-static Driven Comb transistor by transistor is put, the chip is utilized
Internal source voltage voltage be less than the I/O port voltage the characteristics of reduce drain electrode and the grid of the first Electro-static Driven Comb transistor
The voltage difference of pole, so as to reduce the grid induced drain electric leakage of the first Electro-static Driven Comb transistor.
4. Electro-static Driven Comb clamp circuit as claimed in claim 3, it is characterised in that：The Esd detection circuit includes the first electricity
Resistance, the first electric capacity, the first phase inverter and the second phase inverter；
The first end of the first resistor connects the I/O port, and the second end of the first resistor connects first electric capacity
First end, the second end ground connection of first electric capacity；
Second end of the first resistor connects the input of first phase inverter, the output end connection of first phase inverter
The input of second phase inverter, the output end of second phase inverter as the Esd detection circuit output end.
5. Electro-static Driven Comb clamp circuit as claimed in claim 4, it is characterised in that：First phase inverter is that CMOS is anti-phase
Device, second phase inverter is CMOS inverter.
6. the Electro-static Driven Comb clamp circuit as described in Claims 2 or 3 or 4 or 5, it is characterised in that：The first switch is one
PMOS, the grid of the first switch connects the output end of the Esd detection circuit, the source electrode connection of the first switch
The I/O port, the grid of drain electrode connection the first Electro-static Driven Comb transistor of the first switch.
7. the Electro-static Driven Comb clamp circuit as described in claim 3 or 4 or 5, it is characterised in that：The second switch is a PMOS
Pipe, the grid of the second switch connects the output end of the Esd detection circuit, and the source electrode connection of the second switch is described
I/O port, the grid of drain electrode connection the second Electro-static Driven Comb transistor of the second switch.
8. the Electro-static Driven Comb clamp circuit as described in claim 3 or 4 or 5, it is characterised in that：3rd switch is a PMOS
Pipe, the grid of the 3rd switch connects the inversion signal of the signal of the output end of the Esd detection circuit, and the described 3rd opens
The source electrode of pass connects the internal source voltage of the chip, and the drain electrode of the 3rd switch connects the second Electro-static Driven Comb transistor
Grid.
9. the Electro-static Driven Comb clamp circuit as described in any claim in claim 1 to 5, it is characterised in that：The chip includes
Include on more than one power domain, the I/O port ring of each power domain in multiple chip submodules, the same power domain
Set an Esd detection circuit and a charge pump and using the Esd detection circuit and the charge pump as
One integral module is arranged in the same chip submodule, in each chip submodule of the same power domain
One static release circuit, in the same power domain, the signal of the output end of the Esd detection circuit are all set
With output voltage all overall signals of the charge pump and give described in each chip submodule of the same power domain
Static release circuit.
10. Electro-static Driven Comb clamp circuit as claimed in claim 1, it is characterised in that：The first Electro-static Driven Comb transistor is
One PMOS, the size of the first Electro-static Driven Comb transistor meets the progress electrostatic in the state of the appearance of Electro-static Driven Comb event and released
The requirement put；
The charge pump is malleation charge pump, and the output voltage of the charge pump is malleation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710455287.0A CN107331660B (en) | 2017-06-16 | 2017-06-16 | Electrostatic discharge clamping circuit |
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| CN107331660B CN107331660B (en) | 2020-02-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310379B1 (en) * | 1999-06-03 | 2001-10-30 | Texas Instruments Incorporated | NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors |
| CN102754335A (en) * | 2010-01-19 | 2012-10-24 | 高通股份有限公司 | High voltage, high frequency esd protection circuit for RF ICs |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN106816865A (en) * | 2017-02-08 | 2017-06-09 | 上海华虹宏力半导体制造有限公司 | Esd protection circuit |
-
2017
- 2017-06-16 CN CN201710455287.0A patent/CN107331660B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310379B1 (en) * | 1999-06-03 | 2001-10-30 | Texas Instruments Incorporated | NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors |
| CN102754335A (en) * | 2010-01-19 | 2012-10-24 | 高通股份有限公司 | High voltage, high frequency esd protection circuit for RF ICs |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN106816865A (en) * | 2017-02-08 | 2017-06-09 | 上海华虹宏力半导体制造有限公司 | Esd protection circuit |
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| CN107331660B (en) | 2020-02-07 |
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