CN106841823A - A kind of open-loop voltage detecting system - Google Patents
A kind of open-loop voltage detecting system Download PDFInfo
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- CN106841823A CN106841823A CN201710016282.8A CN201710016282A CN106841823A CN 106841823 A CN106841823 A CN 106841823A CN 201710016282 A CN201710016282 A CN 201710016282A CN 106841823 A CN106841823 A CN 106841823A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention discloses a kind of open-loop voltage detecting system, including level transmission circuit, clamp circuit, cut-in voltage produce circuit, Combinational Logic Control circuit；Level transmission circuit is used to, according to the incoming level signal for receiving, produce medium voltage；Cut-in voltage produces circuit to produce the level higher than medium voltage as cut-in voltage, for controlling level transmission circuit to turn on；On the other hand, when incoming level signal is less than or equal to secure threshold, there is no clamping action to medium voltage in clamp circuit, medium voltage is equal with input voltage, and level transmission circuit is directly exported medium voltage as detection level；When input voltage is more than default clamper threshold value, signal of the clamp circuit according to Combinational Logic Control circuit output, medium voltage is clamped to required clamper threshold value, cut-in voltage is clamped to corresponding clamper threshold value simultaneously, while ensureing that electric current is effective between incoming level signal and medium voltage, detection level of the ultra-low loss output in secure threshold.
Description
Technical field
The present invention relates to circuit signal treatment, more particularly to a kind of open-loop voltage detecting system.
Background technology
, it is necessary to have the load switching circuit of two-way admittance function in the charger device of OTG loads is applied to, can
Enough meet power supply to charge host device, can also realize accessing the charging that host device loads OTG when OTG is loaded
Implement, when system judges that transmission line connection status is that OTG is loaded also or during power supply adaptor, it is necessary to one can sense access
The detection level of the stabilization safety of signal, to carry out gating control to two-way admittance load switch；
When USB interface is inserted, the chip pin in external environment condition may be introduced greatly very much can more than chip
The high-voltage pulse for sustaining even surge level, in this case, needs to carry out to the level signal more than secure threshold
Clamper, makes host computer system receive only the detection signal of significant level, and clamper isolation is carried out for unsafe high pressure.
The content of the invention
It is an object of the invention to provide a kind of open-loop voltage detecting system, realize that USB port accesses effective electricity when loading
It is flat to judge, while clamper is carried out to the level signal higher than secure threshold, it is right while sensing mark into level to achieve a butt joint
The level protection of main frame.
To achieve the above object, the embodiment of the present invention provides a kind of open-loop voltage detecting system.The system includes：
Level transmission circuit, for according to the incoming level signal for receiving, producing and exporting medium voltage, and is opening electricity
Turned under the control of pressure, detection level of the output in secure threshold；
Clamp circuit, for by medium voltage and cut-in voltage clamper, when the incoming level signal exceeds secure threshold
When, medium voltage is clamped to the first clamper threshold value by the clamp circuit, while being clamped to the second clamper by by cut-in voltage
Threshold value, the size of current between control input level signal and medium voltage.
Preferably, the clamp circuit is compared by by medium voltage and the first clamper threshold value, judges described
Whether incoming level signal is in secure threshold；
When the medium voltage is less than the first clamper threshold value, the incoming level signal is in secure threshold, described
Level transmission circuit is exported the medium voltage as detection level；
When the medium voltage be equal to the first clamper threshold value when, the incoming level signal be equal to secure threshold, it is described in
Between voltage be equal to the incoming level signal；The level transmission circuit is exported the medium voltage as detection level；
When the medium voltage is more than the first clamper threshold value, the incoming level signal exceeds secure threshold, the pincers
The medium voltage is clamped to the first clamper threshold value by position circuit, and the level transmission circuit is by the medium voltage after the clamper
Exported as detection level.
Preferably, the clamp circuit is by between the medium voltage and ground, and on the cut-in voltage and ground
Between connect some diodes, clamper is carried out to the medium voltage and the cut-in voltage.
Preferably, the clamp circuit is reverse, positive by gating or it combines the diode for accessing, and presets first and clamps
Position threshold value and the second clamper threshold value.
Preferably, the clamp circuit is reverse, positive according to Combinational Logic Control signal gating or it combines what is accessed
Diode, presets the first clamper threshold value and the second clamper threshold value.
Preferably, the second clamper threshold value is equal to the first clamper threshold value and first voltage sum.
Preferably, the clamp circuit includes gating module and clamper module；
Gating module, for the first clamper threshold value according to Combinational Logic Control signal gating and the second clamper threshold
Value；
Clamper module, for carrying out clamper to the medium voltage according to the first clamper threshold value of the gating, and will
The cut-in voltage is clamped to the second clamper threshold value.
Preferably, the clamper module includes the 4th metal-oxide-semiconductor, the first diode, the second diode, the 3rd diode, the
Four diodes, the 5th diode, the 6th diode；The diode selects Zener diode；
First diode, the 3rd diode, the 4th diode, the 5th diode, the 6th diode are sequentially connected in series；The
One diode, the 3rd diode, the 4th diode are reversely access；5th diode, the 6th diode are accessed for positive；First
The negative pole of diode is used to receive medium voltage；The negative pole of the 6th diode connects common reference ground；The positive pole of the second diode connects
Connect the negative pole of the 3rd diode；The negative pole of the second diode connects the source electrode of the 4th metal-oxide-semiconductor；The grid of the 4th metal-oxide-semiconductor and drain electrode
Short circuit；The drain electrode of the 4th metal-oxide-semiconductor is used to receive cut-in voltage；
Voltage difference between the grid and source electrode of the 4th metal-oxide-semiconductor is first voltage；
The gating module includes the first gating switch, the second gating switch, the 3rd gating switch；
Node between drain electrode connection the 3rd diode of the first gating switch and the 4th diode, the first gating is opened
The source ground of pass；Node between drain electrode connection the 4th diode of the second gating switch and the 5th diode, second
The source ground of gating switch；Section between drain electrode connection the 5th diode of the 3rd gating switch and the 6th diode
Point, the source ground of the 3rd gating switch；The grid of first gating switch, the grid of the second gating switch, the 3rd gating
The grid of switch is used to receive Combinational Logic Control signal.
Preferably, the level transmission circuit includes transport module and module of releasing；
The transport module includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor；
The first metal-oxide-semiconductor source electrode connects the source electrode of the second metal-oxide-semiconductor, and the first metal-oxide-semiconductor grid connects the grid of the second metal-oxide-semiconductor
Pole, the drain electrode of the first metal-oxide-semiconductor is used to receive incoming level signal, and the drain electrode of the second metal-oxide-semiconductor is used to export detection level, first
Node is taken between the source electrode of the source electrode of metal-oxide-semiconductor and the second metal-oxide-semiconductor for exporting medium voltage, the grid of the first metal-oxide-semiconductor and second
Node is taken between the grid of metal-oxide-semiconductor for receiving cut-in voltage；Electric current between first metal-oxide-semiconductor drain electrode, source electrode with it is described
Current in proportion relation between the 4th metal-oxide-semiconductor grid, source electrode；
The module of releasing includes the 3rd metal-oxide-semiconductor, first resistor；
The drain electrode of the 3rd metal-oxide-semiconductor of one end connection of the first resistor, the source ground of the 3rd metal-oxide-semiconductor, first resistor
The drain electrode of the second metal-oxide-semiconductor in other end connection transport module, the grid of the 3rd metal-oxide-semiconductor is used to receive enable switch controlling signal；
First metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, from low conduction impedance device.
Preferably, described open-loop voltage detecting system, it is characterised in that also produce circuit including cut-in voltage；
Cut-in voltage produces circuit, for the medium voltage for receiving to be raised into voltage magnitude, produces for opening electricity
The cut-in voltage of flat transmission circuit；When the incoming level blackout, cut-in voltage produces circuit to stop producing unlatching electricity
Pressure, level transmission circuit is closed, while the electric current of the flat transmission circuit output end of vent discharge.
The open-loop voltage detecting system provided using the present invention, because present invention design is in level transmission circuit, is wrapped
Such as the transport module for including and module of releasing, the metal-oxide-semiconductor for using are low conduction impedance device, preferable NDMOS pipes, therefore work as
Incoming level signal is in when in secure threshold, and transport module can be realized exporting it with ultra-low loss, when incoming level signal
During beyond secure threshold, transport module using through the medium voltage after clamp circuit clamper as detection level, equally with ultralow damage
Consumption output, it is ensured that detection level follows the change of incoming level signal, in addition, module of releasing is responsible for when system is closed, by electricity
Current drain in flat transmission circuit, in order to avoid influence is produced on the outer application system using detection level.
It is on the other hand, of the invention when clamp circuit is designed in order to realize detection level of the output in secure threshold,
By some diodes of connecting, to middle voltage clamping, when incoming level signal is in secure threshold, clamp circuit is not moved
Make, level transmission circuit will be equal to the medium voltage of incoming level signal as detection level, directly be exported with ultra-low loss, when
When incoming level signal exceeds secure threshold, i.e., when medium voltage exceeds secure threshold, be clamped to for medium voltage by clamp circuit
First clamper threshold value, it is ensured that the detection level of level transmission circuit output is safe, stabilization, is operated in secure threshold
Level.
Additionally, after medium voltage is clamped, certain voltage difference occurs between incoming level signal and medium voltage,
The drain-source interpolar of the first metal-oxide-semiconductor occurs excessive electric current in transport module, to avoid the electric current from causing to damage to the first metal-oxide-semiconductor
It is bad, and avoid when the present invention is when different incoming level signals are detected, electric current influence Detection results, it is therefore desirable to the
The electric current (electric current i.e. between incoming level signal and medium voltage) of the drain-source interpolar of one metal-oxide-semiconductor is controlled, therefore, this pincers
Cut-in voltage is clamped to the second clamper threshold value by position circuit while medium voltage is clamped into the first clamper threshold value, makes the
Four metal-oxide-semiconductors and a MOS form current mirror, and then can be by controlling the electric current between the 4th metal-oxide-semiconductor hourglass source electrode, by a MOS
The control of pipe drain-source interpolar is in required and effective scope, it is ensured that the safety of level transmission circuit, is further ensured that output
Detection level is safe, stabilization, is operated in the level in secure threshold.
Additionally, to realize according to different clamper demands, this clamp circuit in series diode, by reversely accessing and
Forward direction accesses the diode of varying number, when the diode conducts, is hit by the reverse of each diode for being superimposed respective numbers
Voltage and forward conduction voltage are worn, and then realizes presetting clamper threshold value on demand；And to improve the convenience of clamper threshold value selection,
The present invention can be exported according to the various combination of Combinational Logic Control signal, you can needed for the gating module gating of control clamp circuit
Clamper threshold value.
Brief description of the drawings
Fig. 1 is a kind of structural representation of open-loop voltage detecting system that the embodiment of the present invention one is provided；
Fig. 2 is the electrical block diagram of level transmission circuit；
Fig. 3 is the electrical block diagram of clamp circuit；
Fig. 4 is the electrical block diagram that cut-in voltage produces circuit；
Fig. 5 is the electrical block diagram that cut-in voltage produces after circuits improvement in Fig. 3.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
Fig. 1 is a kind of structural representation of open-loop voltage detecting system that the embodiment of the present invention one is provided.As shown in figure 1,
A kind of open-loop voltage detecting system that the present invention is provided, including level transmission circuit 101, clamp circuit 102, cut-in voltage are produced
Circuit 103, Combinational Logic Control circuit 104.
Level transmission circuit 101 produces and exports middle voltage VM ID according to the incoming level signal USBIN for receiving；When
Incoming level signal USBIN be in secure threshold in when, level transmission circuit 101 using middle voltage VM ID as detection level
USB_SNS is directly exported；When incoming level signal USBIN exceeds secure threshold, level transmission circuit 101 is by after clamper
Between voltage VMID as detection level USB_SNS exported；When incoming level signal USBIN disappears, level transmission circuit
101 close, while the electric current of the flat output end of transmission circuit 101 of vent discharge.
Cut-in voltage produces circuit 103 according to the middle voltage VM ID for receiving, and cut-in voltage VON is produced, for controlling electricity
Flat transmission circuit 101 is turned on；When incoming level signal USBIN disappears, cut-in voltage produces circuit 103 to stop producing unlatching electricity
Pressure VON, level transmission circuit 101 is closed.
Clamp circuit 102 receives middle voltage VM ID, when incoming level signal USBIN exceeds secure threshold, clamper electricity
Middle voltage VM ID is clamped to the first clamper threshold value by road 102, while cut-in voltage VON is clamped into the second clamper threshold value.
Combinational Logic Control circuit 104 is produced and output combinational logic control signal, and the control gating of clamp circuit 102 needs
The first clamper threshold value and the second clamper threshold value.
Level transmission circuit 101 produces middle voltage VM ID according to the incoming level signal USBIN for receiving, and by centre
Voltage VMID is exported produce circuit 103 to clamp circuit 102 and cut-in voltage respectively；Cut-in voltage produces circuit 103 in difference
Under the driving of clock signal clkn and clkp, middle voltage VM ID is raised into a clock amplitude, produced for controlling level to pass
The cut-in voltage VON of transmission of electricity road 101 conducting；On the other hand, after clamp circuit 102 receives middle voltage VM ID, when middle electricity
Pressure VMID is in when in secure threshold, and clamp circuit 102 does not occur clamping action to medium voltage VMID, now level transmission electricity
Road 101 directly exports middle voltage VM ID as detection level USB_SNS；When medium voltage VMID exceeds secure threshold,
The Combinational Logic Control signal that clamp circuit 102 is exported according to Combinational Logic Control circuit 104, middle voltage VM ID is clamped to
First clamper threshold value, level transmission circuit 101 will be exported through the middle voltage VM ID after clamper as detection level USB_SNS；
Additionally, clamp circuit 102 by middle voltage VM ID while the first clamper threshold value is clamped to, cut-in voltage VON is clamped to
Second clamper threshold value, is further ensured that level transmission circuit 101 stably exports detection level USB_SNS；When incoming level letter
When number USBIN disappears, cut-in voltage produces circuit 103 under the control of the enable signal of applications, stops output and opens electricity
Pressure VON, now level transmission circuit 101 close, while by the current drain of the output end of level transmission circuit 101.
Fig. 2 is the electrical block diagram of level transmission circuit 101.As shown in Fig. 2 level transmission circuit 101 includes passing
Defeated module and module of releasing.
Transport module includes metal-oxide-semiconductor MN1, metal-oxide-semiconductor MN2.
Wherein, the source electrode of metal-oxide-semiconductor MN1 source electrodes connection metal-oxide-semiconductor MN2, the grid of metal-oxide-semiconductor MN1 grids connection metal-oxide-semiconductor MN2,
The drain electrode that the drain electrode of metal-oxide-semiconductor MN1 is used to receive incoming level signal USBIN, metal-oxide-semiconductor MN2 is used to export detection level USB_
Node is taken between the source electrode of SNS, metal-oxide-semiconductor MN1 and the source electrode of metal-oxide-semiconductor MN2 for exporting middle voltage VM ID, the grid of metal-oxide-semiconductor MN1
Node is taken between the grid of pole and metal-oxide-semiconductor MN2 for receiving cut-in voltage VON.
Wherein, module of releasing includes metal-oxide-semiconductor MN3, resistance R1.One end of resistance R1 connects the drain electrode of metal-oxide-semiconductor MN3, metal-oxide-semiconductor
The source ground of MN3, the drain electrode of metal-oxide-semiconductor MN2 in the other end connection transport module of resistance R1, the grid of metal-oxide-semiconductor MN3 is used to connect
Receive and enable switch controlling signal ENB.
Above-mentioned metal-oxide-semiconductor MN1, metal-oxide-semiconductor MN2, metal-oxide-semiconductor MN3, from low conduction impedance device, the preferred NDMOS of the present embodiment
Pipe, realizes the ultra-low loss transmission of incoming level signal USBIN, it is ensured that detection level USB_SNS follows incoming level signal
The change of USBIN.
Transport module produces middle voltage VM ID, and export respectively to clamper according to the incoming level signal USBIN for receiving
Circuit 102 and cut-in voltage produce circuit 103；Transport module produces the cut-in voltage VON's of the output of circuit 103 in cut-in voltage
The lower conducting of control, and stabilization, safety detection level USB_SNS is exported under the control of clamp circuit 102；Work as transport module
During closing, module of releasing is in the case where applications enable the control of signal ENB by the current drain of transport module output end.
Because in the present embodiment, metal-oxide-semiconductor MN1 is switching tube, therefore, when the USBIN that transport module is received is in safety threshold
When in value, the middle voltage VM ID of transport module output is equal to incoming level signal USBIN, and now transport module is by medium voltage
VMID is directly exported as detection level USB_SNS with ultra-low loss；When incoming level signal USBIN exceeds secure threshold,
Middle voltage VM ID is clamped to the first clamper threshold value by clamp circuit 102, and transport module makees the middle voltage VM ID after clamper
For detection level USB_SNS is exported with ultra-low loss；When incoming level signal USBIN disappears, cut-in voltage produces circuit 103
Stop output cut-in voltage VON, and then closing transmission module under the control of applications, module of now releasing is enabling switch
Turned under the control of control signal ENB, by the current drain of transport module output end.
Fig. 3 is the electrical block diagram of clamp circuit.As shown in figure 3, clamp circuit 102 includes clamper module and gating
Module.
Clamper module includes metal-oxide-semiconductor MN4, diode D1, diode D2, diode D3, diode D4, diode D5, two
Pole pipe D6；Metal-oxide-semiconductor MN4 is managed for NDMOS.The diode selects Zener diode.
Wherein, diode D1, diode D3, diode D4, diode D5, diode D6 are sequentially connected in series；Diode D1, two
Pole pipe D3, diode D4 are reversely access；Diode D5, diode D6 are accessed for positive；The negative pole of diode D1 is used to receive
Middle voltage VM ID；The negative pole of diode D6 connects common reference ground；The negative pole of the cathode connecting diode D3 of diode D2；Two poles
The source electrode of the negative pole connection metal-oxide-semiconductor MN4 of pipe D2；The grid and drain electrode short circuit of metal-oxide-semiconductor MN4；The drain electrode connection level of metal-oxide-semiconductor MN4
The grid of metal-oxide-semiconductor MN1 in transmission circuit 101, receives cut-in voltage VON；Metal-oxide-semiconductor MN4 and metal-oxide-semiconductor MN1 forms current mirror.
Gating module includes gating switch MN21, gating switch MN22, gating switch MN23.The gating switch is selected
NMOS tube.
Wherein, the grid of gating switch MN21 is used to receive switch control level Vclamp1, the drain electrode of gating switch MN21
Node between connection diode D3 and diode D4, the source electrode of gating switch MN21 connects common reference ground；Gating switch MN22
Grid be used for receive switch control level Vclamp2, gating switch MN22 drain electrode connection diode D4 and diode D5 it
Between node, the source electrode of gating switch MN22 connects common reference ground；The grid of gating switch MN23 is used to receive switch control electricity
Node between the drain electrode connection diode D5 and diode D6 of flat Vclamp1, gating switch MN23, the source of gating switch MN23
Pole connects common reference ground.
Gating module is according to switch control level Vclamp1, switch control level Vclamp2, switch control level
The various combination output of Vclamp3, gates the diode of respective numbers, so that default first clamper threshold value and the second clamper threshold
Value；First clamper threshold value is equal to the secure threshold of incoming level USBIN；Second clamper threshold value is equal to the first clamper threshold value and first
Voltage sum, wherein, first voltage is the voltage difference VGS between metal-oxide-semiconductor MN4 grids and source electrode.
Clamper module compares the middle voltage VM ID of reception with the first clamper threshold value, when medium voltage VMID is not more than
During one clamper threshold value, there is no clamping action in clamp circuit 102 to medium voltage VMID and cut-in voltage VON；When middle electricity
When pressure VMID is more than the first clamper threshold value, middle voltage VM ID is clamped to the first clamper threshold value by clamp circuit 102.
After to medium voltage VMID clampers, had between incoming level signal USBIN and middle voltage VM ID certain
Pressure difference, metal-oxide-semiconductor MN1 can be caused to drain and excessive electric current to be produced and source electrode between (i.e. incoming level signal USBIN is to middle electric
Press the electric current of VMID), the damage of metal-oxide-semiconductor MN1 can be caused, and when requiring to detect the incoming level signal USBIN of particular value,
Metal-oxide-semiconductor MN1 drains and the electric current between source electrode is no more than corresponding current value, otherwise will influence incoming level signal USBIN
Detection, and detection level USB_SNS output；
Therefore, while to medium voltage VMID clampers, cut-in voltage VON is clamped into the second required clamper threshold
Value；After clamper, metal-oxide-semiconductor MN4 and metal-oxide-semiconductor MN1 form current mirror relationship to cut-in voltage VON, the drain electrode of metal-oxide-semiconductor MN4, source electrode it
Between electric current and the electric current between drain electrode, the source electrode of metal-oxide-semiconductor MN1 then there is the proportionate relationship of stabilization, therefore can be according to the ratio
Relation, by controlling the electric current between the drain electrode of metal-oxide-semiconductor MN4 and source electrode, by the electric current between the drain electrode of metal-oxide-semiconductor MN1 and source electrode
Control required, and in effective working range, for example：In the present embodiment, the electric current between drain electrode, the source electrode of metal-oxide-semiconductor MN4
The Proportionality design of the electric current between drain electrode, source electrode with metal-oxide-semiconductor MN1 is：1:100, when by between the drain electrode of metal-oxide-semiconductor MN4, source electrode
Current control be 10uA when, the electric current 1mA between drain electrode, the source electrode of metal-oxide-semiconductor MN1；In other application, the leakage of metal-oxide-semiconductor MN4
The proportionate relationship of the electric current between pole, source electrode and the electric current between drain electrode, the source electrode of metal-oxide-semiconductor MN1, can according to demand carry out difference
Adjustment.
The following is the clamper process of middle voltage VM ID and cut-in voltage VON：
First, the first clamper threshold value and the second clamper threshold value are preset.Because technique is different, the breakdown reverse voltage of diode
Generally 5V-7V, forward conduction voltage is generally 0.5V-0.7V；The preferred diode of the present embodiment, breakdown reverse voltage is all
6V, forward voltage is all 0.6V；When gating module according to switch control level Vclamp1, switch control level Vclamp2, open
The various combination output of control level Vclamp3 is closed, the reverse access diode of respective numbers is gated and is accessed diode with positive,
So as to set the first clamper threshold value, the second clamper threshold value；The preset procedures of various first clamper threshold values and the second clamper threshold value are：
It is low, switch control level Vclamp3 for low, switch controls level Vclamp2 when switch controls level Vclamp1
For it is low when, gating switch MN21 disconnect, gating switch MN22 disconnect, gating switch MN23 disconnect, diode D1, diode D2,
Diode D3, diode D4, diode D5, diode D6 are both turned on, the first clamper threshold value：6V*3+0.6V=19.2V；Second
Clamper threshold value：19.2V+VGS, VGS are that metal-oxide-semiconductor MN4 gate-source voltages are poor, i.e. the value of first voltage；
It is low, switch control level Vclamp3 for low, switch controls level Vclamp2 when switch controls level Vclamp1
For it is high when, gating switch MN21 disconnect, gating switch MN22 disconnect, gating switch MN23 conducting, diode D1, diode D2,
Diode D3, diode D4, diode D5 are both turned on, and diode D6 is shorted, the first clamper threshold value：6V*3+0.6V*1=
18.6V；Second clamper threshold value：18.6V+VGS；
It is high, switch control level Vclamp3 for low, switch controls level Vclamp2 when switch controls level Vclamp1
For it is low when, gating switch MN21 disconnect, gating switch MN22 conducting, gating switch MN23 disconnect, diode D1, diode D2,
Diode D3, diode D4 are both turned on, and diode D5, diode D6 are shorted, the first clamper threshold value：6V*3=18V；Second pincers
Position threshold value：18V+VGS, VGS are the value of first voltage；
It is low, switch control level Vclamp3 for high, switch controls level Vclamp2 when switch controls level Vclamp1
For it is low when, gating switch MN21 conducting, gating switch MN22 disconnect, gating switch MN23 disconnect, diode D1, diode D2,
Diode D3 is turned on, and diode D4, diode D5, diode D6 are shorted, the first clamper threshold value：6V*2=12V；Second clamper
Threshold value：12V+VGS.
In other practical applications, clamp circuit 102 can according to the actual requirements use more diodes, set more
Clamper threshold value is for selection.
Default first clamper threshold value, the second clamper threshold value, for example：First clamper threshold value is：During 6V*3+0.6V=19.2V；
Second clamper threshold value is：19.2V+VGS；
When the middle voltage VM ID that clamper module is received is less than 19.2V, diode D1, diode D2, diode D3, two
Pole pipe D4, diode D5, diode D6 are not acted, level transmission circuit 101 using middle voltage VM ID as detection level
USB_SNS is directly exported；
When the middle voltage VM ID that clamper module is received is equal to 19.2V, diode D1, diode D3, diode D4, two
Pole pipe D5, diode D6 are turned on, and now the value of middle voltage VM ID is exactly clamper threshold value, similarly, level transmission circuit 101
Directly exported middle voltage VM ID as detection level USB_SNS；
When the middle voltage VM ID that clamper module is received is more than 19.2V, diode D1, diode D2, diode D3, two
Pole pipe D4, diode D5, diode D6 are turned on, and middle voltage VM ID is clamped into 19.2V, meanwhile, by cut-in voltage VON pincers
To 19.2V+VGS, the electric current between now metal-oxide-semiconductor MN4 drain electrodes and source electrode is 20uA, between metal-oxide-semiconductor MN1 drain electrodes and source electrode for position
Electric current is 2mA.
Fig. 4 is the electrical block diagram that cut-in voltage produces circuit 103.Due to the transmission in level transmission circuit 101
Module is switched as conducting using NDMOS, it is necessary to the current potential of grid is higher than source voltage, and incoming level signal USBIN is outer
The ceiling voltage that portion provides, in order that the transport module conducting in level transmission circuit 101, the grid of metal-oxide-semiconductor MN1 and metal-oxide-semiconductor MN2
Pole need to obtain voltage higher, for example：During USBIN=10V, then the grid that metal-oxide-semiconductor MN1 and metal-oxide-semiconductor MN2 needs connects the electricity of 15V
Pressure could drive, therefore the cut-in voltage generation circuit 103 of the present embodiment need to be using the frame mode of charge pump.
As shown in figure 4, cut-in voltage produce circuit 103 include metal-oxide-semiconductor MN5, metal-oxide-semiconductor MN6, metal-oxide-semiconductor MN7, metal-oxide-semiconductor MN8,
Metal-oxide-semiconductor MN9, metal-oxide-semiconductor MP1, metal-oxide-semiconductor MP2, electric capacity C1, electric capacity C2.
One end of electric capacity C1 is used to receive clock signal clkn, drain electrode, the MOS of the other end connection metal-oxide-semiconductor MN5 of electric capacity C1
The drain electrode of the drain electrode of pipe MP1, the grid of metal-oxide-semiconductor MN6, the grid of metal-oxide-semiconductor MP2 and metal-oxide-semiconductor MN7, the source ground of metal-oxide-semiconductor MN7；
It is a pair of differential clocks letters that one end of electric capacity C2 is used to receive clock signal clkp, clock signal clkp and clock signal clkn
Number, the grid of the other end of electric capacity C2 connection metal-oxide-semiconductor MP1, the drain electrode of metal-oxide-semiconductor MP2, the grid of metal-oxide-semiconductor MN5, metal-oxide-semiconductor MN6
Drain electrode and the drain electrode of metal-oxide-semiconductor MN8, the source ground of metal-oxide-semiconductor MN8, the source electrode of the source electrode connection metal-oxide-semiconductor MN6 of metal-oxide-semiconductor MN5, MOS
Node is taken between the source electrode of pipe MN5 and the source electrode of metal-oxide-semiconductor MN6 for receiving middle voltage VM ID, the source electrode connection of metal-oxide-semiconductor MP1
The drain electrode of the source electrode and metal-oxide-semiconductor MN9 of metal-oxide-semiconductor MP2, the drain electrode of metal-oxide-semiconductor MN9 is used to export cut-in voltage VON, the grid of metal-oxide-semiconductor MN7
Pole, the grid of metal-oxide-semiconductor MN8, the grid of metal-oxide-semiconductor MN9 are turned on by switch controlling signal ENB controls are enabled.
After cut-in voltage produces circuit 103 to receive middle voltage VM ID, driven in differential clock signal clkn and clkp
Lower work.
Clkn and clkp is two clock signals of opposite in phase.When clkn is low level, and clkp is high, metal-oxide-semiconductor MN5
With metal-oxide-semiconductor MP2 conductings, metal-oxide-semiconductor MN5 drain voltages are equal to VMID, to electric capacity C1 chargings (until anode is changed into VMID), while
The drain voltage of metal-oxide-semiconductor MP2 is equal to VON (exporting).When clkn high level, when clkp is low, metal-oxide-semiconductor MN6 and metal-oxide-semiconductor MP1
Conducting, while drain electrode (i.e. the drain electrode of metal-oxide-semiconductor MP2) voltage of metal-oxide-semiconductor MN6 is equal to VMID, charges (until anode becomes to electric capacity C2
It is VMID), while metal-oxide-semiconductor MP1 drain electrode (i.e. metal-oxide-semiconductor MN5 drain electrodes) voltages are equal to VON (exporting).
Therefore, when clkn is changed into high level from low level (i.e. when clkp is changed into low level from high level), metal-oxide-semiconductor MN6
Conducting, the voltage of electric capacity C1 anodes is increased to VMID+VCLK from VMID, and now, metal-oxide-semiconductor MP1 is turned on, therewith cut-in voltage VON
Also it is increased to VMID+VCLK from VMID；
When clkp is changed into high level from low level (i.e. when clkn is changed into low level from high level), metal-oxide-semiconductor MN5 conductings,
The voltage of electric capacity C2 anodes is increased to VMID+VCLK from VMID, now, metal-oxide-semiconductor MP2 conducting, therewith cut-in voltage VON also from
VMID is increased to VMID+VCLK.
By above procedure, the low and high level of clock signal clkn and clkp back and forth switches, and cut-in voltage is produced circuit
103 produce stable, higher than incoming level signal USBIN cut-in voltage VON, for switching control level transmission circuit 101
Conducting.
When incoming level signal USBIN disappears, metal-oxide-semiconductor MN7, metal-oxide-semiconductor MN8, metal-oxide-semiconductor MN9 are enabling switch control
Turned under the control of signal ENB, clock signal clkn is grounded through metal-oxide-semiconductor MN7, clock signal clkp is grounded through metal-oxide-semiconductor MN8, MOS
Cut-in voltage is produced pipe MN9 the current drain in circuit 103, and cut-in voltage produces circuit 103 to stop output cut-in voltage
VON, level transmission circuit 101 is also accordingly turned off.
For ease of realizing the selection of various first clamper threshold values, the second clamper threshold value, the Combinational Logic Control shown in Fig. 1
Circuit 104, can produce the Combinational Logic Control signal that level is controlled comprising multiple switch according to the demand of clamp circuit 102；This
In embodiment, the Combinational Logic Control signal that Combinational Logic Control circuit 104 is produced includes switch control level Vclamp1, opens
Close control level Vclamp2, switch control level Vclamp3.
Represent low level with 0,1 represents high level, then switch control level Vclamp1, switch control level Vclamp2,
The combination Vclamp1/Vclamp2/Vclamp3 of switch control level Vclamp3 has：000、001、010、011、100、
101、110、111.According to the actual annexation of clamp circuit 102, Combinational Logic Control signal 100,101,110,111 is set
Clamper threshold value be all 12V, therefore be equivalent, thus only take it is 100,101,110,111 one of as output, together
Sample, 010,011 is equivalent, and the clamper threshold value of setting is all 18V, therefore selection 010 or 011 is used as output.
In other practical applications, Combinational Logic Control circuit 104 can be produced by more switch control electricity according to demand
The flat Combinational Logic Control signal for combining.
Fig. 5 is the electrical block diagram after cut-in voltage produces circuit 103 improved.As shown in figure 5, by each
Individual high-voltage path accesses protective resistance, obtain with high voltage nodes protective effect and service life high be longer and reliability more
Cut-in voltage high produces circuit.
The protective resistance includes resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance
R9, resistance R10, resistance R11 and resistance R12.
Wherein, one end of electric capacity C1 is used to receive clock signal clkn, the other end of electric capacity C1 and the drain electrode of metal-oxide-semiconductor MN7
Between series resistance R2, resistance R3, series resistance R4, resistance R5 between the drain electrode of metal-oxide-semiconductor MN5 and the drain electrode of metal-oxide-semiconductor MP1, electricity
Node between resistance R2, resistance R3 and the node connection between resistance R4, resistance R5；One end of electric capacity C2 is used to receive clock letter
Number clkp, series resistance R10, resistance R11 between the drain electrode of the electric capacity C2 other ends and metal-oxide-semiconductor MN8, the drain electrode of metal-oxide-semiconductor MN6 and
Series resistance R8, resistance R9 between the drain electrode of metal-oxide-semiconductor MP2, node and resistance R10 between resistance R8, resistance R9, resistance R11
Between node connection, the source electrode and the source electrode of metal-oxide-semiconductor MN6 of one end connection metal-oxide-semiconductor MN5 of resistance R6, the other end of resistance R6
For receiving middle voltage VM ID, one end of resistance R7 connects the source electrode of metal-oxide-semiconductor MP1 and the source electrode of metal-oxide-semiconductor MP2, resistance R7's
Series resistance R12 between the drain electrode of the other end and metal-oxide-semiconductor MN9, the node between resistance R7 and resistance R12 is used to export opens electricity
Pressure VON.
Above-described specific embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that and the foregoing is only specific embodiment of the invention, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc. all should include
Within protection scope of the present invention.
Claims (10)
1. a kind of open-loop voltage detecting system, it is characterised in that including：
Level transmission circuit (101), for according to the incoming level signal (USBIN) for receiving, producing and exporting medium voltage
(VMID), and under the control of cut-in voltage (VON) turn on, detection level (USB_SNS) of the output in secure threshold；
Clamp circuit (102), for by medium voltage (VMID) and cut-in voltage (VON) clamper, when the incoming level signal
(USBIN) when exceeding secure threshold, medium voltage (VMID) is clamped to the first clamper threshold value by the clamp circuit (102), together
When be clamped to the second clamper threshold value, control input level signal (USBIN) and medium voltage by by cut-in voltage (VON)
(VMID) size of current between.
2. open-loop voltage detecting system according to claim 1, it is characterised in that the clamp circuit (102) will be by will
Medium voltage (VMID) and the first clamper threshold value are compared, and judge whether the incoming level signal (USBIN) is in
In secure threshold；
When the medium voltage (VMID) is less than the first clamper threshold value, the incoming level signal (USBIN) is in safety threshold
In value, the level transmission circuit (101) exports the medium voltage (VMID) as detection level (USB_SNS)；
When the medium voltage (VMID) is equal to the first clamper threshold value, the incoming level signal (USBIN) is equal to safety threshold
Value, the medium voltage (VMID) is equal to the incoming level signal (USBIN)；The level transmission circuit (101) will be described
Medium voltage (VMID) is used as detection level (USB_SNS) output；
When the medium voltage (VMID) is more than the first clamper threshold value, the incoming level signal (USBIN) exceeds safety threshold
The medium voltage (VMID) is clamped to the first clamper threshold value, the level transmission circuit by value, the clamp circuit (102)
(101) using the medium voltage (VMID) after the clamper as detection level (USB_SNS) output.
3. open-loop voltage detecting system according to claim 1 and 2, it is characterised in that the clamp circuit (102) passes through
In the medium voltage (VMID) and ground between, and connected between ground some diodes in the cut-in voltage (VON), it is right
The medium voltage (VMID) and the cut-in voltage (VON) carry out clamper.
4. open-loop voltage detecting system according to claim 3, it is characterised in that the clamp circuit (102) is by choosing
Diode that logical reverse, positive or its combination is accessed, presets the first clamper threshold value and the second clamper threshold value.
5. open-loop voltage detecting system according to claim 4, it is characterised in that the clamp circuit (102) is according to group
Logical control signal gating is reverse, positive or it combines the diode for accessing, and presets the first clamper threshold value and the second clamper
Threshold value.
6. open-loop voltage detecting system according to claim 1 or 5, it is characterised in that the second clamper threshold value is equal to
The first clamper threshold value and first voltage sum.
7. open-loop voltage detecting system according to claim 6, it is characterised in that the clamp circuit (102) includes choosing
Logical module and clamper module；
Gating module, for the first clamper threshold value according to Combinational Logic Control signal gating and the second clamper threshold value；
Clamper module, clamper is carried out for the first clamper threshold value according to the gating to the medium voltage (VMID), and
The cut-in voltage (VON) is clamped to the second clamper threshold value.
8. open-loop voltage detecting system according to claim 7, it is characterised in that
The clamper module includes the 4th metal-oxide-semiconductor (MN4), the first diode (D1), the second diode (D2), the 3rd diode
(D3), the 4th diode (D4), the 5th diode (D5), the 6th diode (D6)；The diode selects Zener diode；
First diode (D1), the 3rd diode (D3), the 4th diode (D4), the 5th diode (D5), the six or two pole
Pipe (D6) is sequentially connected in series；First diode (D1), the 3rd diode (D3), the 4th diode (D4) are reversely access；Five or two
Pole pipe (D5), the 6th diode (D6) are accessed for positive；The negative pole of the first diode (D1) is used to receive medium voltage (VMID)；
The negative pole of the 6th diode (D6) connects common reference ground；The positive pole of the second diode (D2) connects the negative of the 3rd diode (D3)
Pole；The negative pole of the second diode (D2) connects the source electrode of the 4th metal-oxide-semiconductor (MN4)；The grid of the 4th metal-oxide-semiconductor (MN4) and drain electrode are short
Connect；The drain electrode of the 4th metal-oxide-semiconductor (MN4) is used to receive cut-in voltage (VON)；
Voltage difference between the grid and source electrode of the 4th metal-oxide-semiconductor (MN4) is first voltage；
The gating module includes the first gating switch (MN21), the second gating switch (MN22), the 3rd gating switch (MN23)；
The drain electrode of the first gating switch (MN21) connects the node between the 3rd diode (D3) and the 4th diode (D4),
The source ground of the first gating switch (MN21)；The drain electrode of the second gating switch (MN22) connect the 4th diode (D4) and
Node between 5th diode (D5), the source ground of the second gating switch (MN22)；The leakage of the 3rd gating switch (MN23)
Pole connects the node between the 5th diode (D5) and the 6th diode (D6), and the source electrode of the 3rd gating switch (MN23) connects
Ground；The grid of first gating switch (MN21), the grid of the second gating switch (MN22), the 3rd gating switch (MN23)
Grid is used to receive Combinational Logic Control signal.
9. open-loop voltage detecting system according to claim 8, it is characterised in that level transmission circuit (101) bag
Include transport module and module of releasing；
The transport module includes the first metal-oxide-semiconductor (MN1), the second metal-oxide-semiconductor (MN2)；
First metal-oxide-semiconductor (MN1) source electrode connects the source electrode of the second metal-oxide-semiconductor (MN2), the first metal-oxide-semiconductor (MN1) grid connection second
The grid of metal-oxide-semiconductor (MN2), the drain electrode of the first metal-oxide-semiconductor (MN1) is used to receive incoming level signal (USBIN), the second metal-oxide-semiconductor
(MN2) drain electrode is used to export detection level (USB_SNS), the source electrode of the first metal-oxide-semiconductor (MN1) and the source of the second metal-oxide-semiconductor (MN2)
Node is taken between pole for exporting medium voltage (VMID), the grid of the first metal-oxide-semiconductor (MN1) and the grid of the second metal-oxide-semiconductor (MN2)
Between take node for receiving cut-in voltage (VON)；Electric current and the institute between first metal-oxide-semiconductor (MN1) drain electrode, source electrode
State current in proportion relation of the 4th metal-oxide-semiconductor (MN4) between grid, source electrode；
The module of releasing includes the 3rd metal-oxide-semiconductor (MN3), first resistor (R1)；
The drain electrode of the 3rd metal-oxide-semiconductor (MN3) of one end connection of the first resistor (R1), the source ground of the 3rd metal-oxide-semiconductor (MN3),
The drain electrode of the second metal-oxide-semiconductor (MN2) in the other end connection transport module of first resistor (R1), the grid of the 3rd metal-oxide-semiconductor (MN3) is used
Switch controlling signal (ENB) is enabled in receiving；
First metal-oxide-semiconductor (MN1), the second metal-oxide-semiconductor (MN2), the 3rd metal-oxide-semiconductor (MN3), from low conduction impedance device.
10. the open-loop voltage detecting system according to claim 1 to 2,4 to 5,7 to 9 any claims, its feature exists
In also including cut-in voltage generation circuit (103)；
Cut-in voltage produces circuit (103), and for the medium voltage (VMID) for receiving to be raised into voltage magnitude, producing is used for
The cut-in voltage (VON) of unblocked level transmission circuit (101)；When the incoming level signal (USBIN) disappears, cut-in voltage
Circuit (103) is produced to stop producing cut-in voltage (VON), level transmission circuit (101) is closed, while the flat transmission circuit of vent discharge
(101) electric current of output end.
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| CN2016108874987 | 2016-10-11 | ||
| CN2016211141629 | 2016-10-11 | ||
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| CN201621114162 | 2016-10-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108828296A (en) * | 2018-08-17 | 2018-11-16 | 深圳南云微电子有限公司 | A kind of detection circuit and the contactor electricity-saving appliance comprising the detection circuit |
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010036702A1 (en) * | 2009-10-28 | 2011-05-05 | Intersil Americas Inc., Milpitas | Electrostatic discharge clamp for use in integrated circuit to couple nodes, has voltage threshold circuit triggered to turn-off clam circuit when voltage between nodes decreases to threshold voltage that is less than another voltage |
| CN102307010A (en) * | 2011-09-14 | 2012-01-04 | 深圳市九洲电器有限公司 | Data transmission voltage conversion circuit |
| CN202794314U (en) * | 2012-07-19 | 2013-03-13 | 快捷半导体(苏州)有限公司 | Over-current detection circuit of power switching tube |
| CN103248033A (en) * | 2013-05-09 | 2013-08-14 | 北京大学 | Transient and DC synchronous triggering type power supply clamping ESD protection circuit |
| US20130328610A1 (en) * | 2012-05-31 | 2013-12-12 | Renesas Electronics Corporation | Semiconductor device |
| CN104300952A (en) * | 2014-11-03 | 2015-01-21 | 西安电子科技大学 | Self-adaptive drive circuit for environment-friendly switching mode power supply chip |
| CN105186444A (en) * | 2015-07-27 | 2015-12-23 | 昆山龙腾光电有限公司 | Power supply protection circuit |
| CN206353183U (en) * | 2016-10-11 | 2017-07-25 | 英特格灵芯片(天津)有限公司 | A kind of open-loop voltage detecting system |
-
2017
- 2017-01-10 CN CN201710016282.8A patent/CN106841823B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010036702A1 (en) * | 2009-10-28 | 2011-05-05 | Intersil Americas Inc., Milpitas | Electrostatic discharge clamp for use in integrated circuit to couple nodes, has voltage threshold circuit triggered to turn-off clam circuit when voltage between nodes decreases to threshold voltage that is less than another voltage |
| CN102307010A (en) * | 2011-09-14 | 2012-01-04 | 深圳市九洲电器有限公司 | Data transmission voltage conversion circuit |
| US20130328610A1 (en) * | 2012-05-31 | 2013-12-12 | Renesas Electronics Corporation | Semiconductor device |
| CN202794314U (en) * | 2012-07-19 | 2013-03-13 | 快捷半导体(苏州)有限公司 | Over-current detection circuit of power switching tube |
| CN103248033A (en) * | 2013-05-09 | 2013-08-14 | 北京大学 | Transient and DC synchronous triggering type power supply clamping ESD protection circuit |
| CN104300952A (en) * | 2014-11-03 | 2015-01-21 | 西安电子科技大学 | Self-adaptive drive circuit for environment-friendly switching mode power supply chip |
| CN105186444A (en) * | 2015-07-27 | 2015-12-23 | 昆山龙腾光电有限公司 | Power supply protection circuit |
| CN206353183U (en) * | 2016-10-11 | 2017-07-25 | 英特格灵芯片(天津)有限公司 | A kind of open-loop voltage detecting system |
Non-Patent Citations (1)
| Title |
|---|
| 宁红英;孙旭霞;杨媛;: "一种基于di_C/dt反馈控制的大功率IGBT驱动保护方法" * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108828296A (en) * | 2018-08-17 | 2018-11-16 | 深圳南云微电子有限公司 | A kind of detection circuit and the contactor electricity-saving appliance comprising the detection circuit |
| CN110597344A (en) * | 2019-09-26 | 2019-12-20 | 北京集创北方科技股份有限公司 | Voltage adjusting device, chip and electronic equipment |
| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
| CN113242035B (en) * | 2021-05-08 | 2023-06-02 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
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| CN106841823B (en) | 2023-06-06 |
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