CN206353183U - A kind of open-loop voltage detecting system - Google Patents

Abstract

The utility model discloses a kind of open-loop voltage detecting system, including level transmission circuit, clamp circuit, cut-in voltage generation circuit, Combinational Logic Control circuit；Level transmission circuit is used for the incoming level signal according to reception, produces medium voltage；Cut-in voltage generation circuit produces the level higher than medium voltage as cut-in voltage, for controlling level transmission circuit to turn on；On the other hand, when incoming level signal is less than or equal to secure threshold, clamp circuit medium voltage does not occur clamping action, and medium voltage is equal with input voltage, and level transmission circuit is directly exported medium voltage as detection level；When input voltage is more than default clamper threshold value, clamp circuit is according to the signal of Combinational Logic Control circuit output, medium voltage is clamped to required clamper threshold value, cut-in voltage is clamped to corresponding clamper threshold value simultaneously, while ensureing that electric current is effective between incoming level signal and medium voltage, detection level of the ultra-low loss output in secure threshold.

Description

A kind of open-loop voltage detecting system

Technical field

The utility model is related to circuit signal processing, more particularly to a kind of open-loop voltage detecting system.

Background technology

, can it is necessary to have the load switching circuit of two-way admittance function in the charger device loaded applied to OTG Enough meet power supply to charge to host device, the charging that host device loads OTG when can also realize access OTG loads Implement, when system judges that transmission line connection status is that OTG is loaded also or during power supply adaptor, it is necessary to which one can sense access The detection level of the stable safety of signal, gating control is carried out to two-way admittance load switch；

When USB interface is inserted, the chip pin in external environment condition may be introduced greatly very much can more than chip The high-voltage pulse sustained even surge level, in this case, needs to carry out to the level signal more than secure threshold Clamper, makes host computer system receive only the detection signal of significant level, and clamper isolation is carried out for unsafe high pressure.

The content of the invention

The purpose of this utility model is to provide a kind of open-loop voltage detecting system, realizes having during USB port access load Electrical level judging is imitated, while carrying out clamper to the level signal higher than secure threshold, the same of mark is sensed into level to achieve a butt joint When, the level of main frame is protected.

To achieve the above object, the utility model embodiment provides a kind of open-loop voltage detecting system.The system includes：

Level transmission circuit, for the incoming level signal according to reception, produces and exports medium voltage, and is opening electricity Turned under the control of pressure, detection level of the output in secure threshold；

Clamp circuit, for by medium voltage and cut-in voltage clamper, when the incoming level signal exceeds secure threshold When, medium voltage is clamped to the first clamper threshold value by the clamp circuit, while by the way that cut-in voltage is clamped into the second clamper Threshold value, the size of current between control input level signal and medium voltage.

It is preferred that, the clamp circuit judges described by the way that medium voltage and the first clamper threshold value are compared Whether incoming level signal is in secure threshold；

When the medium voltage is less than the first clamper threshold value, the incoming level signal is in secure threshold, described Level transmission circuit regard the medium voltage as detection level output；

When the medium voltage be equal to the first clamper threshold value when, the incoming level signal be equal to secure threshold, it is described in Between voltage be equal to the incoming level signal；The level transmission circuit regard the medium voltage as detection level output；

When the medium voltage is more than the first clamper threshold value, the incoming level signal exceeds secure threshold, the pincers The medium voltage is clamped to the first clamper threshold value by position circuit, and the level transmission circuit is by the medium voltage after the clamper It is used as detection level output.

It is preferred that, the clamp circuit is by between the medium voltage and ground, and in the cut-in voltage and ground Between connect some diodes, clamper is carried out to the medium voltage and the cut-in voltage.

It is preferred that, the clamp circuit is by gating reverse, positive or its combination access diode, and default first clamps Position threshold value and the second clamper threshold value.

It is preferred that, the clamp circuit is reverse, positive or its combination access according to Combinational Logic Control signal gating Diode, presets the first clamper threshold value and the second clamper threshold value.

It is preferred that, the second clamper threshold value is equal to the first clamper threshold value and first voltage sum.

It is preferred that, the clamp circuit includes gating module and clamper module；

Gating module, for the first clamper threshold value according to Combinational Logic Control signal gating and the second clamper threshold Value；

Clamper module, clamper is carried out to the medium voltage for the first clamper threshold value according to the gating, and will The cut-in voltage is clamped to the second clamper threshold value.

It is preferred that, the clamper module includes the 4th metal-oxide-semiconductor, the first diode, the second diode, the 3rd diode, the Four diodes, the 5th diode, the 6th diode；The diode selects Zener diode；

First diode, the 3rd diode, the 4th diode, the 5th diode, the 6th diode are sequentially connected in series；The One diode, the 3rd diode, the 4th diode are reverse access；5th diode, the 6th diode access to be positive；First The negative pole of diode is used to receive medium voltage；The negative pole of 6th diode is with connecing common reference；The positive pole of second diode connects Connect the negative pole of the 3rd diode；The negative pole of second diode connects the source electrode of the 4th metal-oxide-semiconductor；The grid of 4th metal-oxide-semiconductor and drain electrode Short circuit；The drain electrode of 4th metal-oxide-semiconductor is used to receive cut-in voltage；

Voltage difference between the grid and source electrode of 4th metal-oxide-semiconductor is first voltage；

The gating module includes the first gating switch, the second gating switch, the 3rd gating switch；

Node between drain electrode connection the 3rd diode of first gating switch and the 4th diode, the first gating is opened The source ground of pass；Node between drain electrode connection the 4th diode of second gating switch and the 5th diode, second The source ground of gating switch；Section between drain electrode connection the 5th diode of 3rd gating switch and the 6th diode Point, the source ground of the 3rd gating switch；Grid, the grid of the second gating switch, the 3rd gating of first gating switch The grid of switch is used to receive Combinational Logic Control signal.

It is preferred that, the level transmission circuit includes transport module and module of releasing；

The transport module includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor；

The first metal-oxide-semiconductor source electrode connects the source electrode of the second metal-oxide-semiconductor, and the first metal-oxide-semiconductor grid connects the grid of the second metal-oxide-semiconductor Pole, the drain electrode of the first metal-oxide-semiconductor is used to receive incoming level signal, and the drain electrode of the second metal-oxide-semiconductor is used to export detection level, first Node is taken to be used to export medium voltage, the grid of the first metal-oxide-semiconductor and second between the source electrode of the source electrode of metal-oxide-semiconductor and the second metal-oxide-semiconductor Node is taken to be used to receive cut-in voltage between the grid of metal-oxide-semiconductor；Electric current between first metal-oxide-semiconductor drain electrode, source electrode with it is described Current in proportion relation between the 4th metal-oxide-semiconductor grid, source electrode；

The module of releasing includes the 3rd metal-oxide-semiconductor, first resistor；

The drain electrode of the 3rd metal-oxide-semiconductor of one end connection of the first resistor, the source ground of the 3rd metal-oxide-semiconductor, first resistor The drain electrode of second metal-oxide-semiconductor in other end connection transport module, the grid of the 3rd metal-oxide-semiconductor, which is used to receive, enables switch controlling signal；

First metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, from low conduction impedance device.

It is preferred that, described open-loop voltage detecting system, it is characterised in that also including cut-in voltage generation circuit；

Cut-in voltage generation circuit, for the medium voltage of reception to be raised into voltage magnitude, is produced for opening electricity The cut-in voltage of flat transmission circuit；When the incoming level blackout, cut-in voltage generation circuit, which stops producing, opens electricity Pressure, level transmission circuit is closed, while the electric current of the flat transmission circuit output end of vent discharge.

The open-loop voltage detecting system provided using the utility model, because the utility model design is in level transmission circuit When, included transport module and module of releasing, the metal-oxide-semiconductor used is low conduction impedance device, such as preferable NDMOS Pipe, therefore when incoming level signal is in secure threshold, transport module can be realized and export it with ultra-low loss, work as input Level signal exceed secure threshold when, transport module using the medium voltage after clamp circuit clamper as detection level, equally Exported with ultra-low loss, it is ensured that detection level follows the change of incoming level signal, in addition, module of releasing is responsible for closing in system When, by the current drain in level transmission circuit, in order to avoid on producing influence using the outer application system for detecting level.

On the other hand, in order to realize detection level of the output in secure threshold, the utility model is in design clamper electricity Lu Shi, by some diodes of connecting, to middle voltage clamping, when incoming level signal is in secure threshold, clamp circuit Do not act, level transmission circuit using equal to the medium voltage of incoming level signal as detection level, it is direct with ultra-low loss Output, when incoming level signal exceeds secure threshold, i.e., when medium voltage exceeds secure threshold, clamp circuit is by medium voltage It is clamped to the first clamper threshold value, it is ensured that the detection level of level transmission circuit output is safe, stabilization, is operated in safety threshold Level in value.

In addition, after medium voltage is clamped, certain voltage difference occurs between incoming level signal and medium voltage, Excessive electric current occurs in the drain-source interpolar of the first metal-oxide-semiconductor in transport module, first to avoid the electric current from causing the first metal-oxide-semiconductor Damage, second when the utility model is detecting different incoming level signals, the electric current can influence Detection results, it is therefore desirable to The electric current (electric current i.e. between incoming level signal and medium voltage) of the drain-source interpolar of first metal-oxide-semiconductor is controlled, therefore, Cut-in voltage is clamped to the second clamper threshold value by this clamp circuit while medium voltage is clamped into the first clamper threshold value, Make the 4th metal-oxide-semiconductor and the first MOS formation current mirrors, and then can be by controlling the electric current between the 4th metal-oxide-semiconductor hourglass source electrode, by first The control of metal-oxide-semiconductor drain-source interpolar is in required and effective scope, it is ensured that the safety of level transmission circuit, is further ensured that defeated The detection level gone out is safe, stabilization, is operated in the level in secure threshold.

In addition, to realize according to different clamper demands, this clamp circuit in series diode, by reversely accessing and The diode of forward direction access varying number, when the diode conducts, is hit by the reverse of each diode for being superimposed respective numbers Voltage and forward conduction voltage are worn, and then realizes default clamper threshold value on demand；And to improve the convenience of clamper threshold value selection, The utility model can be exported according to the various combination of Combinational Logic Control signal, you can the gating module gating of control clamp circuit Required clamper threshold value.

Brief description of the drawings

Fig. 1 is a kind of structural representation for open-loop voltage detecting system that the utility model embodiment one is provided；

Fig. 2 is the electrical block diagram of level transmission circuit；

Fig. 3 is the electrical block diagram of clamp circuit；

Fig. 4 is the electrical block diagram of cut-in voltage generation circuit；

Fig. 5 is the electrical block diagram after cut-in voltage generation circuit is improved in Fig. 3.

Embodiment

Below by drawings and examples, the technical solution of the utility model is described in further detail.

Fig. 1 is a kind of structural representation for open-loop voltage detecting system that the utility model embodiment one is provided.Such as Fig. 1 institutes Show, a kind of open-loop voltage detecting system that the utility model is provided, including level transmission circuit 101, clamp circuit 102, unlatching Voltage generation circuit 103, Combinational Logic Control circuit 104.

Level transmission circuit 101 produces according to the incoming level signal USBIN of reception and exports middle voltage VM ID；When When incoming level signal USBIN is in secure threshold, level transmission circuit 101 regard middle voltage VM ID as detection level USB_SNS is directly exported；When incoming level signal USBIN exceeds secure threshold, level transmission circuit 101 is by after clamper Between voltage VMID as detection level USB_SNS exported；When incoming level signal USBIN disappears, level transmission circuit 101 close, while the electric current of the flat output end of transmission circuit 101 of vent discharge.

Cut-in voltage generation circuit 103 produces cut-in voltage VON, for controlling electricity according to the middle voltage VM ID of reception Flat transmission circuit 101 is turned on；When incoming level signal USBIN disappears, cut-in voltage generation circuit 103, which stops producing, opens electricity VON is pressed, level transmission circuit 101 is closed.

Clamp circuit 102 receives middle voltage VM ID, when incoming level signal USBIN exceeds secure threshold, clamper electricity Middle voltage VM ID is clamped to the first clamper threshold value by road 102, while cut-in voltage VON is clamped into the second clamper threshold value.

Combinational Logic Control circuit 104 is produced and output combinational logic control signal, and the control gating of clamp circuit 102 needs The first clamper threshold value and the second clamper threshold value.

Level transmission circuit 101 produces middle voltage VM ID according to the incoming level signal USBIN of reception, and by centre Voltage VMID is exported to clamp circuit 102 and cut-in voltage generation circuit 103 respectively；Cut-in voltage generation circuit 103 is in difference Under clock signal clkn and clkp driving, middle voltage VM ID is raised into a clock amplitude, produced for controlling level to pass The cut-in voltage VON that transmission of electricity road 101 is turned on；On the other hand, clamp circuit 102 is received after middle voltage VM ID, when middle electricity When pressing VMID in secure threshold, to medium voltage VMID clamping action does not occur for clamp circuit 102, now level transmission electricity Road 101 is directly exported middle voltage VM ID as detection level USB_SNS；When medium voltage VMID exceeds secure threshold, The Combinational Logic Control signal that clamp circuit 102 is exported according to Combinational Logic Control circuit 104, middle voltage VM ID is clamped to First clamper threshold value, level transmission circuit 101 is exported the middle voltage VM ID after clamper as detection level USB_SNS； In addition, cut-in voltage VON is clamped to by clamp circuit 102 while middle voltage VM ID is clamped into the first clamper threshold value Second clamper threshold value, is further ensured that level transmission circuit 101 stably exports detection level USB_SNS；When incoming level letter When number USBIN disappears, cut-in voltage generation circuit 103 stops output and opens electricity under the control of the enable signal of applications VON is pressed, now level transmission circuit 101 is closed, while by the current drain of the output end of level transmission circuit 101.

Fig. 2 is the electrical block diagram of level transmission circuit 101.As shown in Fig. 2 level transmission circuit 101 includes passing Defeated module and module of releasing.

Transport module includes metal-oxide-semiconductor MN1, metal-oxide-semiconductor MN2.

Wherein, metal-oxide-semiconductor MN1 source electrodes connection metal-oxide-semiconductor MN2 source electrode, metal-oxide-semiconductor MN1 grids connection metal-oxide-semiconductor MN2 grid, The drain electrode that metal-oxide-semiconductor MN1 drain electrode is used to receive incoming level signal USBIN, metal-oxide-semiconductor MN2 is used to export detection level USB_ Node is taken to be used to export middle voltage VM ID, metal-oxide-semiconductor MN1 grid between SNS, metal-oxide-semiconductor MN1 source electrode and metal-oxide-semiconductor MN2 source electrode Node is taken to be used to receive cut-in voltage VON between pole and metal-oxide-semiconductor MN2 grid.

Wherein, module of releasing includes metal-oxide-semiconductor MN3, resistance R1.Resistance R1 one end connection metal-oxide-semiconductor MN3 drain electrode, metal-oxide-semiconductor Metal-oxide-semiconductor MN2 drain electrode in MN3 source ground, resistance R1 other end connection transport module, metal-oxide-semiconductor MN3 grid is used to connect Receive and enable switch controlling signal ENB.

Above-mentioned metal-oxide-semiconductor MN1, metal-oxide-semiconductor MN2, metal-oxide-semiconductor MN3, from low conduction impedance device, the preferred NDMOS of the present embodiment Pipe, realizes incoming level signal USBIN ultra-low loss transmission, it is ensured that detection level USB_SNS follows incoming level signal USBIN change.

Transport module produces middle voltage VM ID, and export respectively to clamper according to the incoming level signal USBIN of reception Circuit 102 and cut-in voltage generation circuit 103；The cut-in voltage VON's that transport module is exported in cut-in voltage generation circuit 103 Control is lower to be turned on, and output stabilization, the safety detection level USB_SNS under the control of clamp circuit 102；Work as transport module During closing, module of releasing is in the case where applications enable signal ENB control by the current drain of transport module output end.

Because in the present embodiment, metal-oxide-semiconductor MN1 is switching tube, therefore, when the USBIN that transport module is received is in safety threshold When in value, the middle voltage VM ID of transport module output is equal to incoming level signal USBIN, and now transport module is by medium voltage VMID is directly exported as detection level USB_SNS with ultra-low loss；When incoming level signal USBIN exceeds secure threshold, Middle voltage VM ID is clamped to the first clamper threshold value by clamp circuit 102, and transport module makees the middle voltage VM ID after clamper Exported for detection level USB_SNS with ultra-low loss；When incoming level signal USBIN disappears, cut-in voltage generation circuit 103 Stop output cut-in voltage VON, and then closing transmission module under the control of applications, module of now releasing is enabling switch Turned under control signal ENB control, by the current drain of transport module output end.

Fig. 3 is the electrical block diagram of clamp circuit.As shown in figure 3, clamp circuit 102 includes clamper module and gating Module.

Clamper module includes metal-oxide-semiconductor MN4, diode D1, diode D2, diode D3, diode D4, diode D5, two Pole pipe D6；Metal-oxide-semiconductor MN4 manages for NDMOS.The diode selects Zener diode.

Wherein, diode D1, diode D3, diode D4, diode D5, diode D6 are sequentially connected in series；Diode D1, two Pole pipe D3, diode D4 are reverse access；Diode D5, diode D6 access to be positive；Diode D1 negative pole is used to receive Middle voltage VM ID；Diode D6 negative pole is with connecing common reference；Diode D2 cathode connecting diode D3 negative pole；Two poles Pipe D2 negative pole connection metal-oxide-semiconductor MN4 source electrode；Metal-oxide-semiconductor MN4 grid and drain electrode short circuit；Metal-oxide-semiconductor MN4 drain electrode connection level Metal-oxide-semiconductor MN1 grid in transmission circuit 101, receives cut-in voltage VON；Metal-oxide-semiconductor MN4 and metal-oxide-semiconductor MN1 formation current mirrors.

Gating module includes gating switch MN21, gating switch MN22, gating switch MN23.The gating switch is selected NMOS tube.

Wherein, gating switch MN21 grid is used to receive switch control level Vclamp1, gating switch MN21 drain electrode The node between diode D3 and diode D4 is connected, gating switch MN21 source electrode is with connecing common reference；Gating switch MN22 Grid be used for receive switch control level Vclamp2, gating switch MN22 drain electrode connection diode D4 and diode D5 it Between node, gating switch MN22 source electrode is with connecing common reference；Gating switch MN23 grid is used to receive switch control electricity Node between flat Vclamp1, gating switch MN23 drain electrode connection diode D5 and diode D6, gating switch MN23 source Pole is with connecing common reference.

Gating module is according to switch control level Vclamp1, switch control level Vclamp2, switch control level Vclamp3 various combination output, gates the diode of respective numbers, so that default first clamper threshold value and the second clamper threshold Value；First clamper threshold value is equal to incoming level USBIN secure threshold；Second clamper threshold value is equal to the first clamper threshold value and first Voltage sum, wherein, first voltage is the voltage difference VGS between metal-oxide-semiconductor MN4 grids and source electrode.

Clamper module is compared the middle voltage VM ID of reception with the first clamper threshold value, when medium voltage VMID is not more than During one clamper threshold value, to medium voltage VMID and cut-in voltage VON clamping action does not occur for clamp circuit 102；When middle electricity When pressing VMID more than the first clamper threshold value, middle voltage VM ID is clamped to the first clamper threshold value by clamp circuit 102.

After to medium voltage VMID clampers, had between incoming level signal USBIN and middle voltage VM ID certain Pressure difference, metal-oxide-semiconductor MN1 can be caused to drain and excessive electric current is produced between source electrode (i.e. incoming level signal USBIN is electric to centre Press VMID electric current), metal-oxide-semiconductor MN1 damage can be caused, and when requiring to detect the incoming level signal USBIN of particular value, The electric current that metal-oxide-semiconductor MN1 drains between source electrode, otherwise will influence incoming level signal USBIN no more than corresponding current value Detection, and detection level USB_SNS output；

Therefore, while to medium voltage VMID clampers, cut-in voltage VON to be clamped to the second required clamper threshold Value；Cut-in voltage VON is after clamper, metal-oxide-semiconductor MN4 and metal-oxide-semiconductor MN1 formation current mirror relationships, metal-oxide-semiconductor MN4 drain electrode, source electrode it Between electric current and metal-oxide-semiconductor MN1 drain electrode, source electrode between electric current then there is stable proportionate relationship, therefore can be according to the ratio Relation, by controlling the electric current between metal-oxide-semiconductor MN4 drain electrode and source electrode, by the electric current between metal-oxide-semiconductor MN1 drain electrode and source electrode Control is required, and in effective working range, for example：In the present embodiment, the electric current between metal-oxide-semiconductor MN4 drain electrode, source electrode The Proportionality design of the electric current between drain electrode, source electrode with metal-oxide-semiconductor MN1 is：1:100, when by between metal-oxide-semiconductor MN4 drain electrode, source electrode Current control when being 10uA, the electric current 1mA between metal-oxide-semiconductor MN1 drain electrode, source electrode；In other application, metal-oxide-semiconductor MN4 leakage The proportionate relationship of electric current between the drain electrode of electric current and metal-oxide-semiconductor MN1 between pole, source electrode, source electrode, difference can be carried out according to demand Adjustment.

The following is middle voltage VM ID and cut-in voltage VON clamper process：

First, the first clamper threshold value and the second clamper threshold value are preset.Because technique is different, the breakdown reverse voltage of diode Generally 5V-7V, forward conduction voltage is generally 0.5V-0.7V；The preferred diode of the present embodiment, breakdown reverse voltage is all 6V, forward voltage is all 0.6V；When gating module according to switch control level Vclamp1, switch control level Vclamp2, open Control level Vclamp3 various combination output is closed, the reverse access diode and positive access diode of respective numbers is gated, So as to set the first clamper threshold value, the second clamper threshold value；The preset procedures of various first clamper threshold values and the second clamper threshold value are：

When switch control level Vclamp1 to be that control level Vclamp2 be low, switchs and controls level Vclamp3 for low, switch For it is low when, gating switch MN21 disconnect, gating switch MN22 disconnect, gating switch MN23 disconnect, diode D1, diode D2, Diode D3, diode D4, diode D5, diode D6 are both turned on, the first clamper threshold value：6V*3+0.6V=19.2V；Second Clamper threshold value：19.2V+VGS, VGS are that metal-oxide-semiconductor MN4 gate-source voltages are poor, i.e. the value of first voltage；

When switch control level Vclamp1 to be that control level Vclamp2 be low, switchs and controls level Vclamp3 for low, switch For it is high when, gating switch MN21 disconnect, gating switch MN22 disconnect, gating switch MN23 conducting, diode D1, diode D2, Diode D3, diode D4, diode D5 are both turned on, and diode D6 is short-circuited, the first clamper threshold value：6V*3+0.6V*1= 18.6V；Second clamper threshold value：18.6V+VGS；

When switch control level Vclamp1 to be that control level Vclamp2 be high, switchs and controls level Vclamp3 for low, switch For it is low when, gating switch MN21 disconnect, gating switch MN22 conducting, gating switch MN23 disconnect, diode D1, diode D2, Diode D3, diode D4 are both turned on, and diode D5, diode D6 are short-circuited, the first clamper threshold value：6V*3=18V；Second pincers Position threshold value：18V+VGS, VGS are the value of first voltage；

When switch control level Vclamp1 to be that control level Vclamp2 be low, switchs and controls level Vclamp3 for high, switch For it is low when, gating switch MN21 conducting, gating switch MN22 disconnect, gating switch MN23 disconnect, diode D1, diode D2, Diode D3 is turned on, and diode D4, diode D5, diode D6 are short-circuited, the first clamper threshold value：6V*2=12V；Second clamper Threshold value：12V+VGS.

In other practical applications, clamp circuit 102 can use more diodes according to the actual requirements, set more Clamper threshold value is for selection.

Default first clamper threshold value, the second clamper threshold value, for example：First clamper threshold value is：During 6V*3+0.6V=19.2V； Second clamper threshold value is：19.2V+VGS；

When the middle voltage VM ID that clamper module is received is less than 19.2V, diode D1, diode D2, diode D3, two Pole pipe D4, diode D5, diode D6 are not acted, and level transmission circuit 101 regard middle voltage VM ID as detection level USB_SNS is directly exported；

When the middle voltage VM ID that clamper module is received is equal to 19.2V, diode D1, diode D3, diode D4, two Pole pipe D5, diode D6 are turned on, and now middle voltage VM ID value is exactly clamper threshold value, similarly, level transmission circuit 101 Directly exported middle voltage VM ID as detection level USB_SNS；

When the middle voltage VM ID that clamper module is received is more than 19.2V, diode D1, diode D2, diode D3, two Pole pipe D4, diode D5, diode D6 are turned on, and middle voltage VM ID is clamped into 19.2V, meanwhile, cut-in voltage VON is clamped Position is to 19.2V+VGS, and the electric current between now metal-oxide-semiconductor MN4 drain electrodes and source electrode is 20uA, between metal-oxide-semiconductor MN1 drain electrodes and source electrode Electric current is 2mA.

Fig. 4 is the electrical block diagram of cut-in voltage generation circuit 103.Due to the transmission in level transmission circuit 101 Module is switched using NDMOS as conducting, it is necessary to which the current potential of grid is higher than source voltage, and incoming level signal USBIN is outer The ceiling voltage that portion is provided, in order that the transport module conducting in level transmission circuit 101, metal-oxide-semiconductor MN1 and metal-oxide-semiconductor MN2 grid Pole need to obtain higher voltage, for example：During USBIN=10V, then the grid that metal-oxide-semiconductor MN1 and metal-oxide-semiconductor MN2 needs connects 15V electricity Pressure could drive, therefore the cut-in voltage generation circuit 103 of the present embodiment need to use the frame mode of charge pump.

As shown in figure 4, cut-in voltage generation circuit 103 include metal-oxide-semiconductor MN5, metal-oxide-semiconductor MN6, metal-oxide-semiconductor MN7, metal-oxide-semiconductor MN8, Metal-oxide-semiconductor MN9, metal-oxide-semiconductor MP1, metal-oxide-semiconductor MP2, electric capacity C1, electric capacity C2.

Electric capacity C1 one end is used to receive clock signal clkn, electric capacity C1 other end connection metal-oxide-semiconductor MN5 drain electrode, MOS Pipe MP1 drain electrode, metal-oxide-semiconductor MN6 grid, metal-oxide-semiconductor MP2 grid and metal-oxide-semiconductor MN7 drain electrode, metal-oxide-semiconductor MN7 source ground； It is a pair of differential clocks letters that electric capacity C2 one end, which is used to receive clock signal clkp, clock signal clkp and clock signal clkn, Number, electric capacity C2 other end connection metal-oxide-semiconductor MP1 grid, metal-oxide-semiconductor MP2 drain electrode, metal-oxide-semiconductor MN5 grid, metal-oxide-semiconductor MN6 Drain electrode and metal-oxide-semiconductor MN8 drain electrode, metal-oxide-semiconductor MN8 source ground, metal-oxide-semiconductor MN5 source electrode connection metal-oxide-semiconductor MN6 source electrode, MOS Node is taken to be used to receive middle voltage VM ID, metal-oxide-semiconductor MP1 source electrode connection between pipe MN5 source electrode and metal-oxide-semiconductor MN6 source electrode The drain electrode of metal-oxide-semiconductor MP2 source electrode and metal-oxide-semiconductor MN9, metal-oxide-semiconductor MN9 drain electrode is used to export cut-in voltage VON, metal-oxide-semiconductor MN7 grid Pole, metal-oxide-semiconductor MN8 grid, metal-oxide-semiconductor MN9 grid are turned on by switch controlling signal ENB controls are enabled.

Cut-in voltage generation circuit 103 is received after middle voltage VM ID, in differential clock signal clkn and clkp driving Lower work.

Clkn and clkp is two clock signals of opposite in phase.When clkn is low level, and clkp is high, metal-oxide-semiconductor MN5 With metal-oxide-semiconductor MP2 conductings, metal-oxide-semiconductor MN5 drain voltages are equal to VMID, electric capacity C1 are charged (until anode is changed into VMID), simultaneously Metal-oxide-semiconductor MP2 drain voltage is equal to VON (exporting).When clkn high level, when clkp is low, metal-oxide-semiconductor MN6 and metal-oxide-semiconductor MP1 Conducting, while metal-oxide-semiconductor MN6 drain electrode (i.e. metal-oxide-semiconductor MP2 drain electrode) voltage is equal to VMID, to electric capacity C2 chargings (until anode becomes For VMID), while metal-oxide-semiconductor MP1 drain electrode (i.e. metal-oxide-semiconductor MN5 drain electrodes) voltages are equal to VON (exporting).

Therefore, when clkn is changed into high level from low level (i.e. when clkp is changed into low level from high level), metal-oxide-semiconductor MN6 Conducting, the voltage of electric capacity C1 anodes is increased to VMID+VCLK from VMID, now, metal-oxide-semiconductor MP1 conductings, therewith cut-in voltage VON Also it is increased to VMID+VCLK from VMID；

When clkp is changed into high level from low level (i.e. when clkn is changed into low level from high level), metal-oxide-semiconductor MN5 conductings, The voltage of electric capacity C2 anodes is increased to VMID+VCLK from VMID, now, metal-oxide-semiconductor MP2 conducting, therewith cut-in voltage VON also from VMID is increased to VMID+VCLK.

By above procedure, clock signal clkn and clkp low and high level back and forth switch, and make cut-in voltage generation circuit 103 produce stable, higher than incoming level signal USBIN cut-in voltage VON, for switching control level transmission circuit 101 Conducting.

When incoming level signal USBIN disappears, metal-oxide-semiconductor MN7, metal-oxide-semiconductor MN8, metal-oxide-semiconductor MN9 are enabling switch control Turned under signal ENB control, clock signal clkn is grounded through metal-oxide-semiconductor MN7, clock signal clkp is grounded through metal-oxide-semiconductor MN8, MOS Pipe MN9 is by the current drain in cut-in voltage generation circuit 103, and cut-in voltage generation circuit 103 stops output cut-in voltage VON, level transmission circuit 101 is also accordingly turned off.

For ease of realizing the selection of a variety of first clamper threshold values, the second clamper threshold value, the Combinational Logic Control shown in Fig. 1 Circuit 104, can produce the Combinational Logic Control signal that level is controlled comprising multiple switch according to the demand of clamp circuit 102；This In embodiment, the Combinational Logic Control signal that Combinational Logic Control circuit 104 is produced includes switch control level Vclamp1, opened Close control level Vclamp2, switch control level Vclamp3.

Represent low level with 0,1 represents high level, then switch control level Vclamp1, switch control level Vclamp2, Switch control level Vclamp3 combination Vclamp1/Vclamp2/Vclamp3 has：000、001、010、011、100、 101、110、111.According to the actual annexation of clamp circuit 102, Combinational Logic Control signal 100,101,110,111 is set Clamper threshold value be all 12V, therefore be equivalent, thus only take it is 100,101,110,111 one of as output, together Sample, 010,011 is equivalent, and the clamper threshold value of setting is all 18V, therefore selection 010 or 011 is used as output.

In other practical applications, Combinational Logic Control circuit 104 can be produced by more switch control electricity according to demand The flat Combinational Logic Control signal combined.

Fig. 5 is the electrical block diagram after cut-in voltage generation circuit 103 is improved.As shown in figure 5, by each Individual high-voltage path accesses protective resistance, obtain there is high voltage nodes protective effect and high service life is longer and reliability more High cut-in voltage generation circuit.

The protective resistance includes resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11 and resistance R12.

Wherein, electric capacity C1 one end is used to receive clock signal clkn, the electric capacity C1 other end and metal-oxide-semiconductor MN7 drain electrode Between series resistance R2, resistance R3, series resistance R4, resistance R5 between metal-oxide-semiconductor MN5 drain electrode and metal-oxide-semiconductor MP1 drain electrode, electricity The node hindered between node and resistance R4, resistance R5 between R2, resistance R3 is connected；Electric capacity C2 one end is used to receive clock letter Number clkp, series resistance R10, resistance R11 between the electric capacity C2 other ends and metal-oxide-semiconductor MN8 drain electrode, metal-oxide-semiconductor MN6 drain electrode and Series resistance R8, resistance R9 between metal-oxide-semiconductor MP2 drain electrode, node and resistance R10, resistance R11 between resistance R8, resistance R9 Between node connection, resistance R6 one end connection metal-oxide-semiconductor MN5 source electrode and metal-oxide-semiconductor MN6 source electrode, the resistance R6 other end For receiving middle voltage VM ID, resistance R7 one end connects metal-oxide-semiconductor MP1 source electrode and metal-oxide-semiconductor MP2 source electrode, resistance R7's Series resistance R12 between the other end and metal-oxide-semiconductor MN9 drain electrode, the node between resistance R7 and resistance R12, which is used to export, opens electricity Press VON.

Above-described embodiment, is entered to the purpose of this utility model, technical scheme and beneficial effect One step is described in detail, be should be understood that and be the foregoing is only embodiment of the present utility model, is not used to limit Fixed protection domain of the present utility model, all any modifications within spirit of the present utility model and principle, made, is equally replaced Change, improve, should be included within protection domain of the present utility model.

Claims (10)

1. a kind of open-loop voltage detecting system, it is characterised in that including：

Level transmission circuit (101), for the incoming level signal (USBIN) according to reception, produces and exports medium voltage (VMID), and under cut-in voltage (VON) control turn on, detection level (USB_SNS) of the output in secure threshold；

Clamp circuit (102), for by medium voltage (VMID) and cut-in voltage (VON) clamper, when the incoming level signal (USBIN) when exceeding secure threshold, medium voltage (VMID) is clamped to the first clamper threshold value by the clamp circuit (102), together When by the way that cut-in voltage (VON) is clamped into the second clamper threshold value, control input level signal (USBIN) and medium voltage (VMID) size of current between.

2. open-loop voltage detecting system according to claim 1, it is characterised in that the clamp circuit (102) is by inciting somebody to action Medium voltage (VMID) and the first clamper threshold value are compared, and judge whether the incoming level signal (USBIN) is in In secure threshold；

When the medium voltage (VMID) is less than the first clamper threshold value, the incoming level signal (USBIN) is in safety threshold In value, the level transmission circuit (101) exports the medium voltage (VMID) as detection level (USB_SNS)；

When the medium voltage (VMID) is equal to the first clamper threshold value, the incoming level signal (USBIN) is equal to safety threshold Value, the medium voltage (VMID) is equal to the incoming level signal (USBIN)；The level transmission circuit (101) will be described Medium voltage (VMID) is used as detection level (USB_SNS) output；

When the medium voltage (VMID) is more than the first clamper threshold value, the incoming level signal (USBIN) exceeds safety threshold The medium voltage (VMID) is clamped to the first clamper threshold value, the level transmission circuit by value, the clamp circuit (102) (101) exported the medium voltage (VMID) after the clamper as detection level (USB_SNS).

3. open-loop voltage detecting system according to claim 1 or 2, it is characterised in that the clamp circuit (102) passes through In the medium voltage (VMID) between ground, and connected between ground some diodes in the cut-in voltage (VON), it is right The medium voltage (VMID) and the cut-in voltage (VON) carry out clamper.

4. open-loop voltage detecting system according to claim 3, it is characterised in that the clamp circuit (102) passes through choosing Logical reverse, positive or its combination access diode, presets the first clamper threshold value and the second clamper threshold value.

5. open-loop voltage detecting system according to claim 4, it is characterised in that the clamp circuit (102) is according to group Logical control signal gating is reverse, positive or it combines the diode accessed, presets the first clamper threshold value and the second clamper Threshold value.

6. open-loop voltage detecting system according to claim 1 or 5, it is characterised in that the second clamper threshold value is equal to The first clamper threshold value and first voltage sum.

7. open-loop voltage detecting system according to claim 6, it is characterised in that the clamp circuit (102) includes choosing Logical module and clamper module；

Gating module, for the first clamper threshold value according to Combinational Logic Control signal gating and the second clamper threshold value；

Clamper module, clamper is carried out to the medium voltage (VMID) for the first clamper threshold value according to the gating, and The cut-in voltage (VON) is clamped to the second clamper threshold value.

8. open-loop voltage detecting system according to claim 7, it is characterised in that

The clamper module includes the 4th metal-oxide-semiconductor (MN4), the first diode (D1), the second diode (D2), the 3rd diode (D3), the 4th diode (D4), the 5th diode (D5), the 6th diode (D6)；The diode selects Zener diode；

First diode (D1), the 3rd diode (D3), the 4th diode (D4), the 5th diode (D5), the six or two pole Pipe (D6) is sequentially connected in series；First diode (D1), the 3rd diode (D3), the 4th diode (D4) are reverse access；Five or two Pole pipe (D5), the 6th diode (D6) access to be positive；The negative pole of first diode (D1) is used to receive medium voltage (VMID)； The negative pole of 6th diode (D6) is with connecing common reference；The positive pole of second diode (D2) connects the negative of the 3rd diode (D3) Pole；The negative pole of second diode (D2) connects the source electrode of the 4th metal-oxide-semiconductor (MN4)；The grid of 4th metal-oxide-semiconductor (MN4) and drain electrode are short Connect；The drain electrode of 4th metal-oxide-semiconductor (MN4) is used to receive cut-in voltage (VON)；

Voltage difference between the grid and source electrode of 4th metal-oxide-semiconductor (MN4) is first voltage；

The gating module includes the first gating switch (MN21), the second gating switch (MN22), the 3rd gating switch (MN23)；

The drain electrode of first gating switch (MN21) connects the node between the 3rd diode (D3) and the 4th diode (D4), The source ground of first gating switch (MN21)；The drain electrode of second gating switch (MN22) connect the 4th diode (D4) and Node between 5th diode (D5), the source ground of the second gating switch (MN22)；The leakage of 3rd gating switch (MN23) Pole connects the node between the 5th diode (D5) and the 6th diode (D6), and the source electrode of the 3rd gating switch (MN23) connects Ground；The grid of first gating switch (MN21), the grid of the second gating switch (MN22), the 3rd gating switch (MN23) Grid is used to receive Combinational Logic Control signal.

9. open-loop voltage detecting system according to claim 8, it is characterised in that level transmission circuit (101) bag Include transport module and module of releasing；

The transport module includes the first metal-oxide-semiconductor (MN1), the second metal-oxide-semiconductor (MN2)；

First metal-oxide-semiconductor (MN1) source electrode connects the source electrode of the second metal-oxide-semiconductor (MN2), the first metal-oxide-semiconductor (MN1) grid connection second The grid of metal-oxide-semiconductor (MN2), the drain electrode of the first metal-oxide-semiconductor (MN1) is used to receive incoming level signal (USBIN), the second metal-oxide-semiconductor (MN2) drain electrode is used to export detection level (USB_SNS), the source electrode of the first metal-oxide-semiconductor (MN1) and the source of the second metal-oxide-semiconductor (MN2) Node is taken to be used to export medium voltage (VMID), the grid of the first metal-oxide-semiconductor (MN1) and the grid of the second metal-oxide-semiconductor (MN2) between pole Between take node be used for receive cut-in voltage (VON)；Electric current and the institute between first metal-oxide-semiconductor (MN1) drain electrode, source electrode State the current in proportion relation between the 4th metal-oxide-semiconductor (MN4) grid, source electrode；

The module of releasing includes the 3rd metal-oxide-semiconductor (MN3), first resistor (R1)；

The drain electrode of the 3rd metal-oxide-semiconductor (MN3) of one end connection of the first resistor (R1), the source ground of the 3rd metal-oxide-semiconductor (MN3), The drain electrode of second metal-oxide-semiconductor (MN2) in the other end connection transport module of first resistor (R1), the grid of the 3rd metal-oxide-semiconductor (MN3) is used Switch controlling signal (ENB) is enabled in receiving；

First metal-oxide-semiconductor (MN1), the second metal-oxide-semiconductor (MN2), the 3rd metal-oxide-semiconductor (MN3), from low conduction impedance device.

10. the open-loop voltage detecting system according to claim 1 to 2,4 to 5,7 to 9 any claims, its feature exists In, in addition to cut-in voltage generation circuit (103)；

Cut-in voltage generation circuit (103), for the medium voltage (VMID) of reception to be raised into voltage magnitude, producing is used for The cut-in voltage (VON) of unblocked level transmission circuit (101)；When the incoming level signal (USBIN) disappears, cut-in voltage Generation circuit (103) stops producing cut-in voltage (VON), and level transmission circuit (101) is closed, while the flat transmission circuit of vent discharge (101) electric current of output end.