CN107331660B - Electrostatic discharge clamping circuit - Google Patents

Electrostatic discharge clamping circuit Download PDF

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Publication number
CN107331660B
CN107331660B CN201710455287.0A CN201710455287A CN107331660B CN 107331660 B CN107331660 B CN 107331660B CN 201710455287 A CN201710455287 A CN 201710455287A CN 107331660 B CN107331660 B CN 107331660B
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electrostatic discharge
static electricity
switch
discharge transistor
transistor
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CN201710455287.0A
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Chinese (zh)
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CN107331660A (en
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吕斌
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上海华虹宏力半导体制造有限公司
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Publication of CN107331660A publication Critical patent/CN107331660A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The invention discloses an electrostatic discharge clamping circuit, comprising: an electrostatic detection circuit, an electrostatic discharge circuit and a charge pump; the electrostatic discharge circuit comprises a first electrostatic discharge transistor connected between the IO port and the ground; the output end of the charge pump is connected with the grid electrode of the first electrostatic discharge transistor; the output end of the static electricity detection circuit is connected with the input end of the charge pump; the output end of the static electricity detection circuit is also connected with the control end of a first switch, and the first switch is connected between the IO port and the grid electrode of the first static electricity discharge transistor; under the state that the electrostatic discharge event occurs, the charge pump stops working, the first switch is opened, and the first electrostatic discharge transistor is conducted to realize electrostatic discharge; under the normal working state of the chip, the charge pump works and the output voltage is connected to the grid electrode of the first electrostatic discharge transistor to enable the first electrostatic discharge transistor to be in a deep closed state, so that the leakage of the first electrostatic discharge transistor in an off state is reduced. The invention can reduce power consumption.

Description

Electrostatic discharge clamping circuit

Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to an electrostatic discharge (ESD) clamp circuit.

Background

As shown in fig. 1, a circuit diagram of a conventional electrostatic discharge clamping circuit is shown, and the conventional electrostatic discharge clamping circuit includes: an electrostatic detection circuit 101 and an electrostatic discharge circuit 102.

The static electricity detection circuit 101 is arranged between an IO port of the chip and the ground, and is used for detecting static electricity appearing at the IO port; the voltage at the IO port in fig. 1 is denoted by VDDIO.

The static electricity detection circuit 101 comprises a resistor R101 and a capacitor C101 which are connected in series between an IO port and the ground, a detection voltage V101 is formed at the connection position of the resistor R101 and the capacitor C101, and an output Signal, namely an electrostatic discharge Signal ESD Signal, is formed after the detection voltage V101 passes through three inverters. In fig. 1, three inverters are CMOS inverters, a first CMOS inverter is composed of an NMOS transistor MN101 and a PMOS transistor MP101, a second CMOS inverter is composed of an NMOS transistor MN102 and a PMOS transistor MP102, and a third CMOS inverter is composed of an NMOS transistor MN103 and a PMOS transistor MP 103.

The electrostatic discharge circuit 102 is composed of an electrostatic discharge transistor, in fig. 1, the electrostatic discharge transistor is an NMOS transistor MN104, and the NMOS transistor MN104 is connected between the IO port and the ground, that is, the source and the drain of the NMOS transistor MN104 are grounded and connected to the IO port.

The NMOS transistor MN104 is turned on when an electrostatic discharge event occurs and is used for discharging static electricity, and is turned off when the chip normally works, and in order to meet the requirement of electrostatic discharge, the size of the NMOS transistor MN104 is large, and the NMOS transistor MN104 is a large-sized NMOS transistor, that is, a bigbnmos transistor, compared to each transistor of each inverter 3 in fig. 1.

In fig. 1, a BigNMOS transistor, i.e., an NMOS transistor MN104, is a main device for electrostatic discharge. When the electrostatic discharge pulse is detected by the electrostatic detection circuit 101, the electrostatic discharge Signal ESD Signal on the gate of the bignnmos is in a "1" state, and the bignnmos is triggered to turn on, releasing the ESD current. When the circuit is in a normal working state, the electrostatic discharge signal on the BigNMOS gate is in a '0' state, the BigNMOS is closed, the circuit consumes off-state current (Ioff), and the value of the off-state current is larger because the NMOS tube MN104 is a BigNMOS tube. And now many products have higher and higher requirements for electrostatic discharge of the whole chip, more and more electrostatic discharge clamping circuits are arranged between a power supply and the ground, and the power consumption consumed by the electrostatic discharge clamping circuits in the whole chip is higher and higher.

Disclosure of Invention

The technical problem to be solved by the invention is to provide an electrostatic discharge clamping circuit which can reduce power consumption.

To solve the above technical problem, the electrostatic discharge clamping circuit provided by the present invention comprises: an electrostatic detection circuit, an electrostatic discharge circuit and a charge pump.

The static electricity detection circuit is arranged between an IO port of the chip and the ground and used for detecting static electricity at the IO port.

The electrostatic discharge circuit includes a first electrostatic discharge transistor connected between the IO port and ground.

The output end of the charge pump is connected with the grid electrode of the first electrostatic discharge transistor; the output end of the static electricity detection circuit is connected with the input end of the charge pump.

The output end of the static electricity detection circuit is further connected with the control end of a first switch, and the first switch is connected between the IO port and the grid electrode of the first static electricity discharge transistor.

Under the state that the static electricity discharge event appears, the static electricity detection circuit detects the static electricity that the IO port appears, the signal of the output of static electricity detection circuit makes charge pump stop working and will first switch opens, the gate connection IO port of first static electricity discharge transistor is switched on under the control of IO port voltage to with the static electricity of IO port is released to ground.

Under the normal operating condition of the chip, the static that does not appear at the IO port, the signal of the output of static electricity detection circuit makes the charge pump work and will the first switch closes, the grid disconnection of first electrostatic discharge transistor with the connection of IO port just the output voltage of charge pump is connected to the grid of first electrostatic discharge transistor, the output voltage of charge pump makes first electrostatic discharge transistor is in dark off-state to reduce the electric leakage of first electrostatic discharge transistor under off-state.

In a further improvement, the first esd transistor is an NMOS transistor, and the size of the first esd transistor satisfies the requirement of esd discharging in the state of occurrence of an esd event.

The charge pump is a negative-pressure charge pump, and the output voltage of the charge pump is negative pressure.

In a further improvement, the electrostatic discharge circuit further comprises a second electrostatic discharge transistor.

The second electrostatic discharge transistor is also an NMOS transistor, and the size of the second electrostatic discharge transistor meets the requirement of electrostatic discharge under the condition that an electrostatic discharge event occurs.

The source electrode of the first electrostatic discharge transistor is grounded, and the drain electrode of the first electrostatic discharge transistor is connected with the source electrode of the second electrostatic discharge transistor.

The drain of the second electrostatic discharge transistor is connected to the IO port through a second switch, and the drain of the second electrostatic discharge transistor is connected to the internal voltage source of the chip through a third switch.

In a state where an electrostatic discharge event occurs, the second switch is turned on and the third switch is turned off, so that the static electricity of the IO port is discharged to the ground through the second electrostatic discharge transistor and the first electrostatic discharge transistor which are connected in series.

And under the normal working state of the chip, the second switch is closed and the third switch is turned on, the second electrostatic discharge transistor connects the internal voltage source of the chip to the drain electrode of the first electrostatic discharge transistor, and the voltage difference between the drain electrode and the grid electrode of the first electrostatic discharge transistor is reduced by utilizing the characteristic that the voltage of the internal voltage source of the chip is smaller than the voltage of the IO port, so that the Grid Induced Drain Leakage (GIDL) of the first electrostatic discharge transistor is reduced.

In a further improvement, the static electricity detection circuit comprises a first resistor, a first capacitor, a first inverter and a second inverter.

The first end of the first resistor is connected with the IO port, the second end of the first resistor is connected with the first end of the first capacitor, and the second end of the first capacitor is grounded.

The second end of the first resistor is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is used as the output end of the static electricity detection circuit.

In a further improvement, the first inverter is a CMOS inverter and the second inverter is a CMOS inverter.

In a further improvement, the first switch is a PMOS transistor, a gate of the first switch is connected to the output terminal of the static electricity detection circuit, a source of the first switch is connected to the IO port, and a drain of the first switch is connected to the gate of the first static electricity discharge transistor.

In a further improvement, the second switch is a PMOS transistor, a gate of the second switch is connected to the output terminal of the electrostatic detection circuit, a source of the second switch is connected to the IO port, and a drain of the second switch is connected to a gate of the second electrostatic discharge transistor.

In a further improvement, the third switch is a PMOS transistor, a gate of the third switch is connected to an inverted signal of a signal at an output terminal of the electrostatic discharge detection circuit, a source of the third switch is connected to an internal voltage source of the chip, and a drain of the third switch is connected to a gate of the second electrostatic discharge transistor.

In a further improvement, the chip includes more than one power domain, an IO port ring of each power domain includes a plurality of chip submodules, one static electricity detection circuit and one charge pump are disposed in the same power domain, and the static electricity detection circuit and the charge pump are disposed in the same chip submodule as an integral module, one static electricity discharge circuit is disposed in each chip submodule in the same power domain, and in the same power domain, a signal at an output terminal of the static electricity detection circuit and an output voltage of the charge pump are both global signals and are sent to the static electricity discharge circuits of each chip submodule in the same power domain.

In a further improvement, the first electrostatic discharge transistor is a PMOS transistor, and the size of the first electrostatic discharge transistor meets the requirement of electrostatic discharge in a state of occurrence of an electrostatic discharge event;

the charge pump is a positive voltage charge pump, and the output voltage of the charge pump is positive voltage.

According to the invention, the charge pump is arranged, and the output voltage of the charge pump is provided for the grid electrode of the first electrostatic discharge transistor for discharging electrostatic current of the electrostatic discharge circuit in the working state of the chip and the deep closing of the first electrostatic discharge transistor is realized, so that the off-state leakage of the first electrostatic discharge transistor can be greatly reduced, and the power consumption of the electrostatic discharge clamping circuit can be reduced. When the electrostatic discharge event occurs, the charge pump is turned off, so the increase of the charge pump does not affect the protection capability of the electrostatic discharge clamping circuit on the electrostatic discharge of the chip.

In addition, the second electrostatic discharge transistor is arranged on the drain electrode side of the first electrostatic discharge transistor, and the second electrostatic discharge transistor can be connected with an internal voltage source of the chip to the drain electrode of the first electrostatic discharge transistor in the working state of the chip, so that the voltage difference between the drain electrode and the grid electrode of the first electrostatic discharge transistor can be reduced, the GIDL of the first electrostatic discharge transistor can be reduced, and the power consumption of the electrostatic discharge clamping circuit can be further reduced. Under the condition that the electrostatic discharge event occurs, the second electrostatic discharge transistor connects the IO port to the drain of the first electrostatic discharge transistor, so that the electrostatic discharge of the IO port through the first electrostatic discharge transistor is realized, and the protection capability of the electrostatic discharge clamping circuit on the electrostatic discharge of the chip is not influenced by the increase of the second electrostatic discharge transistor.

In addition, the invention can also carry on the arrangement of the electrostatic discharge clamping circuit according to the power domain of the chip, only need to set up a static detection circuit and charge pump in a power domain, and the electrostatic discharge circuit needs to set up to every chip submodule piece in the power domain, because only need to set up a charge pump in a power domain, for needing to set up the situation of the charge pump in every chip submodule piece, the invention can reduce the power consumption that the charge pump itself brings to the maximum extent.

Therefore, the invention can reduce the function of the electrostatic discharge clamping circuit, and simultaneously can not influence the protection capability of the electrostatic discharge clamping circuit on the electrostatic discharge of the chip.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of a conventional electrostatic discharge clamp;

fig. 2 is a circuit diagram of an electrostatic discharge clamp according to an embodiment of the invention.

Detailed Description

As shown in fig. 2, the circuit diagram of the electrostatic discharge clamping circuit according to the embodiment of the present invention is shown, and the electrostatic discharge clamping circuit according to the embodiment of the present invention includes: an electrostatic detection circuit, an electrostatic discharge circuit 2 and a charge pump 3. In fig. 1, the electrostatic detection circuit and the charge pump 3 are shown as an integral module and indicated by a dashed box 1.

The static electricity detection circuit is arranged between an IO port of the chip and the ground and used for detecting static electricity at the IO port. The voltage at the IO port in fig. 2, i.e., the IO port voltage, is represented by VDDIO.

The electrostatic discharge circuit 2 includes a first electrostatic discharge transistor MN0, and the first electrostatic discharge transistor MN0 is connected between the IO port and ground.

The output end of the charge pump 3 is connected to the gate of the first electrostatic discharge transistor MN0, and the voltage at the output end of the charge pump 3 in fig. 2 is the output voltage V4. In the embodiment of the present invention, the first esd discharging transistor MN0 is an NMOS transistor, and is therefore represented by MNO. The first electrostatic discharge transistor MN0 is sized to meet the electrostatic discharge requirements in a state where an electrostatic discharge event occurs. The Charge Pump 3 is a Negative voltage Charge Pump (Negative Charge Pump)3, and the output voltage V4 of the Charge Pump 3 is a Negative voltage. In other embodiments, this can also be: the first electrostatic discharge transistor is a PMOS (P-channel metal oxide semiconductor) transistor, and the size of the first electrostatic discharge transistor meets the requirement of electrostatic discharge under the condition that an electrostatic discharge event occurs; in this case, the charge pump 3 is a positive voltage charge pump 3, and the output voltage of the charge pump 3 is a positive voltage, and the embodiment corresponding to this situation can be obtained by performing the conversion between the PMOS transistor and the NMOS transistor according to the embodiment of the present invention, which will not be described in detail herein.

The output end of the static electricity detection circuit is connected to the input end of the charge pump 3, and the voltage at the output end of the static electricity detection circuit in fig. 2 is the voltage V3.

The output terminal of the electrostatic detection circuit, i.e. the voltage V3, is further connected to the control terminal of a first switch MP4, and the first switch MP4 is connected between the IO port and the gate of the first electrostatic discharge transistor MN 0. The first switch MP4 is a PMOS transistor, so the first switch is represented by MP4 in fig. 2. The gate of the first switch MP4 is connected to the output terminal of the electrostatic discharge detection circuit, the source of the first switch MP4 is connected to the IO port, and the drain of the first switch MP4 is connected to the gate of the first electrostatic discharge transistor MN 0.

Under the state that the static electricity discharge incident appears, the static electricity detection circuit detects the static electricity that the IO port appears, the signal of the output of static electricity detection circuit is voltage V3 and makes charge pump 3 stop working and will first switch MP4 opens, the IO port is connected and switched on under the control of IO port voltage VDDIO to the grid of first static electricity discharge transistor MN0, thereby will the static electricity of IO port is discharged to ground. It is known that, since the charge pump 3 stops operating in the state where the electrostatic discharge event occurs, the protection capability of the electrostatic discharge of the circuit is not affected after the charge pump 3 is added.

Under the normal working state of the chip, the IO port has no static electricity, the signal at the output end of the static electricity detection circuit, i.e. the voltage V3, makes the charge pump 3 work and the first switch MP4 close, the gate of the first electrostatic discharge transistor MN0 is disconnected from the IO port and the output voltage of the charge pump 3 is connected to the gate of the first electrostatic discharge transistor MN0, the output voltage V4 of the charge pump 3 makes the first electrostatic discharge transistor MN0 in the deep closing state, thereby reducing the leakage of the first electrostatic discharge transistor MN0 in the closing state; as can be seen from fig. 2, since the output voltage V4 of the charge pump 3 is negative, the negative voltage of the embodiment of the invention can make the first esd transistor MN0 turn off more tightly and the off-state leakage, i.e., Ioff, is smaller than the ground voltage shown in fig. 1.

In fig. 2, the embodiment of the present invention is further modified as follows: the electrostatic discharge circuit 2 further includes a second electrostatic discharge transistor MN 1. The second esd discharge transistor MN1 is also an NMOS transistor, and is denoted by MN 1. The second electrostatic discharge transistor MN1 is sized to meet the electrostatic discharge requirements in the state where an electrostatic discharge event occurs. The connection relationship of the electrostatic discharge circuit 2 including the second electrostatic discharge transistor MN1 is as follows: the source of the first electrostatic discharge transistor MN0 is grounded, and the drain of the first electrostatic discharge transistor MN0 is connected to the source of the second electrostatic discharge transistor MN 1.

The drain of the second esd transistor MN1 is connected to the IO port through a second switch MP0, the drain of the second esd transistor MN1 is connected to the internal voltage source of the chip through a third switch MP1, and the voltage of the internal voltage source of the chip in fig. 2, i.e., the internal voltage source voltage, is represented by VDDCORE.

In the embodiment of the present invention, the second switch MP0 is a PMOS transistor, and is represented by MP 0; the gate of the second switch MP0 is connected to the output terminal of the static electricity detection circuit, i.e. the connection voltage V3, the source of the second switch MP0 is connected to the IO port, and the drain of the second switch MP0 is connected to the gate of the second static electricity discharge transistor MN 1.

The third switch MP1 is a PMOS transistor and is represented by MP 1; the gate of the third switch MP1 is connected to the inverted signal of the signal at the output terminal of the static electricity detection circuit, and in fig. 2, the inverted signal of the signal at the output terminal of the static electricity detection circuit is the voltage V2. The source of the third switch MP1 is connected to the internal voltage source of the chip, and the drain of the third switch MP1 is connected to the gate of the second electrostatic discharge transistor MN 1.

In a state where an electrostatic discharge event occurs, the second switch MP0 is turned on and the third switch MP1 is turned off, so that the static electricity of the IO port is discharged to the ground through the second electrostatic discharge transistor MN1 and the first electrostatic discharge transistor MN0 connected in series. It is known that the addition of the second esd discharging transistor MN1 does not affect the protection capability of esd discharge of the circuit.

Under the normal working state of the chip, the second switch MP0 is turned off and the third switch MP1 is turned on, the second esd transistor MN1 connects the internal voltage source of the chip to the drain of the first esd transistor MN0, and the voltage difference between the drain and the gate of the first esd transistor MN0 is reduced by using the characteristic that the voltage VDDCORE of the internal voltage source of the chip is smaller than the voltage VDDIO of the IO port, so that the Gate Induced Drain Leakage (GIDL) of the first esd transistor MN0 is reduced, which can further reduce the off-state leakage of the first esd transistor MN0, thereby further reducing the power consumption of the circuit.

In fig. 2, the static electricity detection circuit includes a first resistor R0, a first capacitor C0, a first inverter and a second inverter.

The first end of the first resistor R0 is connected to the IO port, the second end of the first resistor R0 is connected to the first end of the first capacitor C0, and the second end of the first capacitor C0 is grounded.

In fig. 2, the second terminal of the first resistor R0 outputs a voltage V1 and is connected to the input terminal of the first inverter, the output terminal of the first inverter outputs a voltage V2 and is connected to the input terminal of the second inverter, and the output terminal of the second inverter outputs a voltage V3 as the output terminal of the static electricity detection circuit.

Preferably, the first inverter is a CMOS inverter, and the second inverter is a CMOS inverter. In fig. 2, the first inverter is formed by connecting an NMOS transistor MN2 and a PMOS transistor MP2, and the second inverter is formed by connecting an NMOS transistor MN3 and a PMOS transistor MP 3.

In the embodiment of the present invention, the chip includes more than one power domain, an IO port ring of each power domain includes a plurality of chip submodules, one static electricity detection circuit and one charge pump 3 are disposed in the same power domain, and the static electricity detection circuit and the charge pump 3 are disposed in the same chip submodule as an integral module 1, one static electricity discharge circuit 2 is disposed in each chip submodule of the same power domain, and in the same power domain, a signal at an output terminal of the static electricity detection circuit and an output voltage of the charge pump 3 are both global signals and are sent to the static electricity discharge circuit 2 of each chip submodule of the same power domain. Therefore, although the charge pump 3 itself may bring a certain power consumption, the static electricity detection circuit and the charge pump 3 are integrated into a module 1 and only arranged in the same chip sub-module of the power domain, that is, only one charge pump 3 needs to be adopted in one power domain, and compared with the case that the charge pump 3 needs to be arranged in each chip sub-module of the same power domain, the embodiment of the present invention can reduce the power consumption brought by the charge pump 3 itself to the maximum extent.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (8)

1. An electrostatic discharge clamp, comprising: an electrostatic detection circuit, an electrostatic discharge circuit and a charge pump;
the static detection circuit is arranged between an IO port of the chip and the ground and used for detecting static at the IO port;
the electrostatic discharge circuit comprises a first electrostatic discharge transistor connected between the IO port and ground;
the output end of the charge pump is connected with the grid electrode of the first electrostatic discharge transistor; the output end of the static electricity detection circuit is connected with the input end of the charge pump;
the output end of the static electricity detection circuit is also connected with the control end of a first switch, and the first switch is connected between the IO port and the grid electrode of the first static electricity discharge transistor;
when an electrostatic discharge event occurs, the electrostatic detection circuit detects the static electricity occurring at the IO port, a signal at an output end of the electrostatic detection circuit stops the charge pump and turns on the first switch, and a gate of the first electrostatic discharge transistor is connected to the IO port and is turned on under the control of the voltage of the IO port, so that the static electricity at the IO port is discharged to the ground;
under a normal working state of a chip, static electricity does not appear at the IO port, a signal at an output end of the static electricity detection circuit enables the charge pump to work and turns off the first switch, a grid electrode of the first static electricity discharge transistor is disconnected from the IO port, an output voltage of the charge pump is connected to the grid electrode of the first static electricity discharge transistor, and the output voltage of the charge pump enables the first static electricity discharge transistor to be in a deep turn-off state, so that electric leakage of the first static electricity discharge transistor in the turn-off state is reduced;
the first electrostatic discharge transistor is an NMOS transistor, and the size of the first electrostatic discharge transistor meets the requirement of electrostatic discharge under the condition that an electrostatic discharge event occurs;
the charge pump is a negative-pressure charge pump, and the output voltage of the charge pump is negative pressure;
the electrostatic discharge circuit further comprises a second electrostatic discharge transistor;
the second electrostatic discharge transistor is also an NMOS transistor, and the size of the second electrostatic discharge transistor meets the requirement of electrostatic discharge under the condition that an electrostatic discharge event occurs;
the source electrode of the first electrostatic discharge transistor is grounded, and the drain electrode of the first electrostatic discharge transistor is connected with the source electrode of the second electrostatic discharge transistor;
the grid electrode of the second electrostatic discharge transistor is connected to the IO port through a second switch, and the grid electrode of the second electrostatic discharge transistor is connected to the internal voltage source of the chip through a third switch;
in a state that an electrostatic discharge event occurs, the second switch is turned on and the third switch is turned off, so that the static electricity of the IO port is discharged to the ground through the second electrostatic discharge transistor and the first electrostatic discharge transistor which are connected in series;
under the normal working state of the chip, the second switch is closed, the third switch is turned on, the second electrostatic discharge transistor connects the internal voltage source of the chip to the drain electrode of the first electrostatic discharge transistor, and the voltage difference between the drain electrode and the grid electrode of the first electrostatic discharge transistor is reduced by utilizing the characteristic that the voltage of the internal voltage source of the chip is smaller than the voltage of the IO port, so that the grid-induced drain leakage of the first electrostatic discharge transistor is reduced.
2. The electrostatic discharge clamp of claim 1 wherein: the static electricity detection circuit comprises a first resistor, a first capacitor, a first inverter and a second inverter;
a first end of the first resistor is connected with the IO port, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded;
the second end of the first resistor is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is used as the output end of the static electricity detection circuit.
3. The electrostatic discharge clamp of claim 2 wherein: the first inverter is a CMOS inverter, and the second inverter is a CMOS inverter.
4. The electrostatic discharge clamp of claim 1, 2 or 3, wherein: the first switch is a PMOS tube, the grid electrode of the first switch is connected with the output end of the static electricity detection circuit, the source electrode of the first switch is connected with the IO port, and the drain electrode of the first switch is connected with the grid electrode of the first static electricity release transistor.
5. The electrostatic discharge clamp of claim 1, 2 or 3, wherein: the second switch is a PMOS tube, the grid electrode of the second switch is connected with the output end of the static electricity detection circuit, the source electrode of the second switch is connected with the IO port, and the drain electrode of the second switch is connected with the grid electrode of the second static electricity release transistor.
6. The electrostatic discharge clamp of claim 1, 2 or 3, wherein: the third switch is a PMOS tube, the grid electrode of the third switch is connected with the inverted signal of the signal at the output end of the static electricity detection circuit, the source electrode of the third switch is connected with the internal voltage source of the chip, and the drain electrode of the third switch is connected with the grid electrode of the second static electricity discharge transistor.
7. The electrostatic discharge clamp of any of claims 1 to 3, wherein: the chip comprises more than one power domain, an IO port ring of each power domain comprises a plurality of chip submodules, one static electricity detection circuit and one charge pump are arranged in the same power domain and are arranged in the same chip submodule as an integral module, one static electricity discharge circuit is arranged in each chip submodule of the same power domain, and in the same power domain, signals of an output end of the static electricity detection circuit and output voltages of the charge pumps are global signals and are sent to the static electricity discharge circuits of the chip submodules of the same power domain.
8. The electrostatic discharge clamp of claim 1 wherein: the first electrostatic discharge transistor is a PMOS (P-channel metal oxide semiconductor) transistor, and the size of the first electrostatic discharge transistor meets the requirement of electrostatic discharge under the condition that an electrostatic discharge event occurs;
the charge pump is a positive voltage charge pump, and the output voltage of the charge pump is positive voltage.
CN201710455287.0A 2017-06-16 2017-06-16 Electrostatic discharge clamping circuit CN107331660B (en)

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CN107331660B true CN107331660B (en) 2020-02-07

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310379B1 (en) * 1999-06-03 2001-10-30 Texas Instruments Incorporated NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors
CN102754335A (en) * 2010-01-19 2012-10-24 高通股份有限公司 High voltage, high frequency esd protection circuit for RF ICs
CN104979814A (en) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protecting circuit
CN106816865A (en) * 2017-02-08 2017-06-09 上海华虹宏力半导体制造有限公司 Esd protection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310379B1 (en) * 1999-06-03 2001-10-30 Texas Instruments Incorporated NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors
CN102754335A (en) * 2010-01-19 2012-10-24 高通股份有限公司 High voltage, high frequency esd protection circuit for RF ICs
CN104979814A (en) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protecting circuit
CN106816865A (en) * 2017-02-08 2017-06-09 上海华虹宏力半导体制造有限公司 Esd protection circuit

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