CN107329612A - A kind of scanning circuit, drive circuit and touch control display apparatus - Google Patents
A kind of scanning circuit, drive circuit and touch control display apparatus Download PDFInfo
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- CN107329612A CN107329612A CN201710516356.4A CN201710516356A CN107329612A CN 107329612 A CN107329612 A CN 107329612A CN 201710516356 A CN201710516356 A CN 201710516356A CN 107329612 A CN107329612 A CN 107329612A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
- G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of scanning circuit, drive circuit and touch control display apparatus, scanning circuit is corresponding with a pixel cell row, and scanning circuit includes:Input module, input module is used to generate scanning signal according to the open signal of access;The latch module electrically connected with input module, latch module is used to generate open signal according to scanning signal, and open signal is latched;And, the gating module electrically connected with latch module, gating module is used to carry out respective pixel cell row display scanning according to the control of open signal in the display stage, and is suspended in the touch-control stage according to the control of open signal to the progress display scanning of respective pixel cell row.By setting gating module to scanning circuit, so that scanning circuit carries out display scanning according to the control of open signal in the display stage to pixel cell row, and suspended in the touch-control stage according to the control of open signal and display scanning is carried out to pixel cell, it is ensured that the normal display of touch control display apparatus.
Description
Technical field
The present invention relates to driving display technology field, more specifically, it is related to a kind of scanning circuit, drive circuit and touches
Control display device.
Background technology
Now, the array base palte of display device is typically scanned using gate driving circuit to pixel cell, wherein, grid
Pole drive circuit is made up of the scanning circuit of multi-stage cascade, per one-level scanning circuit one pixel cell row of correspondence, to show
Display scanning is driven in journey to respective pixel cell row, while also open signal is provided for next stage scanning circuit, with complete
Into the purpose scanned step by step to pixel cell row.With the development of Display Technique, touch control display apparatus progresses into the life of people
Among living, the touch control display apparatus used at present is general that touch control display apparatus is driven using timesharing type of drive, that is, touches
The driving process of control display device is divided into display stage and touch-control stage.Wherein, the drive to pixel cell is completed in the display stage
Dynamic display scanning, and be driven scanning to touch-control structure in the touch-control stage, two stages should be independent of each other, complete independently.But
It is that existing touch control display apparatus is in the touch-control stage, and the situation for keeping display scanning often occurs in scanning circuit, that is, scans electricity
The display scanning sequence on road is not off, and causes display bad.
The content of the invention
In view of this, the invention provides a kind of scanning circuit, drive circuit and touch control display apparatus, by scanning electricity
Road sets gating module, is swept so that scanning circuit carries out display according to the control of open signal in the display stage to pixel cell row
Retouch, and suspended in the touch-control stage according to the control of open signal and display scanning is carried out to pixel cell, it is ensured that scanning circuit is being touched
The control stage stops display scanning, it is ensured that the normal display of touch control display apparatus.
To achieve the above object, the technical scheme that the present invention is provided is as follows:
A kind of scanning circuit, applied to touch control display apparatus, the touch control display apparatus includes multirow pixel cell row, institute
State scanning circuit corresponding with a pixel cell row, the scanning circuit includes:
Input module, the input module is used to generate scanning signal according to the open signal of access;
The latch module electrically connected with the input module, the latch module is used to generate institute according to the scanning signal
Open signal is stated, and the open signal is latched;
And, the gating module electrically connected with the latch module, the gating module is used in the display stage according to institute
The control for stating open signal carries out display scanning to the corresponding pixel cell row, and in the touch-control stage according to the open signal
Control pause display scanning is carried out to the corresponding pixel cell row.
Accordingly, present invention also offers a kind of drive circuit, applied to touch control display apparatus, the touch control display apparatus
Including multirow pixel cell row, the drive circuit multistage includes above-mentioned scanning circuit;
Wherein, the scanning circuit is corresponded with the pixel cell row.
Accordingly, present invention also offers a kind of touch control display apparatus, the touch control display apparatus includes above-mentioned driving
Circuit.
Compared to prior art, the technical scheme that the present invention is provided at least has advantages below:
The invention provides a kind of scanning circuit, drive circuit and touch control display apparatus, the touch control display apparatus includes
Multirow pixel cell row, the scanning circuit is corresponding with a pixel cell row, and the scanning circuit includes:Input module, it is described
Input module is used to generate scanning signal according to the open signal of access;The latch module electrically connected with the input module, institute
Stating latch module is used to generate the open signal according to the scanning signal, and the open signal is latched;And, with institute
The gating module of latch module electrical connection is stated, the gating module is used for the control pair according to the open signal in the display stage
The corresponding pixel cell row carries out display scanning, and is suspended in the touch-control stage according to the control of the open signal to corresponding institute
State pixel cell row and carry out display scanning.As shown in the above, the technical scheme that the present invention is provided, by being set to scanning circuit
Gating module is put, so that scanning circuit carries out display scanning according to the control of open signal in the display stage to pixel cell row,
And suspended in the touch-control stage according to the control of open signal and display scanning is carried out to pixel cell, it is ensured that scanning circuit is in touch-control rank
Section stops display scanning, it is ensured that the normal display of touch control display apparatus.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
A kind of structural representation for scanning circuit that Fig. 1 provides for the embodiment of the present application;
A kind of concrete structure schematic diagram for scanning circuit that Fig. 2 provides for the embodiment of the present application;
The concrete structure schematic diagram for another scanning circuit that Fig. 3 a provide for the embodiment of the present application;
A kind of image element circuit structure schematic diagram that Fig. 3 b provide for the embodiment of the present application;
A kind of timing diagram that Fig. 4 provides for the embodiment of the present application;
The concrete structure schematic diagram for another scanning circuit that Fig. 5 provides for the embodiment of the present application;
Another timing diagram that Fig. 6 provides for the embodiment of the present application;
A kind of structural representation for drive circuit that Fig. 7 provides for the embodiment of the present application;
A kind of structural representation for touch control display apparatus that Fig. 8 provides for the embodiment of the present application;
The structural representation for another touch control display apparatus that Fig. 9 provides for the embodiment of the present application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As described in background, with the development of Display Technique, the life that touch control display apparatus progresses into people is worked as
In, the touch control display apparatus used at present is general that touch control display apparatus is driven using timesharing type of drive, i.e., touch-control shows
The driving process of showing device is divided into display stage and touch-control stage.Wherein, the driving to pixel cell is completed in the display stage to show
Show scanning, and be driven scanning to touch-control structure in the touch-control stage, two stages should be independent of each other, complete independently.But, it is existing
Some touch control display apparatus are in the touch-control stage, and the situation for keeping display scanning, i.e. scanning circuit often occurs in scanning circuit
Sequential is not off, and causes display bad.
Based on this, the embodiment of the present application provides a kind of scanning circuit, drive circuit and touch control display apparatus, by sweeping
Scanning circuit sets gating module, so that scanning circuit is shown in the display stage according to the control of open signal to pixel cell row
Show scanning, and suspended in the touch-control stage according to the control of open signal and display scanning is carried out to pixel cell, it is ensured that scanning circuit
Stop display scanning in the touch-control stage, it is ensured that the normal display of touch control display apparatus.To achieve the above object, the embodiment of the present application
The technical scheme of offer is as follows, specific to carry out detailed retouch with reference to the technical scheme that Fig. 1 to Fig. 9 is provided the embodiment of the present application
State.
With reference to shown in Fig. 1, a kind of structural representation of the scanning circuit provided for the embodiment of the present application, wherein, scanning electricity
Road is applied to touch control display apparatus, and the touch control display apparatus includes multirow pixel cell row, the scanning circuit and a pixel
Cell row correspondence, the scanning circuit includes:
Input module 100, the input module 100 is used to generate scanning signal according to the open signal STV of access;
The latch module 200 electrically connected with the input module 100, the latch module 200 is used for according to the scanning
Open signal STV described in signal generation, and the open signal STV is latched;
And, the gating module 300 electrically connected with the latch module 200, the gating module 300 is used in display rank
Section carries out display scanning to the corresponding pixel cell row according to the control of the open signal, and in the touch-control stage according to described
The control pause of open signal carries out display scanning to the corresponding pixel cell row.
It should be noted that the touch control display apparatus that the embodiment of the present application is provided, it can be liquid crystal touch control display device,
It can also be organic electroluminescence display device and method of manufacturing same, this application is not specifically limited;In addition, the embodiment of the present application offer is tactile
The array base palte for controlling display device can be the array base palte using low-temperature polysilicon silicon technology, not do specific equally to this application
Limitation.
In the embodiment of the application one, when touch control display apparatus is liquid crystal display device, pixel cell row one grid of correspondence
Polar curve, wherein, scanning circuit is electrically connected with gate line, i.e., scanning circuit includes an output port;And, shown in touch-control
When device is organic electroluminescence display device and method of manufacturing same, pixel cell includes an image element circuit, and pixel cell correspondence multi-strip scanning
Line, wherein, scanning circuit electrical connection corresponding with multi-strip scanning line, i.e. scanning circuit includes multiple output ports.
As shown in the above, the technical scheme that the embodiment of the present application is provided, by setting gating module to scanning circuit,
So that scanning circuit carries out display scanning to pixel cell row in the display stage according to the control of open signal (opens scanning electricity
The display scanning sequence on road), and suspended in the touch-control stage according to the control of open signal and display scanning is carried out (i.e. to pixel cell
Suspend the display scanning sequence of scanning circuit), it is ensured that scanning circuit stops display scanning in the touch-control stage, it is ensured that touch-control display dress
The normal display put.
It is described with reference to a kind of structure of Fig. 2 to Fig. 6 specific scanning circuits provided the embodiment of the present application.
With reference to shown in Fig. 2, a kind of concrete structure schematic diagram of the scanning circuit provided for the embodiment of the present application.Wherein, originally
The input module 100 that application embodiment is provided includes:
First clocked inverter CKINV1;
The input of the first clocked inverter CKINV1 accesses the input signal STV, first clock inversion
Device CKINV1 output end is electrically connected with the latch module 200, the first control end of the first clocked inverter CKINV1
The second control end for accessing the first control signal Vk1, the first clocked inverter CKINV2 accesses the second control signal Vk2,
Wherein, the first control signal Vk1 and the second control signal Vk2 level are opposite.
In the embodiment of the application one, the first control signal Vk1 and the second control signal Vk2 can be opposite by two level
Signal wire provide respectively;Or, in order to save wire structures, due to the first control signal Vk1 and the second control signal Vk2 electricity
It is flat on the contrary, so above-mentioned two signal can be realized by a phase inverter, i.e. with reference to shown in Fig. 2, the input module 100 is also wrapped
Include:
First phase inverter INV1;
The input of the first phase inverter INV1 and the first clocked inverter CKINV1 the second control end are electrically connected
First clock signal terminal CK1, the first phase inverter INV1 output end electrically connects the first clocked inverter CKINV1's
First control end.
With reference to shown in Fig. 2, the latch module 200 that the embodiment of the present application is provided includes:
Second phase inverter INV2 and second clock phase inverter CKINV2;
The input of the second phase inverter INV2 and the second clock phase inverter CKINV2 output end are electrically connected
The input module 100, the output end of the second phase inverter INV2 and the second clock phase inverter CKINV2 input
The gating module 300 is electrically connected, the first control end of the second clock phase inverter CKINV2 accesses the 3rd control signal
Vk3, the second clock phase inverter CKINV2 the second control end access the 4th control signal Vk4, wherein, the 3rd control
Signal Vk3 and the 4th control signal Vk4 level are opposite.
In the embodiment of the application one, the 3rd control signal Vk3 and the 4th control signal Vk4 can be opposite by level signal
Two signal wires provide respectively;Or, in order to save wiring, due to the 3rd control signal Vk3's and the 4th control signal Vk4
Level signal is on the contrary, thus the 3rd control signal Vk3 and the 4th control signal Vk4 can equally be realized by a phase inverter;And
Further, in order to save number of devices, the 3rd control signal Vk3 and the 4th control signal Vk4 can be by input modules 100
First phase inverter INV1 is realized, with reference to shown in Fig. 2, when the input module 100 includes the first phase inverter INV1, its
In, the first control end of the second clock phase inverter CKINV1 electrically connects the first clock signal terminal CK1, when described second
Clock phase inverter CKINV2 the second control end electrically connects the output end of the first phase inverter INV1;
The first control end of the second clock phase inverter CKINV2 and the first of the first clocked inverter CKINV1
Effective control level of control end is identical, and, the second control end and described first of the second clock phase inverter CKINV2
Effective control level of clocked inverter CKINV1 the second control end is identical.
It should be noted that significant level is the level of control device structure conducting, such as the first clocked inverter CKINV1
The first control end with second clock phase inverter CKINV2 is low level control end, and the first clocked inverter CKINV1 and second
When clocked inverter CKINV2 the second control end is high level control end, the first control signal Vk1 and the 3rd control signal Vk3
Significant level be low level, and the second control signal Vk2 and the 4th control signal Vk4 significant level is high level,
And then control the first clocked inverter CKINV1 and second clock phase inverter CKINV2 to turn on by significant level.
With reference to shown in Fig. 2, the gating module 300 that the embodiment of the present application is provided includes:
First NAND gate 311, the 3rd phase inverter INV3 and at least one output module 320;
Wherein, the first input end of first NAND gate 311 electrically connects the latch module 200, described first with it is non-
The second input electrical connection second clock signal end CK2 of door 311, the output end electrical connection of first NAND gate 311 is described
3rd phase inverter INV3 input, the output end of the 3rd phase inverter INV3 electrically connects the output module 320, described defeated
Go out module 320 to electrically connect with the corresponding pixel cell row.
In the embodiment of the application one, the output module that the application is provided includes:Second NAND gate, described second with
The first input end of NOT gate electrically connects the output end of the 3rd phase inverter, the second input electrical connection of second NAND gate
One clock signal terminal, the corresponding pixel cell row of output end electrical connection of second NAND gate;Or,
The output module includes an output port, and the output port is by the output end of the 3rd phase inverter and accordingly
Electrically connected between the pixel cell row.
The scanning circuit provided below by taking the scanning circuit of organic electroluminescence display device and method of manufacturing same as an example the embodiment of the present application
And gating module is described in detail, with reference to shown in Fig. 3 a, another scanning circuit provided for the embodiment of the present application it is specific
Structural representation, gating module 300 includes three output modules.
Wherein, two output modules include one second NAND gate 312 and the second NAND gate 313, the second NAND gate 312
Scanning signal SCAN1 is exported to the image element circuit of pixel cell, the second NAND gate 313 exports scanning signal SCAN2 to pixel list
The image element circuit of member, and, an output module includes an output port, and output port exports scanning signal EMIT to pixel cell
Image element circuit;Wherein, the second input of the second NAND gate 312 electrically connects one the 3rd clock signal terminal CK3, the second NAND gate
313 the second input electrically connects one the 4th clock signal terminal CK4.
With reference to shown in Fig. 3 a, scanning signal SCAN1, scanning signal SCAN2 and the scanning signal exported by scanning circuit
EMIT is scanned to image element circuit.Wherein, scanning signal SCAN1 is generally used for control image element circuit and completes reseting procedure, sweeps
Signal SCAN2 is retouched to be generally used for controlling to write data-signal into image element circuit, and scanning signal EMIT is generally used for control
Connected between image element circuit and light emitting diode, and then connect negative electrode low potential, it is same as the prior art to this.
As shown in Figure 3 b, a kind of image element circuit structure schematic diagram provided for the embodiment of the present application, it is typical 8T2C
Image element circuit, i.e., be the first transistor T1 to the 8th transistor T8 including eight thin film transistor (TFT)s, and two electric capacity are the first electricity
Hold C1 and the second electric capacity C2.Wherein, in reseting procedure, scanning signal EMIT controls the 7th transistor T7 and the 8th transistor T8
During conducting, the 8th transistor T8 enables to image element circuit to connect LED, and then is connected to negative electrode low potential
PVEE, can reset to signal in image element circuit;And, in luminescence process, the first transistor T1 is conducting state, and
Scanning signal EMIT is when controlling the 7th transistor T7 and the 8th transistor T8 conductings, the 7th transistor T7 and the 8th transistor T8
Anode voltage PVDD is connected by LED with negative electrode low potential PVEE jointly with the first transistor T1 so that hair
Optical diode PVEE lights.
Scanning signal SCAN1, can be by reference signal REF when controlling second transistor T2 and third transistor T3 conductings
Transmit to the first transistor T1 of image element circuit grid, and then image element circuit is resetted (i.e. to the first transistor T1's
Grid is resetted).And, scanning signal SCAN2 controls the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6 to lead
It is logical, to ensure in data-signal DATA normal transmissions to the first transistor T1, i.e. writing pixel circuit.
The course of work of the corresponding scanning circuits of the embodiment of the present application Fig. 3 a is described in detail with reference to timing diagram.
Wherein, describe to illustrate so that the transistor of image element circuit is P-type TFT as an example below, wherein, the first clock signal
CK1 and second clock signal end CK2 is held to export clock signal phase on the contrary, the 3rd clock signal terminal CK3 and the 4th clock signal
CK4 is held to export the opposite in phase of clock signal.With reference to shown in Fig. 4, a kind of timing diagram provided for the embodiment of the present application drove
Journey is divided into display stage and touch-control stage, wherein, display the stage include first stage T1, second stage T2, phase III T3 and
Fourth stage T4.With reference to shown in Fig. 3 a and Fig. 4:
T1 in the first stage:The open signal STV of high level is inputted to the first clocked inverter of input module 100
CKINV1 input;Now the first clock signal terminal CK1 exports high level signal, to be changed after the first phase inverter INV1
For low level signal, then the high level signal and low level signal control the first clocked inverter CKINV1 conductings, and first
Open signal STV is converted to low level signal output by clocked inverter CKINV1;Then the first clocked inverter CKINV1 is defeated
The low level signal gone out is exported after the second phase inverter INV2 in the open signal STV of high level;
Now second clock signal end CK2 exports low level signal, and the low level signal and the second phase inverter INV2 are exported
The open signal STV of high level generate high level signal after the first NAND gate 311, again pass by the 3rd phase inverter INV3
After generate low level signal, the low level signal is output as scanning signal EMIT by output port, to control image element circuit to enter
Row resets;And, because the 3rd phase inverter INV3 exports low level signal, thus by the second NAND gate 312 and the 3rd with it is non-
It is high level signal that high level signal, i.e. scanning signal SCAN1 and scanning signal SCAN2 are converted into after door 313, and control with
Its connected thin film transistor (TFT) cut-off.
In second stage T2:First clock signal terminal CK1 exports low level signal and controls second clock phase inverter
CKINV2 is turned on, and open signal STV is realized by second clock phase inverter CKINV2 and the second phase inverter INV2 circulations and latched;This
When second clock signal end CK2 output high level signal and cause the first NAND gate 311 output low level signal, it is anti-by the 3rd
High level signal is converted to after phase device INV3, the high level signal is scanning signal EMIT by output port so that with output
The thin film transistor (TFT) cut-off of port connection;And now the 3rd clock signal terminal CK3 exports high level signal so that the second NAND gate
The scanning signal SCAN1 of 312 output low level signals, and then image element circuit is resetted;And the 4th clock signal terminal CK4 is defeated
Go out low level signal so that the second NAND gate 313 exports the scanning signal SCAN2 of high level signal.
In phase III T3:First clock signal terminal CK1 keeps low level signal output, and scanning signal EMIT level is constant
It is identical with second stage T2, and the 3rd clock signal terminal CK3 output low level signals so that the second NAND gate 312 exports high electricity
The scanning signal SCAN1 of ordinary mail number;And the 4th clock signal terminal CK4 output high level signals so that the second NAND gate 313 is exported
The scanning signal SCAN2 of low level signal, and then by data-signal writing pixel circuit.
In fourth stage T4:First clock signal terminal CK1 output high level signals, and now the first clocked inverter INV1
High level signal output is converted to after access low level signal, low level signal is exported after the second phase inverter INV2;This is low
Level signal is high level signal after the first NAND gate 311, and low level is converted to after again passing by the 3rd phase inverter INV3
Signal output, so that scanning signal EMIT is low level signal, and then controls image element circuit to be connected with light emitting diode, and is connected
Make lumination of light emitting diode to negative electrode low potential.
And at the touch-control stage, then stop the sequential of scanning display, i.e. because scanning circuit completes to show sweep phase
Afterwards, its latch module 200 is output as low level signal, thus, in touch-control stage control the first clock signal terminal CK1 to the 4th
(when i.e. control shows that scanning sequence stops, low level signal is exported when clock signal end CK4 stops), and the 3rd phase inverter INV3 is defeated
The signal gone out is still low level signal, and then causes the second NAND gate 312 and the 3rd NAND gate 313 to keep output high level letter
Number, and scanning signal EMIT keeps image element circuit to connect light emitting diode for low level signal, light emitting diode is normally sent out
Light, it is ensured that touch control display apparatus is normally shown in the touch-control stage.
Further, in order to improve the driving force of scanning signal, the output module that the embodiment of the present application is provided is also
Including:At least one buffer cell;
Between second NAND gate and the corresponding pixel cell row and/or the output port and the corresponding pixel
Buffer cell described in electrical connection one is corresponded between cell row respectively.
In the embodiment of the application one, gating module can also be other structures mode, as the embodiment of the present application is provided
The gating module includes:At least one three end input nand gate and/or at least one the 3rd NAND gate, at least one is the 4th anti-
Phase device and gating clock signal end;
The first input end of three end input nand gate electrically connects the latch module, three end input nand gate
Second input electrically connects a clock signal terminal, and the 3rd input of three end input nand gate electrically connects the gated clock
Signal end;
The first input end of 3rd NAND gate electrically connects the latch module, the second input of the 3rd NAND gate
The end electrical connection gating clock signal end, the output end and the input of one the 4th phase inverter of the 3rd NAND gate are electrically connected
Connect, the 3rd NAND gate is corresponded with the 4th phase inverter.
The same scanning provided by taking the scanning circuit of organic electroluminescence display device and method of manufacturing same as an example the embodiment of the present application below
Circuit and gating module are described in detail, with reference to shown in Fig. 5, the tool of another scanning circuit provided for the embodiment of the present application
Body structural representation, wherein, gating module 300 includes:
Three end input nand gates 331, three end input nand gates 332, the 3rd NAND gate 340 and the 4th phase inverter INV4 and
Gating clock signal end CKx;
The first input end electrical connection latch module 200 of three end input nand gates 331 and three end input nand gates 332, three
The second input of input nand gate 331 is held to electrically connect the 5th clock signal terminal CK5, the second of three end input nand gates 332 is defeated
Access port electrically connects the 6th clock signal terminal CK6, the 3rd input of three end input nand gates 331 and three end input nand gates 332
End electrical connection gating clock signal end CKx;
The first input end electrical connection latch module 200 of 3rd NAND gate 340, the second input of the 3rd NAND gate 340
Gating clock signal end CKx is electrically connected, the output end of the 3rd NAND gate 340 electrically connects the 4th phase inverter INV4 input.Its
In, the output signal of three end input nand gates 331 is scanning signal SCAN1, and the output signal of three end input nand gates 332 is to sweep
Signal SCAN2 is retouched, and, the 4th phase inverter INV4 output signal is scanning signal EMIT.
The course of work of the corresponding scanning circuits of the embodiment of the present application Fig. 5 is described in detail with reference to timing diagram,
It should be noted that the image element circuit for the pixel cell that the application is provided is same as the prior art, therefore unnecessary repeat is not done;This
Outside, describe to illustrate so that the transistor of image element circuit is P-type TFT as an example below, wherein, the first clock signal terminal
CK1 and gating clock signal end CKx exports clock signal phase on the contrary, the 5th clock signal terminal CK5 and the 6th clock signal terminal
CK6 exports the opposite in phase of clock signal.With reference to shown in Fig. 6, another timing diagram provided for the embodiment of the present application drove
Journey is divided into display stage and touch-control stage, wherein, display the stage include first stage T1, second stage T2, phase III T3 and
Fourth stage T4.With reference to shown in Fig. 5 and Fig. 6:
T1 in the first stage:The open signal STV of high level is inputted to the first clocked inverter of input module 100
CKINV1 input;Now the first clock signal terminal CK1 exports high level signal, to be changed after the first phase inverter INV1
For low level signal, then the high level signal and low level signal control the first clocked inverter CKINV1 conductings, and first
Open signal STV is converted to low level signal output by clocked inverter CKINV1;Then the first clocked inverter CKINV1 is defeated
The low level signal gone out is exported after the second phase inverter INV2 in the open signal STV of high level;
Now gating clock signal end CKx export low level signal, thus three end input nand gates 331, three ends input with
The NAND gate 340 of NOT gate 332 and the 3rd exports high level signal so that scanning signal SCAN1 and scanning signal SCAN2 is high electricity
Ordinary mail number, and the 3rd NAND gate 340 transmits high level signal to the 4th phase inverter INV4 the scanning of output high level signal
Signal EMIT, and then control image element circuit to be resetted.
In second stage T2:First clock signal terminal CK1 exports low level signal and controls second clock phase inverter
CKINV2 is turned on, and open signal STV is realized by second clock phase inverter CKINV2 and the second phase inverter INV2 circulations and latched;This
When gating clock signal end CKx output high level signal so that the 3rd NAND gate 340 export low level signal, it is anti-by the 4th
The scanning signal EMIT of high level signal is exported after phase device INV4;In addition, the 5th clock signal terminal CK5 exports high level signal,
And make it that three end input nand gates 331 export the scanning signal SCAN1 of low level signal, and then image element circuit is resetted;
And the 6th clock signal terminal CK4 output low level signals so that the scanning letter of three end input nand gates 332 output high level signal
Number SCAN2.
In phase III T3:First clock signal terminal CK1 keeps low level signal output, and scanning signal EMIT level is constant
It is identical with second stage T2, and the 5th clock signal terminal CK5 output low level signals so that three end input nand gates 331 are exported
The scanning signal SCAN1 of high level signal;And the 6th clock signal terminal CK6 output high level signal so that three ends input with it is non-
Door 332 exports the scanning signal SCAN2 of low level signals, and then by data-signal writing pixel circuit.
In fourth stage T4:First clock signal terminal CK1 output high level signals, and now the first clocked inverter INV1
High level signal output is converted to after access low level signal, low level signal is exported after the second phase inverter INV2;This is low
Level signal controls three end input nand gates 331, three end input nand gates 332 and the 3rd NAND gate 340 to export high level letter
Number, and the 4th phase inverter INV4 exports the high level signal scanning signal EMIT of low level signal after anti-phase, and then control
Image element circuit is connected with light emitting diode, and being connected to negative electrode low potential makes lumination of light emitting diode.
And at the touch-control stage, then stop the sequential of scanning display, i.e. because scanning circuit completes to show sweep phase
Afterwards, its latch module 200 is output as low level signal, thus, in the first clock signal terminal of touch-control stage control CK1, gating
(i.e. control shows that scanning sequence stops when clock signal end CKx, the 5th clock signal terminal CK5 and the 6th clock signal terminal CK6 stop
When only), three end input nand gates 331, three end input nand gates 332 and the 3rd NAND gate 340 export high level signal, and
The scanning signal EMIT of high level signal output low level signal after anti-phase is kept image element circuit by four phase inverter INV4
Light emitting diode is connected, makes light emitting diode normal luminous, it is ensured that touch control display apparatus is normally shown in the touch-control stage.
It should be noted that the concrete structure for the scanning circuit that the embodiment of the present application is provided is not limited to above-mentioned offer
Two kinds of particular circuit configurations, in the application other embodiment, scanning circuit can also be other particular circuit configurations, to this
Application is not particularly limited.
Accordingly, the embodiment of the present application additionally provides a kind of drive circuit, applied to touch control display apparatus, and the touch-control shows
Showing device includes multirow pixel cell row, and the drive circuit multistage includes above-mentioned scanning circuit;
Wherein, the scanning circuit is corresponded with the pixel cell row.
With reference to shown in Fig. 7, a kind of driving circuit structure schematic diagram provided for the embodiment of the present application, wherein, drive circuit
Including multilevel scanning circuit SR1 to SRn, electricity is scanned described in the output of the latch module of scanning circuit described in upper level and next stage
The input electrical connection of the input module on road.
Wherein, the external open signal STV of the input of first order scanning circuit SR1 input module.
Accordingly, the embodiment of the present application additionally provides a kind of touch control display apparatus, and the touch control display apparatus includes above-mentioned
Drive circuit.
With reference to shown in Fig. 8, a kind of structural representation of the touch control display apparatus provided for the embodiment of the present application, wherein, touch
Controlling display device includes drive circuit 400, and drive circuit is arranged at the frame region of touch control display apparatus.
In addition, the drive circuit that the embodiment of the present application is provided is further divided into two sub- drive circuits, it is respectively arranged at tactile
The opposite end of display device frame is controlled, and then narrow frame design can be realized, is that the embodiment of the present application is carried with reference to shown in Fig. 9
The structural representation of another touch control display apparatus supplied, wherein, touch control display apparatus includes drive circuit, and drive circuit is divided into
The first sub- drive circuit 420 of sub- drive circuit 410 and second, the first sub- drive circuit 420 of sub- drive circuit 410 and second is distinguished
It is arranged at the frame region opposite sides of touch control display apparatus.
The first sub- drive circuit that the embodiment of the present application is provided can scan odd level pixel cell row, and the second son drives
Circuit can scan even level pixel cell row, this application is not particularly limited, it is necessary to be carried out according to practical application specific
Design.
The embodiment of the present application provides a kind of scanning circuit, drive circuit and touch control display apparatus, the touch-control display dress
Put including multirow pixel cell row, the scanning circuit is corresponding with a pixel cell row, and the scanning circuit includes:Input mould
Block, the input module is used to generate scanning signal according to the open signal of access;The latch electrically connected with the input module
Module, the latch module is used to generate the open signal according to the scanning signal, and the open signal is latched;With
And, the gating module electrically connected with the latch module, the gating module is used in the display stage according to the open signal
Control display scanning is carried out to the corresponding pixel cell row, and suspended in the touch-control stage according to the control of the open signal
Display scanning is carried out to the corresponding pixel cell row.As shown in the above, the technical scheme that the embodiment of the present application is provided, leads to
Cross to scanning circuit set gating module so that scanning circuit display the stage according to the control of open signal to pixel cell row
Display scanning is carried out, and is suspended in the touch-control stage according to the control of open signal and display scanning is carried out to pixel cell, it is ensured that is swept
Scanning circuit stops display scanning in the touch-control stage, it is ensured that the normal display of touch control display apparatus.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (12)
1. a kind of scanning circuit, applied to touch control display apparatus, the touch control display apparatus includes multirow pixel cell row, described
Scanning circuit is corresponding with a pixel cell row, it is characterised in that the scanning circuit includes:
Input module, the input module is used to generate scanning signal according to the open signal of access;
The latch module electrically connected with the input module, the latch module is used to open according to scanning signal generation
Signal is opened, and the open signal is latched;
And, the gating module electrically connected with the latch module, the gating module is used to open according in the display stage
The control for opening signal carries out display scanning to the corresponding pixel cell row, and in control of the touch-control stage according to the open signal
System pause carries out display scanning to the corresponding pixel cell row.
2. scanning circuit according to claim 1, it is characterised in that the input module includes:First clocked inverter;
The input of first clocked inverter accesses the input signal, the output end of first clocked inverter and institute
Latch module electrical connection is stated, the first control end of first clocked inverter accesses the first control signal, first clock
Second control end of phase inverter accesses the second control signal, wherein, the level of first control signal and the second control signal
Conversely.
3. scanning circuit according to claim 2, it is characterised in that the input module also includes:First phase inverter;
The input of first phase inverter and the second control end of the first clocked inverter electrically connect the first clock signal terminal,
The output end of first phase inverter electrically connects the first control end of first clocked inverter.
4. the scanning circuit according to claims 1 to 3 any one, it is characterised in that the latch module includes:Second
Phase inverter and second clock phase inverter;
The output end of the input of second phase inverter and the second clock phase inverter electrically connects the input module, institute
State the output end of the second phase inverter and the input of the second clock phase inverter electrically connects the gating module, described second
First control end of clocked inverter accesses the 3rd control signal, the second control end access the 4th of the second clock phase inverter
Control signal, wherein, the level of the 3rd control signal and the 4th control signal is opposite.
5. scanning circuit according to claim 4, it is characterised in that include described first in the input module anti-phase
During device, wherein, the first control end of the second clock phase inverter electrically connects first clock signal terminal, the second clock
Second control end of phase inverter electrically connects the output end of first phase inverter;
Effective control of first control end of the second clock phase inverter and the first control end of first clocked inverter
Level is identical, and, the second control end of the second clock phase inverter and the second control end of first clocked inverter
Effective control level it is identical.
6. scanning circuit according to claim 1, it is characterised in that the gating module includes:First NAND gate, the 3rd
Phase inverter and at least one output module;
Wherein, the first input end of first NAND gate electrically connects the latch module, and the second of first NAND gate is defeated
Enter end electrical connection second clock signal end, the output end of first NAND gate electrically connects the input of the 3rd phase inverter,
The output end of 3rd phase inverter electrically connects the output module, and the output module is electrically connected with the corresponding pixel cell row
Connect.
7. scanning circuit according to claim 6, it is characterised in that the output module includes:Second NAND gate, it is described
The first input end of second NAND gate electrically connects the output end of the 3rd phase inverter, the second input of second NAND gate
Electrically connect a clock signal terminal, the corresponding pixel cell row of output end electrical connection of second NAND gate;Or,
The output module includes an output port, and the output port is described by the output end of the 3rd phase inverter and accordingly
Electrically connected between pixel cell row.
8. scanning circuit according to claim 7, it is characterised in that the output module also includes:At least one buffering
Unit;
Between second NAND gate and the corresponding pixel cell row and/or the output port and the corresponding pixel cell
Buffer cell described in electrical connection one is corresponded between row respectively.
9. scanning circuit according to claim 1, it is characterised in that the gating module includes:At least one three end is defeated
Enter NAND gate and/or at least one the 3rd NAND gate, at least one the 4th phase inverter and gating clock signal end;
The first input end of three end input nand gate electrically connects the latch module, the second of three end input nand gate
Input electrically connects a clock signal terminal, and the 3rd input of three end input nand gate electrically connects the gating clock signal
End;
The first input end of 3rd NAND gate electrically connects the latch module, the second input electricity of the 3rd NAND gate
The gating clock signal end is connected, the output end of the 3rd NAND gate is electrically connected with the input of one the 4th phase inverter, institute
The 3rd NAND gate is stated to correspond with the 4th phase inverter.
10. a kind of drive circuit, applied to touch control display apparatus, the touch control display apparatus includes multirow pixel cell row, its
It is characterised by, the drive circuit multistage includes the scanning circuit described in claim 1~9 any one;
Wherein, the scanning circuit is corresponded with the pixel cell row.
11. drive circuit according to claim 9, it is characterised in that the latch module of scanning circuit described in upper level
Output is electrically connected with the input of the input module of scanning circuit described in next stage.
12. a kind of touch control display apparatus, it is characterised in that the touch control display apparatus includes the driving electricity described in claim 11
Road.
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CN201710516356.4A CN107329612B (en) | 2017-06-29 | 2017-06-29 | Scanning circuit, driving circuit and touch display device |
US15/724,167 US10345940B2 (en) | 2017-06-29 | 2017-10-03 | Scanning circuit, drive circuit and touch display device |
DE102017124159.0A DE102017124159A1 (en) | 2017-06-29 | 2017-10-17 | DESCENT SWITCH, DRIVER SWITCH AND TOUCH DISPLAY DEVICE |
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Also Published As
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US10345940B2 (en) | 2019-07-09 |
CN107329612B (en) | 2020-04-21 |
DE102017124159A1 (en) | 2019-01-03 |
US20190004643A1 (en) | 2019-01-03 |
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